MC908MR16CFUE

MC68HC908MR8
Technical Data
M68HC08
Microcontrollers
Rev. 4.1
MC68HC908MR8/D
August 16, 2005
freescale.com
MC68HC908MR8
Technical Data — Rev 4.0
Freescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Freescale data sheets
and/or specifications can and do vary in different applications and actual performance
may vary over time. All operating parameters, including "Typicals" must be validated
for each customer application by customer's technical experts. Freescale does not
convey any license under its patent rights nor the rights of others. Freescale products
are not designed, intended, or authorized for use as components in systems intended
for surgical implant into the body, or other applications intended to support or sustain
life, or for any other application in which the failure of the Freescale product could
create a situation where personal injury or death may occur. Should Buyer purchase or
use Freescale products for any such unintended or unauthorized application, Buyer
shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Freescale was negligent regarding the design or manufacture of the part.
Freescale, Inc. is an Equal Opportunity/Affirmative Action Employer.
© Freescale, Inc., 2005
MC68HC908MR8 — Rev 4.1 Technical Data
Freescale Semiconductor 3
Technical Data MC68HC908MR8 — Rev 4.1
4 Freescale Semiconductor
Technical Data — MC68HC908MR8
List of Paragraphs
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 29

Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Section 3. Random-Access Memory (RAM) . . . . . . . . . . 53
Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . 55
Section 5. Configuration Register (CONFIG) . . . . . . . . . 67
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 71
Section 7. System Integration Module (SIM) . . . . . . . . . 89
Section 8. Clock Generator Module (CGM) . . . . . . . . . . 111
Section 9. Pulse-Width Modulator for Motor Control
(PWMMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 187
Section 11. Timer Interface A (TIMA). . . . . . . . . . . . . . . 199
Section 12. Timer Interface B (TIMB). . . . . . . . . . . . . . . 223
Section 13. Serial Communications Interface (SCI) . . . 247
Section 14. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 279
Section 15. Computer Operating Properly (COP) . . . . 291
Section 16. External Interrupt (IRQ) . . . . . . . . . . . . . . . 297
Section 17. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . 305
Section 18. Analog-to-Digital Converter (ADC) . . . . . . 311
Section 19. Power-On Reset (POR) . . . . . . . . . . . . . . . 327
Freescale Semiconductor List of Paragraphs 5

List of Paragraphs
Section 20. Break (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . 329

Section 21. Electrical Specifications. . . . . . . . . . . . . . . 339
Section 22. Mechanical Specifications . . . . . . . . . . . . . 351
Section 23. Ordering Information . . . . . . . . . . . . . . . . . 355
Technical Data — Revision History . . . . . . . . . . . . . . . . 357
6 List of Paragraphs Freescale Semiconductor

Table of Contents
Section 1. General Description

1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.5.1 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . . 34
1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 34
1.5.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.5.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.5.5 CGM Power Supply Pins (VDDA and VSSA) . . . . . . . . . . . . . 35
1.5.6 ADC Reference Voltage Input Pin (VREFH) . . . . . . . . . . . . . 35
1.5.7 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . 35
1.5.8 Port A Input/Output (I/O) Pins (PTA6/ATD6–PTA0/ATD0). . 35
1.5.9 Port B I/O Pins (PTB6/TCHB1–PTB0/RxD) . . . . . . . . . . . . . 36
1.5.10 Port C I/O Pins (PTC1/FAULT1–PTC0/FAULT4). . . . . . . . . 36
1.5.11 PWM Pins (PWM6–PWM1) . . . . . . . . . . . . . . . . . . . . . . . . . 36
Section 2. Memory Map

2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 38
2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.5 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.6 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Freescale Semiconductor Table of Contents 7

Table of Contents
Section 3. Random-Access Memory (RAM)

3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Section 4. FLASH Memory

4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.2 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.2.3 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . 58
4.2.4 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.5 FLASH Program/Read Operation. . . . . . . . . . . . . . . . . . . . .59
4.3 FLASH Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3.1 FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.3.2 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 63
4.3.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3.3.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3.3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Section 5. Configuration Register (CONFIG)

5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3 CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.4 CONFIG Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Section 6. Central Processor Unit (CPU)

6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8 Table of Contents Freescale Semiconductor

Table of Contents
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Section 7. System Integration Module (SIM)

7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 93
7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . 93
7.3.3 Clocks in Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 94
7.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 95
7.4.2.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . 97
7.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . 98
7.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . 99
7.5.2 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . . 99
7.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.6.3 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 103
7.7 Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Table of Contents
7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

7.7.3 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.7.4 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . 108
7.7.5 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .109
Section 8. Clock Generator Module (CGM)

8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
8.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .113
8.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . 115
8.4.2.1 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.4.2.2 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . 118
8.4.2.3 Manual and Automatic PLL Bandwidth Modes . . . . . . . 118
8.4.2.4 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 120
8.4.2.5 Special Programming Exceptions . . . . . . . . . . . . . . . . . 121
8.4.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . 121
8.4.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . 122
8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . 123
8.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . 123
8.5.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . 123
8.5.4 PLL Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . 124
8.5.5 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . 124
8.5.6 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . 124
8.5.7 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . . 124
8.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . 124
8.6 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
8.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . 129
8.6.3 PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . . 131
8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
8.8 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
8.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table of Contents
8.10 CGM During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

8.11 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 134
8.11.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .134
8.11.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . . 135
8.11.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . 136
8.11.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . . 137

(PWMMC)
9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
9.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.4 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.4.1 Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
9.4.2 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9.5 PWM Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9.5.1 Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
9.5.2 PWM Data Overflow and Underflow Conditions. . . . . . . . . 152
9.6 Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
9.6.1 Selecting Six Independent PWMs or Three Complementary
PWM Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
9.6.2 Dead-Time Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
9.6.3 Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
9.6.4 Output Port Control Register . . . . . . . . . . . . . . . . . . . . . . .159
9.7 Fault Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9.7.1 Fault Condition Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . 164
9.7.1.1 Fault Pin Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
9.7.1.2 Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
9.7.1.3 Manual Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
9.7.2 Software Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . 168
9.7.3 Output Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
9.8 Initialization and the PWMEN Bit . . . . . . . . . . . . . . . . . . . . . . 169
9.9 PWM Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . 170
9.10 PWM Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . 170
9.11 PWM Operation in Break Mode . . . . . . . . . . . . . . . . . . . . . . .171

Table of Contents
9.12 Control Logic Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

9.12.1 PWM Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .172
9.12.2 PWM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . 173
9.12.3 PWMx Value Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
9.12.4 PWM Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . .175
9.12.5 PWM Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . .177
9.12.6 Dead-Time Write-Once Register . . . . . . . . . . . . . . . . . . . . 179
9.12.7 PWM Disable Mapping Write-Once Register . . . . . . . . . . . 179
9.12.8 Fault Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
9.12.9 Fault Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
9.12.10 Fault Acknowledge Register. . . . . . . . . . . . . . . . . . . . . . . . 182
9.12.11 PWM Output Control Register . . . . . . . . . . . . . . . . . . . . . . 184
9.13 PWM Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Section 10. Monitor ROM (MON)

10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
10.4.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
10.4.3 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
10.4.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
10.4.5 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
10.4.6 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
10.4.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
10.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Section 11. Timer Interface A (TIMA)

11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
11.4.1 TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .204
11.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table of Contents
11.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

11.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 206
11.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .206
11.4.4 Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 207
11.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 208
11.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 209
11.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
11.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
11.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
11.7 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
11.8 TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 212
11.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
11.9.1 TIMA Clock Pin (PTB2/TCLKA) . . . . . . . . . . . . . . . . . . . . . 213
11.9.2 TIMA Channel I/O Pins (PTB3/TCH0A–PTB4/TCH1A) . . . 213
11.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
11.10.1 TIMA Status and Control Register . . . . . . . . . . . . . . . . . . . 214
11.10.2 TIMA Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .216
11.10.3 TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . 217
11.10.4 TIMA Channel Status and Control Registers . . . . . . . . . . . 218
11.10.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Section 12. Timer Interface B (TIMB)

12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
12.4.1 TIMB Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .228
12.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
12.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
12.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 230
12.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .231
12.4.4 Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 231
12.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 232
12.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 233
12.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Table of Contents
12.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

12.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
12.7 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
12.8 TIMB During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 236
12.9 TIMB Channel I/O Pins (PTB5/TCH0B–PTB6/TCH1B) . . . . . 237
12.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
12.10.1 TIMB Status and Control Register . . . . . . . . . . . . . . . . . . . 237
12.10.2 TIMB Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .240
12.10.3 TIMB Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . 241
12.10.4 TIMB Channel Status and Control Registers . . . . . . . . . . . 242
12.10.5 TIMB Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Section 13. Serial Communications Interface (SCI)

13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
13.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
13.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
13.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
13.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 252
13.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
13.4.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
13.4.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . . 255
13.4.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .255
13.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
13.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.4.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
13.4.3.5 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
13.4.3.6 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
13.4.3.7 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
13.5 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
13.6 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Table of Contents
13.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .262

13.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
13.8.1 PTE2/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . 263
13.8.2 PTB0/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . 263
13.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
13.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
13.9.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
13.9.5 SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
13.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
13.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Section 14. Input/Output (I/O) Ports

14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
14.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
14.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
14.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . 282
14.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
14.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
14.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . 285
14.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
14.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
14.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . 288
Section 15. Computer Operating Properly (COP)

15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
15.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
15.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
15.4.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
15.4.4 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Table of Contents
15.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

15.4.6 COP Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
15.5 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
15.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
15.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
15.8 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
15.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
15.10 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 295
Section 16. External Interrupt (IRQ)

16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
16.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
16.6 IRQ Module During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . 302
16.7 IRQ Module During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . 302
16.8 IRQ Module During Break Mode. . . . . . . . . . . . . . . . . . . . . . . 302
16.9 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 303
Section 17. Low-Voltage Inhibit (LVI)

17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
17.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
17.4.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .307
17.4.3 False Reset Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
17.4.4 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
17.5 LVI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . 308
17.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
17.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

Table of Contents
17.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Section 18. Analog-to-Digital Converter (ADC)

18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
18.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
18.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
18.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
18.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
18.4.5 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
18.4.6 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
18.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
18.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
18.7 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
18.8.1 ADC Voltage Reference Pin (VREFH) . . . . . . . . . . . . . . . . . 317
18.8.2 ADC Voltage In (ADVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . 318
18.8.3 ADC External Connection . . . . . . . . . . . . . . . . . . . . . . . . . 318
18.8.3.1 VREFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
18.8.3.2 ANx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
18.8.3.3 Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
18.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
18.9.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .319
18.9.2 ADC Data Register High . . . . . . . . . . . . . . . . . . . . . . . . . . 322
18.9.3 ADC Data Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . .323
18.9.4 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Section 19. Power-On Reset (POR)

19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Table of Contents
Section 20. Break (BRK)

20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
20.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 330
20.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .332
20.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 332
20.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 332
20.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
20.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
20.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
20.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
20.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . 333
20.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 334
20.6.3 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 336
20.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 337
Section 21. Electrical Specifications

21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
21.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 340
21.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 341
21.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
21.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 343
21.7 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
21.8 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
21.9 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 346
21.10 Clock Generation Module Component Specifications . . . . . . 347
21.11 CGM Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .347
21.12 CGM Acquisition/Lock Time Specifications . . . . . . . . . . . . 348
21.13 Analog-to-Digital Converter (ADC) Characteristics. . . . . . . . . 349

Table of Contents
Section 22. Mechanical Specifications

22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
22.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
22.3 32-Pin LQFP (Case #873A) . . . . . . . . . . . . . . . . . . . . . . . . . . 352
22.4 28-Pin PDIP (Case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
22.5 28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . .353
Section 23. Ordering Information

23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
23.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
23.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Technical Data — Revision History

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Changes from Rev 3.0 published in April 2002 to Rev 4.0 pub-
lished in July 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

Table of Contents

List of Figures
Figure Title Page
1-1 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1-2 QFP and DIP/SOIC Pin Assignments . . . . . . . . . . . . . . . . . 33
1-3 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2-1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2-2 Control, Status, and Data Registers. . . . . . . . . . . . . . . . . . . 41
4-1 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . 57
4-2 FLASH Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . 61
4-3 FLASH Block Protect Register (FLBPR) . . . . . . . . . . . . . . . 63
4-4 FLASH Block Protect Address . . . . . . . . . . . . . . . . . . . . . . . 64
5-1 CONFIG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6-1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6-3 Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6-6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . 76
7-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7-2 SIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 92
7-3 CGM Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7-6 Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7-8 Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7-9 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7-10 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . 103
Freescale Semiconductor List of Figures 21

List of Figures
7-12 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .104

7-13 Wait Recovery from Interrupt or Break. . . . . . . . . . . . . . . . 105
7-14 Wait Recovery from Internal Reset . . . . . . . . . . . . . . . . . . 105
7-15 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . 106
7-16 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . 108
7-17 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . 109
8-1 CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8-2 CGM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .115
8-3 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . 123
8-4 CGM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .125
8-5 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . 126
8-6 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . 129
8-7 PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . 131
9-1 PWM Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 141
9-2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9-3 Center-Aligned PWM (Positive Polarity). . . . . . . . . . . . . . . 147
9-4 Edge-Aligned PWM (Positive Polarity) . . . . . . . . . . . . . . . . 147
9-5 Reload Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . 149
9-6 PWM Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . 150
9-7 Center-Aligned PWM Value Loading . . . . . . . . . . . . . . . . . 150
9-8 Center-Aligned Loading of Modulus . . . . . . . . . . . . . . . . . . 151
9-9 Edge-Aligned PWM Value Loading . . . . . . . . . . . . . . . . . . 151
9-10 Edge-Aligned Modulus Loading . . . . . . . . . . . . . . . . . . . . . 151
9-11 Complementary Pairing . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
9-12 Typical AC Motor Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
9-13 Dead-Time Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
9-14 Effects of Dead-Time Insertion. . . . . . . . . . . . . . . . . . . . . . 156
9-15 Dead-Time at Duty Cycle Boundaries . . . . . . . . . . . . . . . . 156
9-16 Dead-Time and Small Pulse Widths. . . . . . . . . . . . . . . . . . 157
9-17 PWM Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
9-18 PWM Output Control Register (PWMOUT) . . . . . . . . . . . . 159
9-19 Dead-Time Insertion During OUTCTL = 1 . . . . . . . . . . . . . 160
9-20 Dead-Time Insertion During OUTCTL = 1 . . . . . . . . . . . . . 161
9-21 PWM Disabling Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . .162
9-22 PWM Disable Mapping Write-Once Register (DISMAP) . . 163
22 List of Figures Freescale Semiconductor

List of Figures
9-23 PWM Disabling Decode Scheme . . . . . . . . . . . . . . . . . . . .164

9-24 PWM Disabling in Automatic Mode . . . . . . . . . . . . . . . . . . 166
9-25 PWM Disabling in Manual Mode (Example 1) . . . . . . . . . . 167
9-26 PWM Disabling in Manual Mode (Example 2) . . . . . . . . . . 167
9-27 PWM Software Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
9-28 PWMEN and PWM Pins. . . . . . . . . . . . . . . . . . . . . . . . . . .169
9-29 PWM Counter Register High (PCNTH) . . . . . . . . . . . . . . . 172
9-30 PWM Counter Register Low (PCNTH) . . . . . . . . . . . . . . . . 172
9-31 PWM Counter Modulo Register High (PDMODH) . . . . . . . 173
9-32 PWM Counter Modulo Register Low (PDMODL) . . . . . . . . 173
9-33 PWMx Value Registers High (PVALxH) . . . . . . . . . . . . . . . 174
9-34 PWMx Value Registers Low (PVALxL) . . . . . . . . . . . . . . . 174
9-35 PWM Control Register 1 (PCTL1) . . . . . . . . . . . . . . . . . . . 175
9-36 PWM Control Register 2 (PCTL2) . . . . . . . . . . . . . . . . . . . 177
9-37 Dead-Time Write-Once Register (DEADTM) . . . . . . . . . . . 179
9-38 PWM Disable Mapping Write-Once Register (DISMAP) . . 179
9-39 Fault Control Register (FCR) . . . . . . . . . . . . . . . . . . . . . . .180
9-40 Fault Status Register (FSR) . . . . . . . . . . . . . . . . . . . . . . . . 181
9-41 Fault Acknowledge Register (FTACK) . . . . . . . . . . . . . . . . 182
9-42 PWM Output Control Register (PWMOUT) . . . . . . . . . . . . 184
9-43 PWM Clock Cycle and PWM Cycle Definitions . . . . . . . . . 186
9-44 PWM Load Cycle/Frequency Definition . . . . . . . . . . . . . . . 186
10-1 Monitor Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
10-2 Monitor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
10-3 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 191
10-4 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
10-5 Break Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
10-6 Monitor Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . 196
11-1 TIMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
11-2 TIMA I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .201
11-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . 208
11-4 TIMA Status and Control Register (TASC). . . . . . . . . . . . . 214
11-5 TIMA Counter Registers (TACNTH and TACNTL). . . . . . . 216
11-6 TIMA Counter Modulo Registers (TMODH and TMODL). . 217

List of Figures
11-7 TIMA Channel Status and Control Registers (TASC0–TASC1)

218
11-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
11-9 TIMA Channel Registers (TACH0H/L–TACH1H/L) . . . . . . 222
12-1 TIMB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
12-2 TIMB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .225
12-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . 232
12-4 TIMB Status and Control Register (TBSC). . . . . . . . . . . . . 238
12-5 TIMB Counter Registers (TBCNTH and TBCNTL). . . . . . . 240
12-6 TIMB Counter Modulo Registers (TMODH and TMODL). . 241
12-7 TIMB Channel Status and Control Registers (TBSC0–TBSC1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
12-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
12-9 TIMB Channel Registers (TBCH0H/L–TBCH1H/L) . . . . . . 246
13-1 SCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 250
13-2 SCI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . 251
13-3 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
13-4 SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
13-5 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .256
13-6 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . .258
13-7 SCI Control Register 1 (SCC1) . . . . . . . . . . . . . . . . . . . . . 264
13-10 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . 271
13-11 Flag Clearing Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . .274
13-12 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . 275
13-13 SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . 276
13-14 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . 276
14-1 I/O Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 280
14-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . 281
14-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . 282
14-4 Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
14-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . 284
14-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . 285
14-7 Port B I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

List of Figures
14-8 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . 287

14-9 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . 288
14-10 Port C I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
15-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
15-2 COP I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 292
15-3 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . .294
16-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 298
16-2 IRQ I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 298
16-3 IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
16-4 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . 303
17-1 LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 306
17-2 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 307
17-3 LVI Status and Control Register (LVISCR) . . . . . . . . . . . . 308
18-1 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
18-2 8-Bit Truncation Mode Error . . . . . . . . . . . . . . . . . . . . . . . . 316
18-3 ADC Status and Control Register (ADSCR). . . . . . . . . . . . 319
18-4 ADC Data Register High (ADRH) Left Justified Mode . . . . 322
18-5 ADC Data Register High (ADRH) Right Justified Mode . . . 322
18-6 ADC Data Register Low (ADRL) Left Justified Mode . . . . . 323
18-7 ADC Data Register Low (ADRL) Right Justified Mode. . . . 323
18-8 ADC Data Register Low (ADRL) 8-Bit Mode . . . . . . . . . . . 324
18-9 ADC Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . 324
20-1 Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 331
20-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
20-3 Break Status and Control Register (BRKSCR) . . . . . . . . . 333
20-4 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . 334
20-5 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . 335
20-6 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . 336
20-7 Example Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
20-8 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . 337

List of Figures

List of Tables
Table Title Page
2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6-2 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7-1 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7-2 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8-1 VCO Frequency Multiplier (N) Selection. . . . . . . . . . . . . . . . 131
9-1 PWM Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9-2 PWM Reload Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9-3 PWM Data Overflow and Underflow Conditions. . . . . . . . . . 152
9-4 OUTx Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
9-5 PWM Reload Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
9-6 PWM Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
9-7 OUTx Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
10-1 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
10-2 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
10-3 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . 193
10-4 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . .193
10-5 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . .194
10-6 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . 194
10-7 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . 195
10-8 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . 195
11-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
11-2 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . 220
12-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
12-2 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . 244
13-1 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
13-2 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
13-3 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
13-4 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . 266
Freescale Semiconductor List of Tables 27

List of Tables
13-5 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . 277

13-6 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
13-7 SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . 278
14-1 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
14-2 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
14-3 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
17-1 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
18-1 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
18-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
23-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
28 List of Tables Freescale Semiconductor

Section 1. General Description
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
1.5.1 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . .34
1.5.2 Oscillator Pins (OSC1 and OSC2). . . . . . . . . . . . . . . . . . .34
1.5.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . .34
1.5.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . .35
1.5.5 CGM Power Supply Pins (VDDA and VSSA) . . . . . . . . . . . .35
1.5.6 ADC Reference Voltage Input Pin (VREFH) . . . . . . . . . . . .35
1.5.7 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . .35
1.5.8 Port A Input/Output (I/O) Pins (PTA6/ATD6–PTA0/ATD0)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
1.5.9 Port B I/O Pins (PTB6/TCHB1–PTB0/RxD) . . . . . . . . . . . .36
1.5.10 Port C I/O Pins (PTC1/FAULT1–PTC0/FAULT4). . . . . . . .36
1.5.11 PWM Pins (PWM6–PWM1) . . . . . . . . . . . . . . . . . . . . . . . . .36
1.2 Introduction
The MC68HC908MR8 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCU). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
Freescale Semiconductor General Description 29

General Description
1.3 Features
Features of the MC68HC908MR8 include:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
• 8-MHz internal bus frequency
• 8 Kbytes of on-chip FLASH
• On-chip programming firmware for use with host personal
computer
• 256 bytes of on-chip random-access memory (RAM):
• 12-bit, 6-channel center-aligned or edge-aligned pulse-width
modulator (PWMMC)
• Serial communications interface module (SCI)
• Two 16-bit, 2-channel timer interface modules (TIMA and TIMB)
• Eight high current sink and source pins (PTA1/ATD1, PTA0/ATD0,
PTB6/TCH1B, PTB5/TCH0B, PTB4/TCH1A, PTB3/TCH0A,
PTB2/TCLKA, and PTB1/TxD)
• Clock generator module (CGM)
• Digitally filtered low-voltage inhibit (LVI), software selectable for
±5 percent or ±10 percent tolerance
• 10-bit, 4 to 7-channel analog-to-digital converter (ADC)
• System protection features:
– Optional computer operating properly (COP) reset
– Low-voltage detection with optional reset
– Illegal opcode detection with optional reset
– Illegal address detection with optional reset
– Fault detection with optional PWM disabling
30 General Description Freescale Semiconductor

General Description
MCU Block Diagram
• Available packages:
– 32-pin low-profile quad flat pack (LQFP)
– 28-pin dual in-line package (PDIP)
– 28-pin small outline package (SOIC)
• Low-power design, fully static with stop and wait modes
• Break (BRK) module allows single breakpoint setting during
in-circuit debugging
• Master reset pin and power-on reset (POR)
Features of the CPU08 include:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the M68HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16 ÷ 8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• C language support
1.4 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC908MR8.

General Description
32
Technical Data
INTERNAL BUS
M68HC08 CPU
CPU ARITHMETIC/LOGIC PTA6/ATD6

REGISTERS UNIT (ALU) LOW-VOLTAGE INHIBIT PTA5/ATD5
MODULE PTA4/ATD4
DDRA
PTA
PTA3/ATD3
PTA2/ATD2
COMPUTER OPERATING PROPERLY PTA1/ATD1
CONTROL AND STATUS REGISTERS — 112 BYTES MODULE
PTA0/ATD0
USER FLASH — 7680 BYTES BREAK

MODULE PTB6/TCH1B
PTB5/TCH0B
PTB4/TCH1A
USER RAM — 256 BYTES
DDRB
PTB
PTB3/TCH0A
TIMER A AND TIMER B INTERFACE
PTB2/TCLKA
MODULES
PTB1/TxD
MONITOR ROM — 313 BYTES PTB0/RxD
SERIAL COMMUNICATIONS INTERFACE
General Description
USER VECTOR SPACE — 46 BYTES MODULE

PWM6
PWM5
PWM4
PULSE-WIDTH
MODULATOR
OSC1
CLOCK GENERATOR PWM3
OSC2 PWM2
MODULE
CGMXFC PWM1
PTC1/FAULT4
POWER-ON RESET PTC0/FAULT1
SYSTEM INTEGRATION MODULE
RST
MODULE
IRQ
IRQ MODULE
VREFH ANALOG-TO-DIGITAL CONVERTER

MODULE
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
PULSE-WIDTH MODULATOR
MODULE
VDD
VDDA
VSSA POWER
VSS
Figure 1-1. MCU Block Diagram

General Description
Pin Assignments
1.5 Pin Assignments

Figure 1-2 shows 32-pin QFP and 28-pin DIP/SOIC pin assignments.
PTA6/ATD6 **
PTA5/ATD5 **
PTA4/ATD4 **
PTA3/ATD3
25 PTA2/ATD2
VREFH
32 VDDA
RST
VSSA 1 O
31
30
29
28
27
26
24 PTA1/ATD1
OSC2 2 23 PTA0/ATD0
OSC1
*
3 22 PTB6/TCH1B
CGMXFC 4 21 PTB5/TCH0B
32-PIN QFP
IRQ 5 20 VSS
PWM1 6 19 VDD
PWM2 7 18 PTB4/TCH1A
PWM3 8
*
17 PTB3/TCH0A
10
11
12
13
14
15
PTB2/TCLKA 16
PWM4 9
PTC0/FAULT1
** PTC1/FAULT4
PTB0/RxD
PTB1/TxD
PWM5
PWM6
VREFH 1O 28 PTA3/ATD3
RST 2 27 PTA2/ATD2
VDDA 3 26 PTA1/ATD1
VSSA 4 25 PTA0/ATD0
*
OSC2 5 24 PTB6/TCH1B
28-PIN
OSC1 6 DIP/SOIC 23 PTB5/TCH0B
CGMXFC 7 22 VSS
IRQ 8 21 VDD
PWM1 9 20 PTB4/TCH1A
PWM2 10 19 PTB3/TCH0A *
PWM3 11 18 PTB2/TCLKA
PWM4 12 17 PTB1/TxD
PWM5 13 16 PTB0/RxD
PWM6 14 15 PTC0/FAULT1
* High current pins

** These pins are not bonded on the 28-pin package.
Figure 1-2. QFP and DIP/SOIC Pin Assignments

General Description
1.5.1 Power Supply Pins (VDD and VSS)
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current

demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-3
shows. Place the C1 bypass capacitor as close to the MCU as possible.
Use a high-frequency-response ceramic capacitor for C1. C2 is an
optional bulk current bypass capacitor for use in applications that require
the port pins to source high current levels.
MCU
VDD VSS
C1
0.1 µF
C2
VDD
Note: Component values shown represent typical applications.
Figure 1-3. Power Supply Bypassing
1.5.2 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. See Section 8. Clock Generator Module (CGM).
1.5.3 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known startup state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. See Section 7. System
Integration Module (SIM).

General Description
Pin Assignments
1.5.4 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. See Section 16. External

Interrupt (IRQ).
1.5.5 CGM Power Supply Pins (VDDA and VSSA)
VDDA and VSSA are the power supply pins for the analog portion of the
clock generator module (CGM) and the analog-to-digital converter
(ADC). Decoupling of these pins should be per the digital supply. See
Section 8. Clock Generator Module (CGM) and Section 18.
Analog-to-Digital Converter (ADC).
1.5.6 ADC Reference Voltage Input Pin (VREFH)
VREFH is the power supply input for setting the reference voltage. See
Section 18. Analog-to-Digital Converter (ADC).
1.5.7 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See

Section 8. Clock Generator Module (CGM).
1.5.8 Port A Input/Output (I/O) Pins (PTA6/ATD6–PTA0/ATD0)
Port A is a 7-bit special function port, sharing all of its pins with the
analog-to-digital converter (ADC). On the 32-pin QFP package, all seven
bits (PTA6/ATD6–PTA0/ATD0) of the port are available. On the 28-pin
package, four bits (PTA3/ATD3–PTA0/ATD0) are available.
PTA3–PTA0 have high current source and sink capability. See

Section 14. Input/Output (I/O) Ports.

General Description
1.5.9 Port B I/O Pins (PTB6/TCHB1–PTB0/RxD)
Port B is a 7-bit special function port, sharing five of its pins with the timer
interface modules (TIMA and TIMB) and two of its pins with the serial
communications interface (SCI). See Section 11. Timer Interface A
(TIMA), Section 12. Timer Interface B (TIMB), Section 14.
Input/Output (I/O) Ports, and Section 13. Serial Communications
Interface (SCI).
1.5.10 Port C I/O Pins (PTC1/FAULT1–PTC0/FAULT4)
Port C is a 2-bit special function port, sharing its pins with pulse-width
modulator fault inputs. See Section 9. Pulse-Width Modulator for
Motor Control (PWMMC) and Section 14. Input/Output (I/O) Ports.
1.5.11 PWM Pins (PWM6–PWM1)
PWM6–PWM1 are dedicated pins used for the outputs of the pulse-
width modulator module (PWMMC). See Section 9. Pulse-Width
Modulator for Motor Control (PWMMC).

Section 2. Memory Map
2.1 Contents
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . .38
2.4 Reserved Memory Locations. . . . . . . . . . . . . . . . . . . . . . . . .38
2.5 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.6 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.2 Introduction
The central processor unit (CPU08) can address 64 Kbytes of memory
space.
The memory map, shown in Figure 2-1, includes these features:

• 8 Kbytes of FLASH
• 256 bytes of RAM
• 313 bytes of monitor ROM
• 46 bytes of user-defined vectors
Freescale Semiconductor Memory Map 37

Memory Map
2.3 Unimplemented Memory Locations

Some addresses are unimplemented. Accessing an unimplemented
address will cause an illegal address reset. In the memory map and in
the input/output (I/O) register summary, unimplemented addresses are
shaded.
Some I/O bits are read-only; the write function is unimplemented. Writing
to a read-only I/O bit has no effect on MCU operation. In register figures,
the write function of read-only bits is shaded. Similarly, some I/O bits are
write-only; the read function is unimplemented. Reading of write-only I/O
bits has no effect on microcontroller unit (MCU) operation. In register
figures, the read function of write-only bits is shaded.
2.4 Reserved Memory Locations

Some addresses are reserved. Writing to a reserved address can have
unpredictable effects on MCU operation. In the memory map and in the
I/O register summary, reserved addresses are marked with the word
reserved.
Some I/O bits are reserved. Writing to a reserved bit can have
unpredictable effects on MCU operation. In register figures, reserved
bits are marked with the letter R.
38 Memory Map Freescale Semiconductor

Memory Map
I/O Section
2.5 I/O Section

Addresses $0000–$005F, shown in Figure 2-2, contain most of the
control, status, and data registers. Additional I/O registers have these
addresses:
• $FE00, system integration module (SIM) break status register
(SBSR)
• $FE01, SIM reset status register (SRSR)
• $FE03, SIM break flag control register (SBFCR)
• $FE08, FLASH control register (FLCR)
• $FF57, FLASH test control register (FLTCR)
• $FE0C, break address register high (BRKH)
• $FE0D, break flag control register low (BRKL)
• $FE0E, break status and control register (BRKSCR)
• $FE0F, low-voltage inhibit (LVI) status and control register
(LVISCR)
• $FF7E, FLASH block protect register (FLBPR)
• $FFFF, computer operating properly (COP) control register
(COPCTL)

Memory Map
MC68HC908MR8
$0000 $0000
↓ I/O REGISTERS — 96 BYTES ↓
$005F $005F
$0060 $0060
↓
RAM — 256 BYTES ↓
$011F
$0120 $015F
$0160
↓ UNIMPLEMENTED — 56,992 BYTES ↓
$DFFF
$EDFF $E000
$EE00
FLASH MEMORY — 7,680 BYTES ↓
↓
$FDFF $FDFF
$FE00 SIM BREAK STATUS REGISTER (SBSR) $FE00
$FE01 SIM RESET STATUS REGISTER (SRSR) $FE01
$FE02 RESERVED $FE02
$FE03 SIM BREAK FLAG CONTROL REGISTER (SBFCR) $FE03
$FE07 FLASH CONTROL REGISTER (FLCR) $FE08
$FE09 UNIMPLEMENTED $FE09
$FE0A RESERVED $FE0A
$FE0B UNIMPLEMENTED $FE0B
$FE0C BREAK ADDRESS REGISTER HIGH (BRKH) $FE0C
$FE0D BREAK ADDRESS REGISTER LOW (BRKL) $FE0D
$FE0E BREAK STATUS AND CONTROL REGISTER (BRKSCR) $FE0E
$FE0F LVI STATUS AND CONTROL REGISTER (LVISCR) $FE0F
$FE10 $FE10
↓ MONITOR ROM — 313 BYTES ↓
$FF48 $FF48
$FF49 $FF49
↓ UNIMPLEMENTED — 53 BYTES ↓
$FF7D $FF7D
Figure 2-1. Memory Map

Memory Map
I/O Section
$FF7E FLASH BLOCK PROTECT REGISTER (FLBPR) $FF7E

$FF7F $FF7F
↓ UNIMPLEMENTED — 83 BYTES ↓
$FFD1 $FFD1
$FFD2 $FFD2
↓ VECTORS — 45 BYTES (46 including $FFFF) ↓
$FFFE $FFFE
Low byte of reset vector when read
$FFFF $FFFF
COP Control Register (COPCTL)
Figure 2-1. Memory Map
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0

Read
Port A Data Register U PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
$0000 (PTA) Write:
See page 281.
Reset Unaffected by reset
Read:
Port B Data Register U PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001 (PTB) Write:
See page 284.
Reset:
Unaffected by reset
Read:
Port C Data Register U U U U U U PTC1 PTC0
$0002 (PTC) Write:
See page 287.
Reset:
Unaffected by reset
$0003 Unimplemented
Read:
Data Direction Register U DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
A
$0004 Write:
(DDRA)
See page 282. Reset:
U 0 0 0 0 0 0 0
U = Unaffected X = Indetermi- = Reserved = Buff- = Unimplemented

R Bold
nate ered
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 10)

Memory Map

Read:
Data Direction Register U DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
B
$0005 Write:
(DDRB)
U 0 0 0 0 0 0 0
Read:
Data Direction Register DDRC1 DDRC0
C
$0006 Write:
(DDRC)
U U U U U U 0 0
$0007 Unimplemented
↓
$000D Unimplemented
Read: TOF 0 0
TIMA Status/Control TOIE TSTOP PS2 PS1 PS0
$000E Register (TASC) Write: 0 TRST R
See page 214.
Reset: 0 0 1 0 0 0 0 0
TIMA Counter Register Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
High
$000F Write: R R R R R R R R
(TACNTH)
See page 216. Reset: 0 0 0 0 0 0 0 0
TIMA Counter Register Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Low
$0010 Write: R R R R R R R R
(TACNTL)
See page 216. Reset: 0 0 0 0 0 0 0 0
TIMA Counter Modulo Read:
Register High Bit 15 14 13 12 11 10 9 Bit 8
$0011 Write:
(TAMODH)
See page 217. Reset: 1 1 1 1 1 1 1 1
Read:
TIMA Counter Modulo Bit 7 6 5 4 3 2 1 Bit 0
$0012 Register Low (TAMODL) Write:
See page 217.
Reset: 1 1 1 1 1 1 1 1
TIMA Channel 0 Sta- Read: CH0F CH0MA
tus/Control Register CH0IE MS0B MS0A ELS0B ELS0A TOV0
$0013 Write: 0 X
(TASC0)
See page 218. Reset: 0 0 0 0 0 0 0 0
R Bold
nate ered

Memory Map
I/O Section

Read:
TIMA Channel 0 Regis- Bit 15 14 13 12 11 10 9 Bit 8
$0014 ter High (TACH0H) Write:
See page 222.
Reset: Indeterminate after reset
Read:
$0015 ter Low (TACH0L) Write:
See page 218.
TIMA Channel 1 Sta- Read: CH1F 0 CH1MA
tus/Control CH1IE MS1A ELS1B ELS1A TOV1
$0016 Write: 0 R X
Register (TASC1)
See page 222. Reset: 0 0 0 0 0 0 0 0
Read:
$0017 ter High (TACH1H) Write:
See page 222.
Read:
$0018 ter Low (TACH1L) Write:
See page 222.
$0019 Unimplemented
↓
$001E Unimplemented
$001F Read: BOT- TOP-

Configuration Register EDGE INDEP LVIRST LVIPWR STOPE COPD
(CONFIG) Write: NEG NEG
See page 68.
Reset: 0 0 0 0 1 1 0 0
Read: PW- PW-
PWM Control Register 1 DISX DISY PWMF LDOK
$0020 (PCTL1) Write: MINT MEN
See page 175.
Reset: 0 0 0 0 0 0 0 0
Read: 0
PWM Control Register 2 LDFQ1 LDFQ0 SEL12 SEL34 SEL56 PRSC1 PRSC0
$0021 (PCTL2) Write:
See page 177.
Reset: 0 0 0 0 0 0 0 0
R Bold
nate ered

Memory Map

Read: FMODE FMODE
Fault Control Register FINT4 FINT1
$0022 (FCR) Write: 4 1
See page 180.
Reset: 0 0 0 0 0 0 0 0
FFLAG FFLAG
Read: FPIN4 0 0 0 0 FPIN1
Fault Status Register 4 1
$0023 (FSR)
Write:
See page 181.
Reset: U 0 U 0 U 0 U 0
Read: 0 0 0 0 0 0 0 0
Fault Acknowledge Reg-
FTACK FTACK
$0024 ister (FTACK) Write:
4 1
See page 182.
Reset: 0 0 0 0 0 0 0 0
Read: 0 OUT-
PWM Output Control OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
$0025 (PWMOUT) Write: CTL
See page 159.
Reset: 0 0 0 0 0 0 0 0
Read: 0 0 0 0 Bit 11 Bit 10 Bit 9 Bit 8
PWM Counter Register
$0026 High (PCNTH) Write:
See page 172.
Reset: 0 0 0 0 0 0 0 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0027 Low (PCNTL) Write:
See page 172.
Reset: 0 0 0 0 0 0 0 0
Read: 0 0 0 0
PWM Counter Modulo Bit 11 Bit 10 Bit 9 Bit 8
$0028 Register High (PMODH) Write:
See page 173.
Reset: 0 0 0 0 X X X X
Read:
PWM Counter Modulo Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0029 Register Low (PMODL) Write:
See page 173.
Reset: X X X X X X X X
Read:
PWM 1 Value Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$002A High (PVAL1H) Write:
See page 174.
Reset: 0 0 0 0 0 0 0 0
R Bold
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Memory Map
I/O Section

Read:
$002B Low (PVAL1L) Write:
See page 174.
Reset: 0 0 0 0 0 0 0 0
Read:
$002C High (PVAL2H) Write:
See page 174.
Reset: 0 0 0 0 0 0 0 0
Read:
$002D Low (PVAL2L) Write:
See page 174.
Reset: 0 0 0 0 0 0 0 0
Read:
$002E High (PVAL3H) Write:
See page 174.
Reset: 0 0 0 0 0 0 0 0
Read:
$002F Low (PVAL3L) Write:
See page 174.
Reset: 0 0 0 0 0 0 0 0
Read:
$0030 High (PVAL4H) Write:
See page 174.
Reset: 0 0 0 0 0 0 0 0
Read:
$0031 Low (PVAL4L) Write:
See page 174.
Reset: 0 0 0 0 0 0 0 0
Read:
$0032 High (PMVAL5H) Write:
See page 174.
Reset: 0 0 0 0 0 0 0 0
Read:
$0033 Low (PVAL5L) Write:
See page 174.
Reset: 0 0 0 0 0 0 0 0
Read:
$0034 High (PVAL6H) Write:
See page 174.
Reset: 0 0 0 0 0 0 0 0
R Bold
nate ered

Memory Map

Read:
$0035 Low (PMVAL6L) Write:
See page 174.
Reset: 0 0 0 0 0 0 0 0
Read:
Dead-Time Write-Once Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0036 Register (DEADTM) Write:
See page 179.
Reset: 1 1 1 1 1 1 1 1
PWM Disable Mapping Read:
Write-Once Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0037 Write:
(DISMAP)
See page 179. Reset: 1 1 1 1 1 1 1 1
Read: LOOP
SCI Control Register 1 ENSCI TXINV M WAKE ILTY PEN PTY
$0038 (SCC1) Write: S
See page 264.
Reset: 0 0 0 0 0 0 0 0
Read:
SCI Control Register 2 SCTIE TCIE SCRIE ILIE TE RE RWU SBK
$0039 (SCC2) Write:
See page 267.
Reset: 0 0 0 0 0 0 0 0
Read: R8 0 0
SCI Control Register 3 T8 ORIE NEIE FEIE PEIE
$003A (SCC3) Write: R R R
See page 270.
Reset: U U 0 0 0 0 0 0
Read: SCTE TC SCRF IDLE OR NF FE PE
SCI Status Register 1
$003B (SCS1) Write: R R R R R R R R
See page 271.
Reset: 1 1 0 0 0 0 0 0
Read: 0 0 0 0 0 0 BKF RPF
$003C (SCS2) Write: R R R R R R R R
See page 275.
Reset: 0 0 0 0 0 0 0 0
Read: R7 R6 R5 R4 R3 R2 R1 R0
SCI Data Register
$003D (SCDR) Write: T7 T6 T5 T4 T3 T2 T1 T0
See page 276.
Reset: Unaffected by reset
Read: 0 0 0
SCI Baud Rate Register SCP1 SCP0 SCR2 SCR1 SCR0
$003E (SCBR) Write: R R R
See page 276.
Reset: 0 0 0 0 0 0 0 0
R Bold
nate ered

Memory Map
I/O Section

IRQ Status/Control Reg- Read: 0 0 0 0 0
ister IRQF IMASK1 MODE1
$003F Write: R R R R ACK1
(ISCR)
See page 303. Reset: 0 0 0 0 0 0 0 0
Read:
ADC Status and Control COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
$0040 Register (ADSCR) Write:
See page 319.
Reset: 0 0 0 1 1 1 1 1
Read: 0 0 0 0 0 0 AD9 AD8
ADC Data Register High
$0041 (ADRH) Write: R R R R R R R R
See page 322.
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
ADC Data Register Low
$0042 (ADRL) Write: R R R R R R R R
See page 323.
Read: 0
ADC Clock Register ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 0
$0043 (ADCLK) Write: R
See page 324.
Reset: 0 0 0 0 0 1 0 0
$0044 Unimplemented
↓
$0050 Unimplemented
Read: TOF 0 0
TIMB Status/Control TOIE TSTOP PS2 PS1 PS0
$0051 Register (TBSC) Write: 0 TRST R
See page 238.
Reset: 0 0 1 0 0 0 0 0
TIMB Counter Register Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
High
(TBCNTH)
See page 240. Reset: 0 0 0 0 0 0 0 0
TIMB Counter Register Read; Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Low
(TBCNTL)
See page 240. Reset: 0 0 0 0 0 0 0 0
TIMB Counter Modulo Read:
Register High (TB- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$0054 Write:
MODH)
See page 241. Reset: 1 1 1 1 1 1 1 1
R Bold
nate ered

Memory Map

Read:
TIMB Counter Modulo Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0055 Register Low (TBMODL) Write:
See page 241.
Reset: 1 1 1 1 1 1 1 1
TIMB Channel 0 Sta- Read: CH0F CH0MA
tus/Control Register CH0IE MS0B MS0A ELS0B ELS0A TOV0
$0056 Write: 0 X
(TBSC0)
See page 242. Reset: 0 0 0 0 0 0 0 0
Read:
TIMB Channel 0 Regis- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$0057 ter High (TBCH0H) Write:
See page 246.
Read:
$0058 ter Low (TBCH0L) Write:
See page 246.
TIMB Channel 1 Sta- Read: CH1F 0 CH1MA
tus/Control Register CH1IE MS1A ELS1B ELS1A TOV1
$0059 Write: 0 R X
(TBSC1)
See page 242. Reset: 0 0 0 0 0 0 0 0
Read:
$005A ter High (TBCH1H) Write:
See page 246.
Read:
$005B ter Low (TBCH1L) Write:
See page 246.
Read: PLLF 1 1 1 1
PLL Control Register PLLIE PLLON BCS
$005C (PCTL) Write: R R R R R
See page 126.
Reset: 0 0 1 0 1 1 1 1
Read: LOCK 0 0 0 0
PLL Bandwidth Control AUTO ACQ XLD
$005D Register (PBWC) Write: R R R R R
See page 129.
Reset: 0 0 0 0 0 0 0 0
PLL Programming Reg- Read:
ister MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
$005E Write:
(PPG)
See page 131. Reset: 0 1 1 0 0 1 1 0
R Bold
nate ered

Memory Map
I/O Section

$005F Reserved R R R R R R R R
SIM Break Status Regis- Read: SBSW

ter R R R R R R R
$FE00 Write: Note(1)
(SBSR)
See page 336. Reset: 0
Note 1. Writing a logic 0 clears SBSW.
SIM Reset Status Regis- Read: POR PIN COP ILOP ILAD 0 LVI 0
ter
$FE01 Write: R R R R R R R R
(SRSR)
See page 108. Reset: 1 0 0 0 0 0 0 0
Read:
SIM Break Flag Control BCFE R R R R R R R
$FE03 Register (SBFCR) Write:
See page 109.
Reset: 0
Read: 0 0 0 0
FLASH Control Register HVEN MASS ERASE PGM
$FE08 (FLCR) Write:
See page 57.
Reset: 0 0 0 0 0 0 0 0
$FE0A Reserved R R R R R R R R
$FE0B Unimplemented
Read:
Break Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$FE0C High (BRKH) Write:
See page 334.
Reset: 0 0 0 0 0 0 0 0
Read:
Break Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$FE0D Low (BRKL) Write:
See page 334.
Reset: 0 0 0 0 0 0 0 0
Read: 0 0 0 0 0 0
Break Status and Con- BRKE BRKA
$FE0E trol Register (BRKSCR) Write:
See page 333.
Reset: 0 0 0 0 0 0 0 0
R Bold
nate ered

Memory Map

LVI-
Read: 0 TRPS- 0 0 0 0 0
LVI Status and Control OUT
$FE0F Register (LVISCR) EL
Write: R R R R R R R
See page 308.
Reset: 0 0 0 0 0 0 0 0
Read:
FLASH Block Protect BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
$FF7E Register (FLBPR) Write:
See page 63.
Read: Low byte of reset vector
COP Control Register
$FFFF (COPCTL) Write: Clear COP counter
See page 294.

R Bold
nate ered

Memory Map
I/O Section
Table 2-1 is a list of vector locations.
Table 2-1. Vector Addresses

Address Vector
$FFD2 SCI transmit vector (high)
Low
$FFD3 SCI transmit vector (low)
$FFD4 SCI receive vector (high)
$FFD5 SCI receive vector (low)
$FFD6 SCI error vector (high)
$FFD7 SCI error vector (low)
$FFD8 Reserved
$FFD9 Reserved
$FFDA Reserved
$FFDB Reserved
$FFDC A/D vector (high)
$FFDD A/D vector (low)
$FFDE TIMB overflow vector (high)
$FFDF TIMB overflow vector (low)
$FFE0 TIMB channel 1 vector (high)
Priority
$FFE1 TIMB channel 1 vector (low)

$FFE2 TIMB channel 0 vector (high)
$FFE3 TIMB channel 0 vector (low)
$FFE4 TIMA overflow vector (high)
$FFE5 TIMA overflow vector (low)
$FFE6 Reserved
$FFE7 Reserved
$FFE8 Reserved
$FFE9 Reserved
$FFEA TIMA channel 1 vector (high)
$FFEB TIMA channel 1 vector (low)
$FFEC TIMA channel 0 vector (high)
$FFED TIMA channel 0 vector (low)

Memory Map
Table 2-1. Vector Addresses (Continued)

Address Vector
$FFEE PWMMC vector (high)
$FFEF PWMMC vector (low)
$FFF0 FAULT 4 (high)
$FFF1 FAULT 4 (low)
$FFF2 Reserved
$FFF3 Reserved
$FFF4 Reserved
$FFF5 Reserved
Priority
$FFF6 FAULT 1 (high)

$FFF7 FAULT 1 (low)
$FFF8 PLL vector (high)
$FFF9 PLL vector (low)
$FFFA IRQ vector (high)
$FFFB IRQ vector (low)
$FFFC SWI vector (high)
$FFFD SWI vector (low)
$FFFE Reset vector (high)
High
$FFFF Reset vector (low)
2.6 Monitor ROM

313 bytes at addresses $FE10–$FF48 are reserved ROM addresses
that contain the instructions for the monitor functions.
See Section 10. Monitor ROM (MON).

Section 3. Random-Access Memory (RAM)
3.1 Contents
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.2 Introduction
This section describes the 256 bytes of random-access memory (RAM)
on the MC68HC908MR8.
3.3 Functional Description

Addresses $0060–$015F are RAM locations. The location of the stack
RAM is programmable. The 16-bit stack pointer allows the stack to be
anywhere in the 64-Kbyte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 160 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for input/output (I/O) control and user data or code. When the stack
pointer is moved from its reset location at $00FF, direct addressing
mode instructions can access efficiently all page zero RAM locations.
Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the central processor unit (CPU) registers.
NOTE: For M6805 compatibility, the H register is not stacked.
Freescale Semiconductor Random-Access Memory (RAM) 53

Random-Access Memory (RAM)
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
54 Random-Access Memory (RAM) Freescale Semiconductor

Section 4. FLASH Memory
4.1 Contents
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4.2.2 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.2.3 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . .58
4.2.4 FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . .59
4.2.5 FLASH Program/Read Operation . . . . . . . . . . . . . . . . . . .59
4.3 FLASH Programming Algorithm . . . . . . . . . . . . . . . . . . . . . .60
4.3.1 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.3.2 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . .63
4.3.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.2 Introduction
This section describes the operation of the MC68HC908MR8 embedded
FLASH memory. This memory can be read, programmed, and erased
from a single external supply. The program and erase operations are
enabled through the use of an internal charge pump.
Freescale Semiconductor FLASH Memory 55

FLASH Memory
4.2.1 Functional Description
The FLASH memory physically consists of an array of 7680 bytes with

an additional 46 bytes of user vectors and one byte of block protection.
An erased bit reads as a logic 1 and a programmed bit reads as a logic 0.
Program and erase operations are facilitated through control bits in a
memory mapped register. Details for these operations appear later in
this section.
Memory in the FLASH array is organized into two rows per page base.
For the 8-K word by 8-bit embedded FLASH memory, the page size is
64 bytes per page. The minimum erase page size is 64 bytes. Program
and erase operations are performed through control bits in the FLASH
control register (FLCR).
The address ranges for the user memory, control register, and vectors
are:
• $E000–$FDFF, user memory
• $FF7E, block protect register (FLBPR)
• $FE08, FLASH control register (FLCR)
• $FFD2–$FFFF, locations reserved for user-defined interrupt and
reset vectors
Programming tools are available from Freescale. Contact a local

Freescale representative for more information.
NOTE: A security feature1 prevents viewing of the FLASH contents.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or

copying the FLASH difficult for unauthorized users.
56 FLASH Memory Freescale Semiconductor

FLASH Memory
Introduction
4.2.2 FLASH Control Register
The FLASH control register (FLCR) controls the FLASH program, erase,
and read operations.
Ad- $FE08
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0
HVEN MASS ERASE PGM
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 4-1. FLASH Control Register (FLCR)
HVEN — High-Voltage Enable Bit

This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can be set only if
either PGM = 1 or ERASE = 1 and the proper sequence for
program/margin read or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation.
1 = Mass erase operation selected
0 = Mass erase operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
set at the same time.
1 = Erase operation selected
0 = Erase operation unselected

FLASH Memory
PGM — Program Control Bit

This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
set at the same time.
1 = Program operation selected
0 = Program operation unselected
4.2.3 FLASH Page Erase Operation
Use this step-by-step procedure to erase a page (64 bytes) of FLASH

memory to read as logic 1:
1. Set the ERASE bit and clear the MASS bit in the FLASH control
register.
2. Read the FLASH block protect register.
3. Write to any FLASH address with any data within the page
address range desired.
4. Wait for a time, tNVS (minimum of 10 µs).
5. Set the HVEN bit.
6. Wait for a time, tErase (minimum of 1 ms).
7. Clear the ERASE bit.
8. Wait for a time, tNVH (minimum of 5 µs).
9. Clear the HVEN bit.
10. After a time, tRCV (typically 1 µs), the memory can be accessed in
read mode again.
NOTE: While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Do not exceed tNVH
maximum. See 21.7 Memory Characteristics.

FLASH Memory
Introduction
4.2.4 FLASH Mass Erase Operation
Use this step-by-step procedure to erase the entire FLASH memory to

read as logic 1:
1. Set the ERASE bit and the MASS bit in the FLASH control register.
2. Read the block protect register.
6. Wait for a time, tErase (minimum of 4 ms).
7. Clear the ERASE bit.
8. Wait for a time, tNVHL (minimum of 100 µs).
read mode again.
NOTE: Programming and erasing of FLASH locations cannot be performed by

code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed tNVH maximum. See 21.7
Memory Characteristics.
4.2.5 FLASH Program/Read Operation
Programming of the FLASH memory is done on a row basis. A row

consists of 32 consecutive bytes starting from address $XX00, $XX20,
$XX40, and $XX80.
Use this step-by-step procedure to program a row of FLASH memory:
1. Set the PGM bit in the FLASH control register. This configures the
memory for program operation and enables the latching of
address and data programming.
2. Read the block protect register.

FLASH Memory

6. Wait for a time, tPGS (minimum of 5 µs).
7. Write data to the FLASH address to be programmed.
8. Wait for a time, tPROG (minimum of 30 µs).
9. Repeat step 7 and step 8 until all the bytes within the row are
programmed.
10. Clear the PGM bit.
11. Wait for a time, tNVH (minimum of 5 µs).
read mode again.
NOTE: The time between each FLASH address change, or the time between
the last FLASH address programmed to clear the PGM bit, must not
exceed the maximum programming time, tPROG.
Programming and erasing of FLASH locations cannot be performed by

code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed tPROG maximum. See 21.7
Memory Characteristics.
4.3 FLASH Programming Algorithm

Refer to Figure 4-2 for an algorithm for programming a row (32 bytes) of
FLASH memory.

FLASH Memory
FLASH Programming Algorithm
Note: PROGRAM FLASH

This page program algorithm assumes the rows to be
programmed are initially erased.
SET PGM BIT
READ FLASH BLOCK

PROTECT REGISTER
WRITE ANY DATA TO

SELECTED PAGE
WAIT FOR A TIME, tNVS
SET HVEN BIT
WAIT FOR A TIME, tPGS
WRITE DATA TO THE FLASH

ADDRESS TO BE PROGRAMMED
WAIT FOR A TIME, tPROG
NO COMPLETED
PROGRAMMING
THIS ROW?
YES
CLEAR PGM BIT
WAIT FOR A TIME, tPROG
CLEAR HVEN BIT
Note:
The time between each address change, or the time
between the last FLASH address programmed to clear WAIT FOR A TIME, TPROG
the PGM bit, must not exceed the maximum
programming time, tPROG.
PROGRAMMING OPERATION
COMPLETE
Figure 4-2. FLASH Programming Algorithm

FLASH Memory
4.3.1 FLASH Block Protection
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made for protecting
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by using a FLASH protection
register (FLBPR).
The FLBPR determines the range of the FLASH memory which is to be

protected. The range of the protected area starts from a location defined
by FLBPR and ends at the bottom of the FLASH memory ($FFFF). When
the memory is protected, the HVEN bit cannot be set in either erase or
program operations.
NOTE: In performing a program erase operation, the FLASH block protect

register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
When the block protect register is erased (all 1s), the entire memory is
accessible for program and erase. When bits within the register are
programmed (set to 0), they lock blocks of memory address ranges as
shown in 4.3.2 FLASH Block Protect Register. Once the block protect
register is programmed with value other than $FF, any erase or program
of the block protect register or the protected pages will be prohibited. The
block protect register itself can be erased or programmed only with an
external voltage VHI present on the IRQ pin. The presence of VHI on the
IRQ pin also allows entry into monitor mode out of reset. Therefore, the
ability to change the block protect register is voltage dependent and can
occur in either user or monitor modes.

FLASH Memory
4.3.2 FLASH Block Protect Register
The block protect register (FLBPR) is implemented as a byte within the

FLASH memory, and therefore can only be written during a
programming sequence of the FLASH memory. The value in this register
determines the starting location of the protected range within the FLASH
memory.
Ad- $FF7E
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Write:
Reset: U U U U U U U U
U= Unaffected by reset. Initial value from factory is 1.

Write to this register by a programming sequence to the FLASH memory.
Figure 4-3. FLASH Block Protect Register (FLBPR)
BPR[7:0] — Block Protect Register Bits

These eight bits represent bits [13:6] of a 16-bit memory address.
Bits[15:14] are logical 1s and bits [5:0] are logic 0s.
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory at $FFFF. With
this mechanism, the protect start address can be $XX00, $XX40,
$XX80, and $XXC0 (64-byte page boundaries) within the FLASH
memory.

FLASH Memory
16-BIT MEMORY ADDRESS

START ADDRESS OF
FLASH 1 1 FLBPR VALUE 0 0 0 0 0 0
BLOCK PROTECT
Figure 4-4. FLASH Block Protect Address
$80 = The entire FLASH memory is protected.

$81 = Protected range: $E040–$FFFF
$82 = Protected range: $E080–$FFFF
↓ ↓ ↓
$FE = Protected range: $FF80–$FFFF
$FF = Entire FLASH memory is not protected.
If all bits are erased, then all of the memory is available for erase and
program. The presence of a voltage VHI on the IRQ pin will bypass the
block protection so that all of the memory, including the block protect
register, is open for program and erase operations.
4.3.3 Low-Power Modes
The WAIT and STOP instructions will place the MCU in a low power-
consumption standby mode.
4.3.3.1 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly, but there will not
be any memory activity since the CPU is inactive.
The WAIT instruction should never be executed while performing a

program or erase operation on the FLASH. When the MCU is put into
wait mode, the charge pump for the FLASH is disabled so that either a
program or erase operation will not continue. If the memory is in either
program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1,
HVEN = 1), then it will remain in that mode during wait.
NOTE: Exiting from wait must now be done with a reset rather than an interrupt
because if exiting wait with an interrupt, the memory will not be in read
mode and the interrupt vector cannot be read from the memory.

FLASH Memory
4.3.3.2 Stop Mode
If the FLASH is in read mode, when the MCU is put into stop mode, the
FLASH will be put into low-power standby mode.
The STOP instruction should never be executed while performing a

program or erase operation on the FLASH. Otherwise the operation will
be discontinued and the FLASH will be in standby mode.
NOTE: Standby mode is the power-saving mode of the FLASH module, in which
all internal control signals to the FLASH are inactive and the current
consumption of the FLASH is minimum.

FLASH Memory

Section 5. Configuration Register (CONFIG)
5.1 Contents
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.3 CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
5.4 CONFIG Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
5.2 Introduction
This section describes the configuration register (CONFIG).
The CONFIG registers contain bits that configure these options:
• Resets caused by the low-voltage inhibit (LVI) module
• Power to the LVI module
• Computer operating properly (COP) module
• Top-side pulse-width modulator (PWM) polarity
• Bottom-side PWM polarity
• Edge-aligned versus center-aligned PWMs
• Six independent PWMs versus three complementary PWM pairs
• STOP instruction enable
Freescale Semiconductor Configuration Register (CONFIG) 67

Configuration Register (CONFIG)
5.3 CONFIG
The configuration register (CONFIG) is a write-once register. Once the
register is written, further writes will have no effect until a reset occurs.
5.4 CONFIG Bits

NOTE: If the LVI module and the LVI reset signal are enabled, a reset occurs
when VDD falls to a voltage, LVITRIPF, and remains at or below that level
for at least nine consecutive central processor unit (CPU) cycles. Once
an LVI reset occurs, the microcontroller unit (MCU) remains in reset until
VDD rises to a voltage, LVITRIPR.
Address: $001F
Bit 7 6 5 4 3 2 1 Bit 0
Read: BOT- TOP- LVIP-
EDGE INDEP LVIRST STOPE COPD
Write: NEG NEG WR
Reset
states:
CONFIG 0 0 0 0 1 1 0 0
Figure 5-1. CONFIG Register
EDGE — Edge-Align Enable Bit

EDGE determines if the motor control PWM will operate in
edge-aligned mode or center-aligned mode. See Section 9.
Pulse-Width Modulator for Motor Control (PWMMC).
1 = Edge-aligned mode enabled
0 = Center-aligned mode enabled
BOTNEG — Bottom-Side PWM Polarity Bit
BOTNEG determines if the bottom-side PWMs will have positive or
negative polarity. See Section 9. Pulse-Width Modulator for Motor
Control (PWMMC).
1 = Negative polarity
0 = Positive polarity
68 Configuration Register (CONFIG) Freescale Semiconductor

CONFIG Bits
TOPNEG — Top-Side PWM Polarity Bit

TOPNEG determines if the top-side PWMs will have positive or
negative polarity. See Section 9. Pulse-Width Modulator for Motor
Control (PWMMC).
1 = Negative polarity
0 = Positive polarity
INDEP — Independent Mode Enable Bit
INDEP determines if the motor control PWMs will be six independent
PWMs or three complementary PWM pairs. See Section 9.
Pulse-Width Modulator for Motor Control (PWMMC).
1 = Six independent PWMs
0 = Three complementary PWM pairs
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. See Section 17. Low-Voltage
Inhibit (LVI).
1 = LVI module power enabled
0 = LVI module power disabled
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. See
Section 17. Low-Voltage Inhibit (LVI).
1 = LVI module resets enabled
0 = LVI module resets disabled
STOPE — STOP Enable Bit
STOPE enables the STOP instruction. See Section 6. Central
Processor Unit (CPU).
1 = STOP instruction is enabled.
0 = STOP instruction is disabled and executes as an illegal
instruction.
COPD — COP Disable Bit
COPD disables the COP module. See Section 15. Computer
Operating Properly (COP).
1 = COP module disabled
0 = COP module enabled
Freescale Semiconductor Configuration Register (CONFIG) 69

70 Configuration Register (CONFIG) Freescale Semiconductor

Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.4 CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.2 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.5 Arithmetic/Logic Unit (ALU). . . . . . . . . . . . . . . . . . . . . . . . . .78
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
6.2 Introduction
This section describes the central processor unit (CPU08, version A).
The M68HC08 CPU is an enhanced and fully object-code-compatible
version of the M68HC05 CPU. The CPU08 Reference Manual,
Freescale document number CPU08RM/AD, contains a description of
the CPU instruction set, addressing modes, and architecture.
Freescale Semiconductor Central Processor Unit (CPU) 71

Central Processor Unit (CPU)
6.3 Features
Features of the CPU include:
• Fully upward, object-code compatibility with M68HC05 family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with X-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• Sixteen addressing modes
• Memory-to-memory data moves without using the accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64 Kbytes
• Low-power stop and wait modes
6.4 CPU Registers

Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
7 0
ACCUMULATOR (A)
15 0
H X INDEX REGISTER (H:X)
15 0
STACK POINTER (SP)
15 0
PROGRAM COUNTER (PC)
7 0
V 1 1 H I N Z C CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
72 Central Processor Unit (CPU) Freescale Semiconductor

CPU Registers
6.4.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the

accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Re-
Unaffected by reset
set:
Figure 6-2. Accumulator (A)
6.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte

memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
Bit Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read:
Write:
Re-
0 0 0 0 0 0 0 0 X X X X X X X X
set:
X = Indeterminate
Figure 6-3. Index Register (H:X)
The index register can serve also as a temporary data storage location.

6.4.3 Stack Pointer
The stack pointer (SP) is a 16-bit register that contains the address of
the next location on the stack. During a reset, the stack pointer is preset
to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read:
Write:
Re-
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
set:
Figure 6-4. Stack Pointer (SP)
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct
address (page zero) space. For correct operation, the stack pointer must
point only to RAM locations.

CPU Registers
6.4.4 Program Counter
The program counter (PC) is a 16-bit register that contains the address
of the next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next

sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read:
Write:
Re-
Loaded with vector from $FFFE and $FFFF
set:
Figure 6-5. Program Counter (PC)

6.4.5 Condition Code Register
The 8-bit condition code register (CCR) contains the interrupt mask and
five flags that indicate the results of the instruction just executed. Bit 6
and bit 5 are set permanently to logic 1. The functions of the condition
code register are described here.
Bit 7 6 5 4 3 2 1 Bit 0
Read
: V 1 1 H I N Z C
Write:
Re-
X 1 1 X 1 X X X
set:
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add without carry (ADD) or add
with carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA
instruction uses the states of the H and C flags to determine the
appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.

CPU Registers
1 = Interrupts disabled
0 = Interrupts enabled
NOTE: To maintain M6805 compatibility, the upper byte of the index register (H)
is not stacked automatically. If the interrupt service routine modifies H,
then the user must stack and unstack H using the PSHH and PULH
instructions.
After the I bit is cleared, the highest-priority interrupt request is

serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from

the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting
bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7

6.5 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual, Freescale document number

CPU08RM/AD, for a description of the instructions and addressing
modes and more detail about CPU architecture.
6.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.
6.6.1 Wait Mode
The WAIT instruction:

• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
6.6.2 Stop Mode
The STOP instruction:

• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.

Instruction Set Summary
6.7 Instruction Set Summary

Table 6-1 provides a summary of the M68HC08 instruction set.
Table 6-1. Instruction Set Summary (Sheet 1 of 8)
Effect on CCR
Operand
Address
Opcode
Source
Cycles
Operation Description
Mode
Form V H I N Z C
ADC #opr IMM A9 ii 2
ADC opr DIR B9 dd 3
ADC opr EXT C9 hh ll 4
ADC opr,X ↕ ↕ – ↕ ↕ ↕ IX2 D9 ee ff 4
Add with Carry A ← (A) + (M) + (C)
ADC opr,X IX1 E9 ff 3
ADC ,X IX F9 2
ADC opr,SP SP1 9EE9 ff 4
ADC opr,SP SP2 9ED9 ee ff 5
ADD #opr IMM AB ii 2
ADD opr DIR BB dd 3
ADD opr EXT CB hh ll 4
ADD opr,X
↕ ↕ – ↕ ↕ ↕ IX2 DB ee ff 4
ADD opr,X Add without Carry A ← (A) + (M) IX1 EB ff 3
ADD ,X IX FB 2
ADD opr,SP SP1 9EEB ff 4
ADD opr,SP SP2 9EDB ee ff 5
AIS #opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) – – – – – – IMM A7 ii 2
AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) – – – – – – IMM AF ii 2
AND #opr IMM A4 ii 2
AND opr DIR B4 dd 3
AND opr EXT C4 hh ll 4
AND opr,X 0 – – ↕ ↕ – IX2 D4 ee ff 4
Logical AND A ← (A) & (M)
AND opr,X IX1 E4 ff 3
AND ,X IX F4 2
AND opr,SP SP1 9EE4 ff 4
AND opr,SP SP2 9ED4 ee ff 5
ASL opr DIR 38 dd 4
ASLA INH 48 1
ASLX Arithmetic Shift Left ↕ – – ↕ ↕ ↕ INH
C 0
58 1
ASL opr,X (Same as LSL) IX1 68 ff 4
ASL ,X b7 b0 IX 78 3
ASL opr,SP SP1 9E68 ff 5
ASR opr DIR 37 dd 4
ASRA INH 47 1
ASRX ↕ – – ↕ ↕ ↕ INH 57 1
Arithmetic Shift Right C
ASR opr,X b7
IX1 67 ff 4
b0
ASR opr,X IX 77 3
ASR opr,SP SP1 9E67 ff 5
BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 rr 3

Effect on CCR
Operand
Address
Opcode
Source
Cycles
Mode
Form V H I N Z C
DIR (b0) 11 dd 4
DIR (b1) 13 dd 4
DIR (b2) 15 dd 4
– – – – – – DIR (b3) 17 dd 4
BCLR n, opr Clear Bit n in M Mn ← 0 DIR (b4) 19 dd 4
DIR (b5) 1B dd 4
DIR (b6) 1D dd 4
DIR (b7) 1F dd 4
BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 – – – – – – REL 27 rr 3
Branch if Greater Than or Equal To
BGE opr PC ← (PC) + 2 + rel ? (N Ý V) = 0 – – – – – – REL 90 rr 3
(Signed Operands)
Branch if Greater Than
BGT opr PC ← (PC) + 2 + rel ? (Z) | (N Ý V) = 0 – – – – – – REL 92 rr 3
(Signed Operands)
BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 – – – – – – REL 28 rr 3
BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 – – – – – – REL 29 rr 3
BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 – – – – – – REL 22 rr 3
Branch if Higher or Same
BHS rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 rr 3
(Same as BCC)
BIH rel Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 – – – – – – REL 2F rr 3
BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 – – – – – – REL 2E rr 3
BIT #opr IMM A5 ii 2
BIT opr DIR B5 dd 3
BIT opr EXT C5 hh ll 4
BIT opr,X 0 – – ↕ ↕ – IX2 D5 ee ff 4
Bit Test (A) & (M)
BIT opr,X IX1 E5 ff 3
BIT ,X IX F5 2
BIT opr,SP SP1 9EE5 ff 4
BIT opr,SP SP2 9ED5 ee ff 5
Branch if Less Than or Equal To
BLE opr PC ← (PC) + 2 + rel ? (Z) | (N Ý V) = 1 – – – – – – REL 93 rr 3
(Signed Operands)
BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3
BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 – – – – – – REL 23 rr 3
BLT opr Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N Ý V) =1 – – – – – – REL 91 rr 3
BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 – – – – – – REL 2C rr 3
BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 – – – – – – REL 2B rr 3
BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 – – – – – – REL 2D rr 3

Effect on CCR
Operand
Address
Opcode
Source
Cycles
Mode
Form V H I N Z C
BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 – – – – – – REL 26 rr 3
BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 – – – – – – REL 2A rr 3
BRA rel Branch Always PC ¨ (PC) + 2 + rel – – – – – – REL 20 rr 3
DIR (b0) 01 dd rr 5
DIR (b1) 03 dd rr 5
DIR (b2) 05 dd rr 5
– – – – – ↕ DIR (b3) 07 dd rr 5
BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 DIR (b4) 09 dd rr 5
DIR (b5) 0B dd rr 5
DIR (b6) 0D dd rr 5
DIR (b7) 0F dd rr 5
BRN rel Branch Never PC ← (PC) + 2 – – – – – – REL 21 rr 3
DIR (b0) 00 dd rr 5
DIR (b1) 02 dd rr 5
DIR (b2) 04 dd rr 5
– – – – – ↕ DIR (b3) 06 dd rr 5
BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + rel ? (Mn) = 1 DIR (b4) 08 dd rr 5
DIR (b5) 0A dd rr 5
DIR (b6) 0C dd rr 5
DIR (b7) 0E dd rr 5
DIR (b0) 10 dd 4
DIR (b1) 12 dd 4
DIR (b2) 14 dd 4
– – – – – – DIR (b3) 16 dd 4
BSET n,opr Set Bit n in M Mn ← 1 DIR (b4) 18 dd 4
DIR (b5) 1A dd 4
DIR (b6) 1C dd 4
DIR (b7) 1E dd 4
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
BSR rel Branch to Subroutine – – – – – – REL AD rr 4
SP ← (SP) – 1
PC ← (PC) + rel
CBEQ opr,rel PC ← (PC) + 3 + rel ? (A) – (M) = $00 DIR 31 dd rr 5
CBEQA #opr,rel PC ← (PC) + 3 + rel ? (A) – (M) = $00 IMM 41 ii rr 4
CBEQX #opr,rel PC ← (PC) + 3 + rel ? (X) – (M) = $00 – – – – – – IMM 51 ii rr 4
Compare and Branch if Equal
CBEQ opr,X+,rel PC ← (PC) + 3 + rel ? (A) – (M) = $00 IX1+ 61 ff rr 5
CBEQ X+,rel PC ← (PC) + 2 + rel ? (A) – (M) = $00 IX+ 71 rr 4
CBEQ opr,SP,rel PC ← (PC) + 4 + rel ? (A) – (M) = $00 SP1 9E61 ff rr 6
CLC Clear Carry Bit C←0 – – – – – 0 INH 98 1
CLI Clear Interrupt Mask I←0 – – 0 – – – INH 9A 2
CLR opr M ← $00 DIR 3F dd 3
CLRA A ← $00 INH 4F 1
CLRX X ← $00 INH 5F 1
CLRH Clear H ← $00 0 – – 0 1 – INH 8C 1
CLR opr,X M ← $00 IX1 6F ff 3
CLR ,X M ← $00 IX 7F 2
CLR opr,SP M ← $00 SP1 9E6F ff 4

Effect on CCR
Operand
Address
Opcode
Source
Cycles
Mode
Form V H I N Z C
CMP #opr IMM A1 ii 2
CMP opr DIR B1 dd 3
CMP opr EXT C1 hh ll 4
CMP opr,X ↕ – – ↕ ↕ ↕ IX2 D1 ee ff 4
Compare A with M (A) – (M)
CMP opr,X IX1 E1 ff 3
CMP ,X IX F1 2
CMP opr,SP SP1 9EE1 ff 4
CMP opr,SP SP2 9ED1 ee ff 5
COM opr M ← (M) = $FF – (M) DIR 33 dd 4
COMA A ← (A) = $FF – (M) INH 43 1
COMX X ← (X) = $FF – (M) 0 – – ↕ ↕ 1 INH 53 1
Complement (One’s Complement) M ← (M) = $FF – (M)
COM opr,X IX1 63 ff 4
COM ,X M ← (M) = $FF – (M) IX 73 3
COM opr,SP M ← (M) = $FF – (M) SP1 9E63 ff 5
CPHX #opr ↕ – – ↕ ↕ ↕ IMM 65 ii ii+1 3
Compare H:X with M (H:X) – (M:M + 1)
CPHX opr DIR 75 dd 4
CPX #opr IMM A3 ii 2
CPX opr DIR B3 dd 3
CPX opr EXT C3 hh ll 4
CPX ,X ↕ – – ↕ ↕ ↕ IX2 D3 ee ff 4
Compare X with M (X) – (M)
CPX opr,X IX1 E3 ff 3
CPX opr,X IX F3 2
CPX opr,SP SP1 9EE3 ff 4
CPX opr,SP SP2 9ED3 ee ff 5
DAA Decimal Adjust A (A)10 U – – ↕ ↕ ↕ INH 72 2
A ← (A) – 1 or M ← (M) – 1 or X ←(X) – 1 5
DBNZ opr,rel PC ← (PC) + 3 + rel ? (result) ¼ 0 DIR 3B dd rr 3
DBNZA rel PC ← (PC) + 2 + rel ? (result) ¼ 0 INH 4B rr 3
DBNZX rel Decrement and Branch if Not Zero PC ← (PC) + 2 + rel ? (result) ¼ 0 – – – – – – INH 5B rr 5
DBNZ opr,X,rel PC ← (PC) + 3 + rel ? (result) ¼ 0 IX1 6B ff rr 4
DBNZ X,rel PC ← (PC) + 2 + rel ? (result) ¼ 0 IX 7B rr 6
DBNZ opr,SP,rel PC ← (PC) + 4 + rel ? (result) ¼ 0 SP1 9E6B ff rr
DEC opr M ← M) – 1 DIR 3A dd 4
DECA A ← A) – 1 INH 4A 1
DECX X ← (X) – 1 ↕ – – ↕ ↕ – INH 5A 1
Decrement
DEC opr,X M ← (M) – 1 IX1 6A ff 4
DEC ,X M ← (M) – 1 IX 7A 3
DEC opr,SP M ← (M) – 1 SP1 9E6A ff 5
A ← (H:A)/(X)
DIV Divide – – – – ↕ ↕ INH 52 7
H ← Remainder
EOR #opr IMM A8 ii 2
EOR opr DIR B8 dd 3
EOR opr EXT C8 hh ll 4
EOR opr,X 0 – – ↕ ↕ – IX2 D8 ee ff 4
Exclusive OR M with A A ← (A Ý M)
EOR opr,X IX1 E8 ff 3
EOR ,X IX F8 2
EOR opr,SP SP1 9EE8 ff 4
EOR opr,SP SP2 9ED8 ee ff 5

Effect on CCR
Operand
Address
Opcode
Source
Cycles
Mode
Form V H I N Z C
INC opr M ← M) + 1 DIR 3C dd 4
INCA A ← (A) + 1 INH 4C 1
INCX X ← X) + 1 ↕ – – ↕ ↕ – INH 5C 1
Increment
INC opr,X M ← (M) + 1 IX1 6C ff 4
INC ,X M ← (M) + 1 IX 7C 3
INC opr,SP M ← (M) + 1 SP1 9E6C ff 5
JMP opr DIR BC dd 2
JMP opr EXT CC hh ll 3
JMP opr,X Jump PC ← Jump Address – – – – – – IX2 DC ee ff 4
JMP opr,X IX1 EC ff 3
JMP ,X IX FC 2
JSR opr DIR BD dd 4
PC ← (PC) + n (n = 1, 2, or 3)
JSR opr EXT CD hh ll 5
Push (PCL); SP ← (SP) – 1
JSR opr,X Jump to Subroutine – – – – – – IX2 DD ee ff 6
Push (PCH); SP ← (SP) – 1
JSR opr,X IX1 ED ff 5
PC ← Unconditional Address
JSR ,X IX FD 4
LDA #opr IMM A6 ii 2
LDA opr DIR B6 dd 3
LDA opr EXT C6 hh ll 4
LDA opr,X 0 – – ↕ ↕ – IX2 D6 ee ff 4
Load A from M A ← (M)
LDA opr,X IX1 E6 ff 3
LDA ,X IX F6 2
LDA opr,SP SP1 9EE6 ff 4
LDA opr,SP SP2 9ED6 ee ff 5
LDHX #opr 0 – – ↕ ↕ – IMM 45 ii jj 3
Load H:X from M H:X ← (M:M + 1)
LDHX opr DIR 55 dd 4
LDX #opr IMM AE ii 2
LDX opr DIR BE dd 3
LDX opr EXT CE hh ll 4
LDX opr,X 0 – – ↕ ↕ – IX2 DE ee ff 4
Load X from M X ← (M)
LDX opr,X IX1 EE ff 3
LDX ,X IX FE 2
LDX opr,SP SP1 9EEE ff 4
LDX opr,SP SP2 9EDE ee ff 5
LSL opr DIR 38 dd 4
LSLA INH 48 1
LSLX Logical Shift Left ↕ – – ↕ ↕ ↕ INH
C 0 58 1
LSL opr,X (Same as ASL) b7
IX1 68 ff 4
b0
LSL ,X IX 78 3
LSL opr,SP SP1 9E68 ff 5
LSR opr DIR 34 dd 4
LSRA INH 44 1
LSRX ↕ – – 0 ↕ ↕ INH 54 1
Logical Shift Right 0 C
LSR opr,X b7
IX1 64 ff 4
b0
LSR ,X IX 74 3
LSR opr,SP SP1 9E64 ff 5
MOV opr,opr (M)Destination ← (M)Source DD 4E dd dd 5
MOV opr,X+ 0 – – ↕ ↕ – DIX+ 5E dd 4
Move
MOV #opr,opr IMD 6E ii dd 4
MOV X+,opr H:X ← (H:X) + 1 (IX+D, DIX+) IX+D 7E dd 4
MUL Unsigned multiply X:A ¨ (X) ¥ (A) – 0 – – – 0 INH 42 5

Effect on CCR
Operand
Address
Opcode
Source
Cycles
Mode
Form V H I N Z C
NEG opr DIR 30 dd 4
M ← –(M) = $00 – (M)
NEGA INH 40 1
A ← –(A) = $00 – (A)
NEGX ↕ – – ↕ ↕ ↕ INH 50 1
Negate (Two’s Complement) X ← –(X) = $00 – (X)
NEG opr,X IX1 60 ff 4
M ← –(M) = $00 – (M)
NEG ,X IX 70 3
M ← –(M) = $00 – (M)
NEG opr,SP SP1 9E60 ff 5
NOP No Operation None – – – – – – INH 9D 1
NSA Nibble Swap A A ← (A[3:0]:A[7:4]) – – – – – – INH 62 3
ORA #opr IMM AA ii 2
ORA opr DIR BA dd 3
ORA opr EXT CA hh ll 4
ORA opr,X Inclusive OR A and M A ← (A) | (M) 0 – – ↕ ↕ – IX2 DA ee ff 4
ORA opr,X IX1 EA ff 3
ORA ,X IX FA 2
ORA opr,SP SP1 9EEA ff 4
ORA opr,SP SP2 9EDA ee ff 5
PSHA Push A onto Stack Push (A); SP ← (SP) – 1 – – – – – – INH 87 2
PSHH Push H onto Stack Push (H); SP ← (SP) – 1 – – – – – – INH 8B 2
PSHX Push X onto Stack Push (X); SP ← (SP) – 1 – – – – – – INH 89 2
PULA Pull A from Stack SP ← (SP + 1); Pull (A) – – – – – – INH 86 2
PULH Pull H from Stack SP ← (SP + 1); Pull (H) – – – – – – INH 8A 2
PULX Pull X from Stack SP ← (SP + 1); Pull (X) – – – – – – INH 88 2
ROL opr DIR 39 dd 4
ROLA INH 49 1
ROLX ↕ – – ↕ ↕ ↕ INH 59 1
Rotate Left through Carry C
ROL opr,X b7
IX1 69 ff 4
b0
ROL ,X IX 79 3
ROL opr,SP SP1 9E69 ff 5
ROR opr DIR 36 dd 4
RORA INH 46 1
RORX ↕ – – ↕ ↕ ↕ INH 56 1
Rotate Right through Carry C
ROR opr,X b7
IX1 66 ff 4
b0
ROR ,X IX 76 3
ROR opr,SP SP1 9E66 ff 5
RSP Reset Stack Pointer SP ← $FF – – – – – – INH 9C 1
SP ← SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
RTI Return from Interrupt SP ← (SP) + 1; Pull (X) ↕ ↕ ↕ ↕ ↕ ↕ INH 80 7
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SP ← SP + 1; Pull (PCH)
RTS Return from Subroutine – – – – – – INH 81 4
SP ← SP + 1; Pull (PCL)

Effect on CCR
Operand
Address
Opcode
Source
Cycles
Mode
Form V H I N Z C
SBC #opr IMM A2 ii 2
SBC opr DIR B2 dd 3
SBC opr EXT C2 hh ll 4
SBC opr,X ↕ – – ↕ ↕ ↕ IX2 D2 ee ff 4
Subtract with Carry A ← (A) – (M) – (C)
SBC opr,X IX1 E2 ff 3
SBC ,X IX F2 2
SBC opr,SP SP1 9EE2 ff 4
SBC opr,SP SP2 9ED2 ee ff 5
SEC Set Carry Bit C←1 – – – – – 1 INH 99 1
SEI Set Interrupt Mask I←1 – – 1 – – – INH 9B 2
STA opr DIR B7 dd 3
STA opr EXT C7 hh ll 4
STA opr,X IX2 D7 ee ff 4
STA opr,X Store A in M M ← (A) 0 – – ↕ ↕ – IX1 E7 ff 3
STA ,X IX F7 2
STA opr,SP SP1 9EE7 ff 4
STA opr,SP SP2 9ED7 ee ff 5
STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – ↕ ↕ – DIR 35 dd 4
STOP Enable IRQ Pin; Stop Oscillator I ← 0; Stop Oscillator – – 0 – – – INH 8E 1
STX opr DIR BF dd 3
STX opr EXT CF hh ll 4
STX opr,X IX2 DF ee ff 4
STX opr,X Store X in M M ← (X) 0 – – ↕ ↕ – IX1 EF ff 3
STX ,X IX FF 2
STX opr,SP SP1 9EEF ff 4
STX opr,SP SP2 9EDF ee ff 5
SUB #opr IMM A0 ii 2
SUB opr DIR B0 dd 3
SUB opr EXT C0 hh ll 4
SUB opr,X ↕ – – ↕ ↕ ↕ IX2 D0 ee ff 4
Subtract A ← (A) – (M)
SUB opr,X IX1 E0 ff 3
SUB ,X IX F0 2
SUB opr,SP SP1 9EE0 ff 4
SUB opr,SP SP2 9ED0 ee ff 5
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SWI Software Interrupt – – 1 – – – INH 83 9
SP ← (SP) – 1; Push (CCR)
SP ¨ (SP) – 1; I ¨ 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP Transfer A to CCR CCR ← (A) ↕ ↕ ↕ ↕ ↕ ↕ INH 84 2
TAX Transfer A to X X ← (A) – – – – – – INH 97 1
TPA Transfer CCR to A A ← (CCR) – – – – – – INH 85 1

Effect on CCR
Operand
Address
Opcode
Source
Cycles
Mode
Form V H I N Z C
TST opr DIR 3D dd 3
TSTA INH 4D 1
TSTX 0 – – ↕ ↕ – INH 5D 1
Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00
TST opr,X IX1 6D ff 3
TST ,X IX 7D 2
TST opr,SP SP1 9E6D ff 4
TSX Transfer SP to H:X H:X ← (SP) + 1 – – – – – – INH 95 2
TXA Transfer X to A A ← (X) – – – – – – INH 9F 1
TXS Transfer H:X to SP (SP) ← (H:X) – 1 – – – – – – INH 94 2
WAIT Enable Interrupts; Stop Processor I bit ← 0 – – 0 – – – INH 8F 1
A Accumulator n Any bit
C Carry/borrow bit opr Operand (one or two bytes)
CCR Condition code register PC Program counter
dd Direct address of operand PCH Program counter high byte
dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte
DD Direct to direct addressing mode REL Relative addressing mode
DIR Direct addressing mode rel Relative program counter offset byte
DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode
EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode
ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer
H Half-carry bit U Undefined
H Index register high byte V Overflow bit
hh ll High and low bytes of operand address in extended addressing X Index register low byte
I Interrupt mask Z Zero bit
ii Immediate operand byte & Logical AND
IMD Immediate source to direct destination addressing mode | Logical OR
IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR
INH Inherent addressing mode () Contents of
IX Indexed, no offset addressing mode –( ) Negation (two’s complement)
IX+ Indexed, no offset, post increment addressing mode # Immediate value
IX+D Indexed with post increment to direct addressing mode « Sign extend
IX1 Indexed, 8-bit offset addressing mode ← Loaded with
IX1+ Indexed, 8-bit offset, post increment addressing mode ? If
IX2 Indexed, 16-bit offset addressing mode : Concatenated with
M Memory location ↕ Set or cleared
N Negative bit — Not affected
6.8 Opcode Map

See Table 6-2.

MC68HC908MR8 — Rev 4.1

Table 6-2. Opcode Map
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX
MSB
0 1 2 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F
LSB
5 4 3 4 1 1 4 5 3 7 3 2 3 4 4 5 3 4 2
0 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG NEG RTI BGE SUB SUB SUB SUB SUB SUB SUB SUB
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 5 4 4 5 6 4 4 3 2 3 4 4 5 3 4 2
1 BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ CBEQ RTS BLT CMP CMP CMP CMP CMP CMP CMP CMP
3 DIR 2 DIR 2 REL 3 DIR 3 IMM 3 IMM 3 IX1+ 4 SP1 2 IX+ 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 5 7 3 2 3 2 3 4 4 5 3 4 2
2 BRSET1 BSET1 BHI MUL DIV NSA DAA BGT SBC SBC SBC SBC SBC SBC SBC SBC
3 DIR 2 DIR 2 REL 1 INH 1 INH 1 INH 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 9 3 2 3 4 4 5 3 4 2
3 BRCLR1 BCLR1 BLS COM COMA COMX COM COM COM SWI BLE CPX CPX CPX CPX CPX CPX CPX CPX
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 2 2 2 3 4 4 5 3 4 2
4 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR LSR TAP TXS AND AND AND AND AND AND AND AND
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 3 4 3 4 1 2 2 3 4 4 5 3 4 2
5 BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT BIT BIT
3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM 2 DIR 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 2 2 3 4 4 5 3 4 2
6 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR ROR PULA LDA LDA LDA LDA LDA LDA LDA LDA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2
7 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR ASR PSHA TAX AIS STA STA STA STA STA STA STA
5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2
8 BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL LSL PULX CLC EOR EOR EOR EOR EOR EOR EOR EOR
5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2
9 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC ADC ADC
5 4 3 4 1 1 4 5 3 2 2 2 3 4 4 5 3 4 2
A BRSET5 BSET5 BPL DEC DECA DECX DEC DEC DEC PULH CLI ORA ORA ORA ORA ORA ORA ORA ORA
5 4 3 5 3 3 5 6 4 2 2 2 3 4 4 5 3 4 2
B BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ DBNZ PSHH SEI ADD ADD ADD ADD ADD ADD ADD ADD
5 4 3 4 1 1 4 5 3 1 1 2 3 4 3 2
C BRSET6 BSET6 BMC INC INCA INCX INC INC INC CLRH RSP JMP JMP JMP JMP JMP
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 4 3 3 1 1 3 4 2 1 4 4 5 6 5 4
D BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST TST NOP BSR JSR JSR JSR JSR JSR

3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 4 3 5 4 4 4 1 2 3 4 4 5 3 4 2
E BRSET7 BSET7 BIL MOV MOV MOV MOV STOP LDX LDX LDX LDX LDX LDX LDX LDX
3 DIR 2 DIR 2 REL 3 DD 2 DIX+ 3 IMD 2 IX+D 1 INH * 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 3 1 1 3 4 2 1 1 2 3 4 4 5 3 4 2
F BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR CLR WAIT TXA AIX STX STX STX STX STX STX STX
Technical Data
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset MSB
Opcode Map
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset 0 High Byte of Opcode in Hexadecimal
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with LSB
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment 5 Cycles
DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with Low Byte of Opcode in Hexadecimal 0 BRSET0 Opcode Mnemonic
IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment 3 DIR Number of Bytes / Addressing Mode
*Pre-byte for stack pointer indexed instructions
87

Section 7. System Integration Module (SIM)
7.1 Contents
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . .93
7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . .93
7.3.3 Clocks in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . .94
7.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . .95
7.5 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.5.1 SIM Counter During Power-On Reset. . . . . . . . . . . . . . . .99
7.5.2 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . .99
7.6 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.6.1 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
7.6.3 Status Flag Protection in Break Mode . . . . . . . . . . . . . .103
7.7 Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
7.7.3 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . .106
7.7.4 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . .108
7.7.5 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . .109
Freescale Semiconductor System Integration Module (SIM) 89

System Integration Module (SIM)
7.2 Introduction
This section describes the system integration module (SIM). Together
with the central processor unit (CPU), the SIM controls all
microcontroller unit (MCU) activities. A block diagram of the SIM is
shown in Figure 7-1. Figure 7-2 is a summary of the SIM inout/output
(I/O) registers.
The SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop, wait, reset, break entry, and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and
computer operating properly (COP) timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
90 System Integration Module (SIM) Freescale Semiconductor

Introduction
MODULE WAIT
MODULE STOP
STOP/WAIT CPU WAIT (FROM CPU)
CONTROL
CPU STOP (FROM CPU)
SIMOSCEN (TO CGM)
SIM COP CLOCK

COUNTER
CGMXCLK (FROM CGM)

CGMOUT (FROM CGM)
÷2
CLOCK
CONTROL CLOCK GENERATORS INTERNAL CLOCKS
RESET POR CONTROL LVI (FROM LVI MODULE)

PIN LOGIC MASTER ILLEGAL OPCODE (FROM CPU)
RESET PIN CONTROL RESET ILLEGAL ADDRESS (FROM ADDRESS
CONTROL MAP DECODERS)
SIM RESET STATUS REGISTER COP (FROM COP MODULE)
RESET
INTERRUPT CONTROL INTERRUPT SOURCES

AND PRIORITY DECODE
CPU INTERFACE
Figure 7-1. SIM Block Diagram

Read: SBSW
SIM Break Status Register R R R R R R R
Write: Note 1
$FE00 (SBSR)
See page 106. Re-
0
set:
Read: POR PIN COP ILOP ILAD 0 LVI 0

SIM Reset Status Register
Write: R R R R R R R R
$FE01 (SRSR)
See page 108. Re-
1 0 0 0 0 0 0 0
set:
Read:
SIM Break Flag Control BCFE R R R R R R R
Write:
$FE03 Register (SBFCR)
See page 109. Re-
0
set:
Note 1. Writing a logic 0 clears SB- = Reserved

R
SW.
Figure 7-2. SIM I/O Register Summary
Table 7-1 shows the internal signal names used in this section.
Table 7-1. Signal Name Conventions

Signal Name Description
CGMXCLK Buffered version of OSC1 from clock generator module (CGM)
CGMVCLK PLL output
PLL-based or OSC1-based clock output from CGM module
CGMOUT
(bus clock = CGMOUT divided by two)
IAB Internal address bus
IDB Internal data bus
PORRST Signal from the power-on reset module to the SIM
IRST Internal reset signal
R/W Read/write signal

SIM Bus Clock Control and Generation
7.3 SIM Bus Clock Control and Generation

The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 7-3. This clock can come
from either an external oscillator or from the on-chip phase-locked loop
(PLL). See Section 8. Clock Generator Module (CGM).
CGMXCLK
OSC1 SIM COUNTER
CLOCK A CGMOUT
SELECT ÷2 ÷2 BUS CLOCK
CGMVCLK CIRCUIT B S* GENERATORS
*When S = 1,
CGMOUT = B
PLL
BCS SIM
MONITOR MODE
USER MODE
CGM
Figure 7-3. CGM Clock Signals
7.3.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See Section 8. Clock Generator Module (CGM).
7.3.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after the 4096 CGMXCLK
cycle POR timeout has completed. The RST pin is driven low by the SIM
during this entire period. The IBUS clocks start upon completion of the
timeout.

7.3.3 Clocks in Wait Mode
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
7.4 Reset and System Initialization

The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in

monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see 7.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR). See 7.7.4 SIM Reset Status
Register.
7.4.1 External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit
of the SIM reset status register (SRSR) is set as long as RST is held low
for a minimum of 67 CGMXCLK cycles, assuming that neither the POR
nor the LVI was the source of the reset. See Table 7-2 for details.
Figure 7-4 shows the relative timing.

Reset and System Initialization
Table 7-2. PIN Bit Set Timing

Reset Type Number of Cycles Required to set PIN
POR/LVI 4163 (4096 + 64 + 3)
All Others 67 (64 + 3)
CGMOUT
RST
IAB PC VECT H VECT L
Figure 7-4. External Reset Timing
7.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
(IRST) continues to be asserted for an additional 32 cycles (see
Figure 7-5). An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, or POR (see Figure 7-6).
NOTE: For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal
then follows the sequence from the falling edge of RST as shown in
Figure 7-5.
IRST
RST RST PULLED LOW BY MCU
32 CYCLES 32 CYCLES
CGMXCLK
IAB VECTOR HIGH
Figure 7-5. Internal Reset Timing

The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST

ILLEGAL OPCODE RST
COPRST INTERNAL RESET
LVI
POR
Figure 7-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
7.4.2.1 Power-On Reset (POR)
When power is first applied to the MCU, the power-on reset (POR)
module generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, these events occur:

• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables CGMOUT.
• Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.

Reset and System Initialization
OSC1
PORRST
4096 32 32
CYCLES CYCLES CYCLES
CGMXCLK
CGMOUT
RST
IAB $FFFE $FFFF
Figure 7-7. POR Recovery
7.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.

Writing to location $FFFF clears the COP counter and bits 12–4 of the
SIM counter. The SIM counter output, which occurs at least every
213–24 CGMXCLK cycles, drives the COP counter. The COP should be
serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at
VDD + VHI while the MCU is in monitor mode. The COP module can be
disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ pin. This prevents the COP from
becoming disabled as a result of external noise. During a break state,
VDD + VHI on the RST pin disables the COP module.

7.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
Because the MC68HC08MR8 has stop mode disabled by bit 1 in the

CONFIG register, execution of the STOP instruction will cause an illegal
opcode reset if stop mode has not been enabled by setting CONFIG
register bit 1.
7.4.2.4 Illegal Address Reset
An opcode fetch from addresses other than FLASH, I/O, or RAM

addresses generates an illegal address reset (unimplemented locations
within memory map). The SIM verifies that the CPU is fetching an
opcode prior to asserting the ILAD bit in the SIM reset status register
(SRSR) and resetting the MCU. A data fetch from an unmapped address
does not generate a reset.
7.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the VDD voltage falls to the LVILVRX voltage and remains at or below that
level for at least nine consecutive CPU cycles. The LVI bit in the SIM
reset status register (SRSR) is set, and the external reset pin (RST) is
held low while the SIM counter counts out 4096 CGMXCLK cycles.
Sixty-four CGMXCLK cycles later, the CPU is released from reset to
allow the reset vector sequence to occur. The SIM actively pulls down
the RST pin for all internal reset sources.

SIM Counter
7.5 SIM Counter

The SIM counter is used by the POR module to allow the oscillator time
to stabilize before enabling the internal bus (IBUS) clocks. The SIM
counter also serves as a prescaler for the COP module. The SIM counter
overflow supplies the clock for the COP module. The SIM counter is 13
bits long and is clocked by the falling edge of CGMXCLK.
7.5.1 SIM Counter During Power-On Reset
The POR detects power applied to the MCU. At power-on, the POR
circuit asserts the signal PORRST. Once the SIM is initialized, it enables
the clock generation module (CGM) to drive the bus clock state machine.
7.5.2 SIM Counter and Reset States
External reset has no effect on the SIM counter. The SIM counter is
free-running after all reset states. See 7.4.2 Active Resets from
Internal Sources for counter control and internal reset recovery
sequences.
7.6 Exception Control

Normal, sequential program execution can be changed in three different
ways:
1. Interrupts:
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
2. Reset
3. Break interrupts

7.6.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register

contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the return from interrupt
(RTI) instruction recovers the CPU register contents from the stack so
that normal processing can resume. Figure 7-8 shows interrupt entry
timing. Figure 7-10 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared). See
Figure 7-9.
MODULE
INTERRUPT
I BIT
IAB DUMMY SP SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
IDB DUMMY PC – 1[7:0] PC – 1[15:8] X A CCR V DATA H V DATA L OPCODE
R/W
Figure 7-8. Interrupt Entry

Exception Control
FROM RESET
YES
BREAK INTERRUPT?
I BIT SET?
NO
YES
I BIT SET?
NO
INT0 YES
INTERRUPT?
NO
INT1 YES
INTERRUPT?
NO STACK CPU REGISTERS

SET I BIT
AS MANY INTERRUPTS AS EXIST ON CHIP LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI YES
INSTRUCTION?
NO
RTI YES
INSTRUCTION? UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 7-9. Interrupt Processing

MODULE
INTERRUPT
I BIT
IAB SP – 4 SP – 3 SP – 2 SP – 1 SP PC PC + 1
IDB CCR A X PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND
R/W
Figure 7-10. Interrupt Recovery
7.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of

a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction

execution, the highest priority interrupt is serviced first. Figure 7-11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE: To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.

Exception Control
CLI
LDA #$FF BACKGROUND ROUTINE
INT1 PSHH
INT1 INTERRUPT SERVICE ROUTINE

PULH
RTI
INT2 PSHH
INT2 INTERRUPT SERVICE ROUTINE

PULH
RTI
Figure 7-11. Interrupt Recognition Example
7.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an

interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE: A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
7.6.2 Reset
All reset sources always have equal and highest priority and cannot be
arbitrated.
7.6.3 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).

Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a 2-step clearing mechanism — for example, a read of
one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as normal.
7.7 Low-Power Mode

Executing the WAIT or STOP instruction puts the MCU in a low
power-consumption mode for standby situations. The SIM holds the
CPU in a non-clocked state. Both STOP and WAIT clear the interrupt
mask (I) in the condition code register, allowing interrupts to occur.
7.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run. Figure 7-12 shows the timing for wait mode entry.
IAB WAIT ADDR WAIT ADDR + 1 SAME SAME
IDB PREVIOUS DATA NEXT OPCODE SAME SAME
R/W
Note: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 7-12. Wait Mode Entry Timing
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module

Low-Power Mode
is active or inactive in wait mode. Some modules can be programmed to

be active in wait mode.
Wait mode can also be exited by a reset or break. A break interrupt

during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM
break status register (SBSR). If the COP disable bit, COPD, in the
configuration register is logic 0, then the computer operating properly
module (COP) is enabled and remains active in wait mode.
Figure 7-13 and Figure 7-14 show the timing for wait recovery.
IAB $6E0B $6E0C $00FF $00FE $00FD $00FC
IDB $A6 $A6 $A6 $01 $0B $6E
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin or CPU interrupt or break interrupt
Figure 7-13. Wait Recovery from Interrupt or Break
32 32
CYCLES CYCLES
IAB $6E0B RST VCT H RST VCT L
IDB $A6 $A6 $A6
RST
CGMXCLK
Figure 7-14. Wait Recovery from Internal Reset

7.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clock is disabled.
An external interrupt request will cause an exit from stop mode. Stacking
for interrupts begins after the stop recovery delay time of 4096
CGMXCLK cycles has elapsed. Reset or break also cause an exit from
stop mode.
The SIM disables the clock generator module outputs in stop mode,
stopping the CPU and all peripherals.
NOTE: It is important to note that when using the PWM generator Its outputs will
stop toggling when stop mode is entered. The PWM module must be
disabled before entering stop mode to prevent external inverter failure.
7.7.3 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from wait mode.
Ad- $FE00
dress:
BIt 7 6 5 4 3 2 1 Bit 0
Read: SBSW
R R R R R R R
Write: Note(1)
Reset: 0
R = Reserved 1. Writing a logic 0 clears SBSW.
Figure 7-15. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit

This status bit is useful in applications requiring a return to wait mode
after exiting from a break interrupt. Clear SBSW by writing a logic 0 to
it. Reset clears SBSW.
1 = Wait mode was exited by break interrupt.
0 = Wait mode was not exited by break interrupt.

Low-Power Mode
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing 0 to the SBSW bit
clears it.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the break
; service routine software.
HIBYTE EQU 5
LOBYTE EQU 6
; If not SBSW, do RTI
BRCLR SBSW,SBSR, RETURN ; See if wait mode was exited by break.

;
TST LOBYTE,SP ; If RETURNLO is not zero,
BNE DOLO ; then just decrement low byte.
DEC HIBYTE,SP ; Else deal with high byte, too.
DOLO DEC LOBYTE,SP ; Point to WAIT opcode.
RETURN PULH ; Restore H register.

RTI

7.7.4 SIM Reset Status Register
The SIM reset status register (SRSR) contains six flags that show the
source of the last reset. Clear the SRSR by reading it. A power-on reset
sets the POR bit and clears all other bits in the register.
Ad- $FE01
dress:
BIt 7 6 5 4 3 2 1 Bit 0
Read: POR PIN COP ILOP ILAD 0 LVI 0
Reset: 1 0 0 0 0 0 0 0
R = Reserved
Figure 7-16. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit

1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset was caused by the LVI circuit

Low-Power Mode
7.7.5 SIM Break Flag Control Register
The SIM break control register (SBFCR) contains a bit that enables
software to clear status bits while the MCU is in a break state.
Ad- $FE03
dress:
BIt 7 6 5 4 3 2 1 Bit 0
Read:
BCFE R R R R R R R
Write:
Reset: 0
R = Reserved
Figure 7-17. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit

This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break


Section 8. Clock Generator Module (CGM)
8.1 Contents
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
8.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . .113
8.4.2 Phase-Locked Loop Circuit (PLL). . . . . . . . . . . . . . . . . .115
8.4.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . .121
8.4.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . .122
8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
8.5.1 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . .122
8.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . .123
8.5.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . .123
8.5.4 PLL Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . .124
8.5.5 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . .124
8.5.6 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . 124
8.5.7 CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . .124
8.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . .124
8.6 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
8.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . .129
8.6.3 PLL Programming Register. . . . . . . . . . . . . . . . . . . . . . .131
8.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
8.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
8.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
8.10 CGM During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .133
8.11 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . .134
8.11.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . .134
8.11.2 Parametric Influences on Reaction Time . . . . . . . . . . . .135
Freescale Semiconductor Clock Generator Module (CGM) 111

Clock Generator Module (CGM)
8.11.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . .136

8.11.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . .137
8.2 Introduction
This section describes the clock generator module (CGM, version A).
The CGM generates the crystal clock signal, CGMXCLK, which operates
at the frequency of the crystal. The CGM also generates the base clock
signal, CGMOUT, from which the system integration module (SIM)
derives the system clocks.
CGMOUT is based on either the crystal clock divided by two or the

phase-locked loop (PLL) clock, CGMVCLK, divided by two. The PLL is
a frequency generator designed for use with crystals or ceramic
resonators. The PLL can generate an 8-MHz bus frequency without
using a 32-MHz crystal.
8.3 Features
Features of the CGM include:
• Phase-locked loop with output frequency in integer multiples of the
crystal reference
• Programmable hardware voltage-controlled oscillator (VCO) for
low-jitter operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• Central processor unit (CPU) interrupt on entry or exit from locked
condition
112 Clock Generator Module (CGM) Freescale Semiconductor

Functional Description

The CGM consists of three major submodules:
1. Crystal oscillator circuit — The crystal oscillator circuit generates
the constant crystal frequency clock, CGMXCLK.
2. Phase-locked loop (PLL) — The PLL generates the
programmable VCO frequency clock, CGMVCLK.
3. Base clock selector circuit — This software-controlled circuit
selects either CGMXCLK divided by two or the VCO clock,
CGMVCLK, divided by two as the base clock, CGMOUT. The SIM
derives the system clocks from CGMOUT.
Figure 8-1 shows the structure of the CGM.
8.4.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an

external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal from the system integration
module (SIM) enables the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. CGMXCLK is then buffered
to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing

for operation. The duty cycle of CGMXCLK is not guaranteed to be
50 percent and depends on external factors, including the crystal and
related external components.
An externally generated clock also can feed the OSC1 pin of the crystal
oscillator circuit. Connect the external clock to the OSC1 pin and let the
OSC2 pin float.

CRYSTAL OSCILLATOR
OSC2
CGMXCLK
TO SIM
OSC1 CLOCK A CGMOUT

SELECT ÷2 TO SIM
CIRCUIT B S*
SIMOSCEN *WHEN S = 1, CGMOUT = B
CGMRDV CGMRCLK BCS
VDDA CGMXFC VSS USER MODE
VRS[7:4] MONITOR MODE
PHASE LOOP VOLTAGE

DETECTOR FILTER CONTROLLED
OSCILLATOR
PLL ANALOG
LOCK BANDWIDTH INTERRUPT CGMINT

DETECTOR CONTROL CONTROL
LOCK AUTO ACQ PLLIE PLLF
MUL[7:4]
CGMVDV FREQUENCY CGMVCLK

DIVIDER
Figure 8-1. CGM Block Diagram

Read
PLLF 1 1 1 1
:
Write
$005C (PCTL) R R R R R
:
See page 126.
Re-
0 0 1 0 1 1 1 1
set:
Read
LOCK 0 0 0 0
:
PLL Bandwidth Control Reg- AUTO ACQ XLD
Write
$005D ister (PBWC) R R R R R
:
See page 129.
Re-
0 0 0 0 0 0 0 0
set:
Read
:
PLL Programming Register MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
Write
$005E (PPG)
:
See page 131.
Re-
0 1 1 0 0 1 1 0
set:
R = Reserved
Figure 8-2. CGM I/O Register Summary
8.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition

mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
8.4.2.1 PLL Circuits
The PLL consists of these circuits:

• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider

• Phase detector
• Loop filter
• Lock detector

The operating range of the VCO is programmable for a wide range of

frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, fVRS.
Modulating the voltage on the CGMXFC pin changes the frequency
within this range. By design, fVRS is equal to the nominal center-of-range
frequency, fNOM, (4.9152 MHz) times a linear factor L, or (L) fNOM.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.

CGMRCLK runs at a frequency, fRCLK, and is fed to the PLL through a
buffer. The buffer output is the final reference clock, CGMRDV, running
at a frequency, fRDV = fRCLK.
The VCO’s output clock, CGMVCLK, running at a frequency fVCLK, is fed

back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor, N. The divider’s output is the VCO
feedback clock, CGMVDV, running at a frequency, fVDV = fVCLK/N. See
8.4.2.4 Programming the PLL for more information.
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the dc voltage on the external capacitor connected to
CGMXFC based on the width and direction of the correction pulse. The
filter can make fast or slow corrections depending on its mode,
described in 8.4.2.2 Acquisition and Tracking Modes. The value of the
external capacitor and the reference frequency determines the speed of
the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, fRDV. The circuit determines the mode of the PLL and the lock
condition based on this comparison.

8.4.2.2 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two

operating modes:
• Acquisition mode — In acquisition mode, the filter can make large

frequency corrections to the VCO. This mode is used at PLL
startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in
acquisition mode, the ACQ bit is clear in the PLL bandwidth control
register. See 8.6.2 PLL Bandwidth Control Register.
• Tracking mode — In tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. The PLL is automatically in tracking mode when not in
acquisition mode or when the ACQ bit is set. See 8.4.3 Base
Clock Selector Circuit.
8.4.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector

automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT (8.6.2 PLL Bandwidth Control Register). If PLL interrupts
are enabled, the software can wait for a PLL interrupt request and then
check the LOCK bit. If interrupts are disabled, software can poll the
LOCK bit continuously (during PLL startup, usually) or at periodic
intervals. In either case, when the LOCK bit is set, the VCO clock is safe
to use as the source for the base clock (see 8.4.3 Base Clock Selector
Circuit). If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
software must take appropriate action, depending on the application.
See 8.7 Interrupts for information and precautions on using interrupts.

These conditions apply when the PLL is in automatic bandwidth control

mode:
• The ACQ bit (see 8.6.2 PLL Bandwidth Control Register) is a
read-only indicator of the mode of the filter. See 8.4.2.2
Acquisition and Tracking Modes.
• The ACQ bit is set when the VCO frequency is within a certain
tolerance, ∆TRK, and is cleared when the VCO frequency is out of
a certain tolerance, ∆UNT. See 8.11 Acquisition/Lock Time
Specifications for more information.
• The LOCK bit is a read-only indicator of the locked state of the
PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance, ∆Lock, and is cleared when the VCO frequency is out of
a certain tolerance, ∆UNL. See 8.11 Acquisition/Lock Time
Specifications for more information.
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. See 8.6.1 PLL
Control Register.
The PLL also may operate in manual mode (AUTO = 0). Manual mode
is used by systems that do not require an indicator of the lock condition
for proper operation. Such systems typically operate well below fBUSMAX
and require fast startup.
These conditions apply when in manual mode:

• ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
• Before entering tracking mode (ACQ = 1), software must wait a
given time, tACQ (see 8.11 Acquisition/Lock Time
Specifications), after turning on the PLL by setting PLLON in the
PLL control register (PCTL).
• Software must wait a given time, tAL, after entering tracking mode
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.

8.4.2.4 Programming the PLL
This procedure shows how to program the PLL.
NOTE: The round function in the following equations means that the real
number should be rounded to the nearest integer number.
1. Choose the desired bus frequency, fBUSDES.

2. Calculate the desired VCO frequency (four times the desired bus
frequency).
f = 4×f
VCLKDES BUSDES
3. Choose a practical PLL reference frequency, fRCLK.

4. Select a VCO frequency multiplier, N.
5. Calculate and verify the adequacy of the VCO and bus
frequencies fVCLK and fBUS.
f = N×f
VCLK RCLK
f = (f )⁄4
BUS VCLK
6. Select a VCO linear range multiplier, L.

where fNOM = 4.9152 MHz
7. Calculate and verify the adequacy of the VCO programmed
center-of-range frequency, fVRS.
fVRS = (L) fNOM
8. Verify the choice of N and L by comparing fVCLK to fVRS and

fVCLKDES. For proper operation, fVCLK must be within the
application’s tolerance of fVCLKDES, and fVRS must be as close as
possible to fVCLK.
CAUTION: Exceeding the recommended maximum bus frequency or VCO

frequency can crash the MCU.
9. Program the PLL registers accordingly:

a. In the upper four bits of the PLL programming register (PPG),
program the binary equivalent of N.
b. In the lower four bits of the PLL programming register (PPG),
program the binary equivalent of L.

8.4.2.5 Special Programming Exceptions
The programming method described in 8.4.2.4 Programming the PLL

does not account for possible exceptions. A value of 0 for N or L is
meaningless when used in the equations given. To account for these
exceptions:
• A 0 value for N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the
source for the base clock. See 8.4.3 Base Clock Selector
Circuit.
8.4.3 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the
VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The
two input clocks go through a transition control circuit that waits up to
three CGMXCLK cycles and three CGMVCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in state.
The output of the transition control circuit is then divided by two to correct
the duty cycle. Therefore, the bus clock frequency, which is one-half of
the base clock frequency, is one-fourth the frequency of the selected
clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the VCO clock. The VCO clock also cannot
be selected as the base clock source if the factor L is programmed to a 0.
This value would set up a condition inconsistent with the operation of the
PLL, so that the PLL would be disabled and the crystal clock would be
forced as the source of the base clock.

8.4.4 CGM External Connections
In its typical configuration, the CGM requires seven external

components. Five of these are for the crystal oscillator and two are for
the PLL.
The crystal oscillator is normally connected in a Pierce oscillator

configuration, as shown in Figure 8-3. Figure 8-3 shows only the logical
representation of the internal components and may not represent actual
circuitry.
The oscillator configuration uses five components:

1. Crystal, X1
2. Fixed capacitor, C1
3. Tuning capacitor, C2 (can also be a fixed capacitor)
4. Feedback resistor, RB
5. Series resistor, RS (optional)
The series resistor (RS) is included in the diagram to follow strict Pierce
oscillator guidelines and may not be required for all ranges of operation,
especially with high frequency crystals. Refer to the crystal
manufacturer’s data for more information.
Figure 8-3 also shows the external components for the PLL:
• Bypass capacitor, CBYP
• Filter capacitor, CF
Routing should be done with great care to minimize signal cross talk and
noise. See 8.11 Acquisition/Lock Time Specifications for routing
information and more information on the filter capacitor’s value and its
effects on PLL performance.

I/O Signals
SIMOSCEN
CGMXCLK
OSC1 OSC2 VSS CGMXFC VDDA
VDD
CF
RS *
RB CBYP
X1
C1 C2
*RS can be 0 (shorted) when used with higher-frequency crystals.

Refer to manufacturer’s data.
Figure 8-3. CGM External Connections
8.5 I/O Signals

The following paragraphs describe the CGM input/output (I/O) signals.
8.5.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
8.5.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
8.5.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase
corrections. A small external capacitor is connected to this pin.
NOTE: To prevent noise problems, CF should be placed as close to the

CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the CF connection.

8.5.4 PLL Analog Power Pin (VDDA)
VDDA is a power pin used by the analog portions of the PLL. Connect the
VDDA pin to the same voltage potential as the VDD pin.
NOTE: Route VDDA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
8.5.5 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator and PLL.
8.5.6 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (fXCLK) and comes directly from the crystal oscillator circuit.
Figure 8-3 shows only the logical relation of CGMXCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
8.5.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM,
which generates the MCU clocks. CGMOUT is a 50 percent duty cycle
clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by
two or the VCO clock, CGMVCLK, divided by two.
8.5.8 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.

CGM Registers
8.6 CGM Registers

These registers control and monitor operation of the CGM:
• PLL control register (PCTL), see 8.6.1 PLL Control Register
• PLL bandwidth control register (PBWC), see 8.6.2 PLL
Bandwidth Control Register
• PLL programming register (PPG), see 8.6.3 PLL Programming
Register
Figure 8-4 is a summary of the CGM registers.
Read
PLLF 1 1 1 1
:
Write
$005C (PCTL) R R R R R
:
See page 126.
Re-
0 0 1 0 1 1 1 1
set:
Read
LOCK 0 0 0 0
:
PLL Bandwidth Control Reg- AUTO ACQ XLD
Write
$005D ister (PBWC) R R R R R
:
See page 129.
Re-
0 0 0 0 0 0 0 0
set:

Read
:
PLL Programming Register MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
Write
$005E (PPG)
:
See page 131.
Re-
0 1 1 0 0 1 1 0
set:
R = Reserved
Notes:
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
8.6.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, and the base clock selector bit.
Ad- $005C
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: PLLF 1 1 1 1
PLLIE PLLON BCS
Write: R R R R R
Reset: 0 0 1 0 1 1 1 1
R = Reserved
Figure 8-5. PLL Control Register (PCTL)

CGM Registers
PLLIE — PLL Interrupt Enable Bit

This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE: Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit

This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). Reset sets this bit so that the loop
can stabilize as the MCU is powering up. See 8.4.3 Base Clock
Selector Circuit.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output,
CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM
output, CGMOUT. CGMOUT frequency is one-half the frequency of
the selected clock. BCS cannot be set while the PLLON bit is clear.
After toggling BCS, it may take up to three CGMXCLK and three
CGMVCLK cycles to complete the transition from one source clock to
the other. During the transition, CGMOUT is held in stasis. Reset
clears the BCS bit. See 8.4.3 Base Clock Selector Circuit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT

NOTE: PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. See 8.4.3 Base Clock Selector Circuit.
PCTL Bits 3–0 — Unimplemented Bits

These bits provide no function and always read as logic 1s.

CGM Registers
8.6.2 PLL Bandwidth Control Register
The PLL bandwidth control register:

• Selects automatic or manual (software-controlled) bandwidth
control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking
mode
Ad- $005D
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: LOCK 0 0 0 0
AUTO ACQ XLD
Write: R R R R R
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Figure 8-6. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit

This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked

ACQ — Acquisition Mode Bit

When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
XLD — Crystal Loss Detect Bit

When the VCO output, CGMVCLK, is driving CGMOUT, this
read/write bit can indicate whether the crystal reference frequency is
active or not. To check the status of the crystal reference, follow these
steps:
1. Write a logic 1 to XLD.
2. Wait N × 4 cycles. (N is the VCO frequency multiplier.)
3. Read XLD.
1 = Crystal reference is not active.
0 = Crystal reference is active.
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD
always reads as logic 0.
PBWC Bits 3–0 — Reserved for Test

These bits enable test functions not available in user mode. To ensure
software portability from development systems to user applications,
software should write 0s to PBWC[3:0] whenever writing to PBWC.

CGM Registers
8.6.3 PLL Programming Register
The PLL programming register (PPG) contains the programming

information for the modulo feedback divider and the programming
information for the hardware configuration of the VCO.
Ad- $005E
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
Write:
Reset: 0 1 1 0 0 1 1 0
Figure 8-7. PLL Programming Register (PPG)
MUL[7:4] — Multiplier Select Bits

These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. See 8.4.2.1 PLL Circuits and
8.4.2.4 Programming the PLL. A value of $0 in the multiplier select
bits configures the modulo feedback divider the same as a value of
$1. Reset initializes these bits to $6 to give a default multiply value
of 6.
Table 8-1. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4 VCO Frequency Multiplier (N)
0000 1
0001 1
0010 2
0011 3
1101 13
1110 14
1111 15
NOTE: The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).

VRS[7:4] — VCO Range Select Bits

These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency
fVRS. See 8.4.2.1 PLL Circuits, 8.4.2.4 Programming the PLL, and
8.6.1 PLL Control Register. VRS[7:4] cannot be written when the
PLLON bit in the PLL control register (PCTL) is set. See 8.4.2.5
Special Programming Exceptions. A value of $0 in the VCO range
select bits disables the PLL and clears the BCS bit in the PCTL. See
8.4.3 Base Clock Selector Circuit and 8.4.2.5 Special
Programming Exceptions for more information.
Reset initializes the bits to $6 to give a default range multiply
value of 6.
NOTE: The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect

programming may result in failure of the PLL to achieve lock.
8.7 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,
becomes set whether interrupts are enabled or not. When the AUTO bit
is clear, CPU interrupts from the PLL are disabled and PLLF reads as
logic 0.
Software should read the LOCK bit after a PLL interrupt request to see
if the request was due to an entry into lock or an exit from lock. When the
PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not

Wait Mode
frequency-sensitive, interrupts should be disabled to prevent PLL

interrupt service routines from impeding software performance or from
exceeding stack limitations.
NOTE: Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
8.8 Wait Mode

The WAIT instruction puts the MCU in low power-consumption standby
mode.
The WAIT instruction does not affect the CGM. Before entering wait
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
8.9 Stop Mode

The STOP instruction puts the MCU in low power-consumption standby
mode.
The STOP instruction disables the CGMC (oscillator and phase-lock

loop) and holds the CGM outputs low.
8.10 CGM During Break Mode

The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See 7.7.5 SIM Break Flag Control
Register.
To allow software to clear status bits during a break interrupt, write a

logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.

To protect the PLLF bit during the break state, write a logic 0 to the
BCFE bit. With BCFE at logic 0 (its default state), software can read and
write the PLL control register during the break state without affecting the
PLLF bit.
8.11 Acquisition/Lock Time Specifications

The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.
8.11.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the
reaction time, within specified tolerances, of the system to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance is usually specified as a percent of the
step input or when the output settles to the desired value plus or minus
a percent of the frequency change. Therefore, the reaction time is
constant in this definition, regardless of the size of the step input. For
example, consider a system with a 5 percent acquisition time tolerance.
If a command instructs the system to change from 0 Hz to 1 MHz, the
acquisition time is the time taken for the frequency to reach
1 MHz ± 50 kHz. Fifty kHz = 5 percent of the 1-MHz step input. If the
system is operating at 1 MHz and suffers a –100-kHz noise hit, the
acquisition time is the time taken to return from 900 kHz to
1 MHz ± 5 kHz. Five kHz = 5 percent of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.

Acquisition/Lock Time Specifications
The discrepancy in these definitions makes it difficult to specify an

acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are:
• Acquisition time, tACQ, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance, ∆TRK.
Acquisition time is based on an initial frequency error,
(fDES– fORIG)/fDES, of not more than ±100 percent. In automatic
bandwidth control mode (see 8.4.2.3 Manual and Automatic PLL
Bandwidth Modes), acquisition time expires when the ACQ bit
becomes set in the PLL bandwidth control register (PBWC).
• Lock time, tLock, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance, ∆Lock. Lock
time is based on an initial frequency error, (fDES–fORIG)/fDES, of
not more than ± 100 percent. In automatic bandwidth control
mode, lock time expires when the LOCK bit becomes set in the
PLL bandwidth control register (PBWC). See 8.4.2.3 Manual and
Automatic PLL Bandwidth Modes.
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
8.11.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while

still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL
is the reference frequency, fRDV. This frequency is the input to the phase
detector and controls how often the PLL makes corrections. For stability,
the corrections must be small compared to the desired frequency, so
several corrections are required to reduce the frequency error.
Therefore, the slower the reference the longer it takes to make these
corrections. This parameter is also under user control via the choice of
crystal frequency, fXCLK.

Another critical parameter is the external filter capacitor. The PLL

modifies the voltage on the VCO by adding or subtracting charge from
this capacitor. Therefore, the rate at which the voltage changes for a
given frequency error (thus change in charge) is proportional to the
capacitor size. The size of the capacitor also is related to the stability of
the PLL. If the capacitor is too small, the PLL cannot make small enough
adjustments to the voltage and the system cannot lock. If the capacitor
is too large, the PLL may not be able to adjust the voltage in a
reasonable time. See 8.11.3 Choosing a Filter Capacitor.
Also important is the operating voltage potential applied to VDDA. The

power supply potential alters the characteristics of the PLL. A fixed value
is best. Variable supplies, such as batteries, are acceptable if they vary
within a known range at very slow speeds. Noise on the power supply is
not acceptable, because it causes small frequency errors which
continually change the acquisition time of the PLL.
Temperature and processing also can affect acquisition time because

the electrical characteristics of the PLL change. The part operates as
specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of
the PLL. These factors include noise injected into the PLL through the
filter capacitor, filter capacitor leakage, stray impedances on the circuit
board, and even humidity or circuit board contamination.
8.11.3 Choosing a Filter Capacitor
As described in 8.11.2 Parametric Influences on Reaction Time, the

external filter capacitor, CF, is critical to the stability and reaction time of
the PLL. The PLL is also dependent on reference frequency and supply
voltage. The value of the capacitor must, therefore, be chosen with
supply potential and reference frequency in mind. For proper operation,
the external filter capacitor must be chosen according to this equation:
 V DDA
-----------------
FACT  f
C = C
F
RDV 
For acceptable values of CFACT, see 8.11 Acquisition/Lock Time

Specifications. For the value of VDDA, choose the voltage potential at
which the MCU is operating. If the power supply is variable, choose a
value near the middle of the range of possible supply values.

Acquisition/Lock Time Specifications
This equation does not always yield a commonly available capacitor

size, so round to the nearest available size. If the value is between two
different sizes, choose the higher value for better stability. Choosing the
lower size may seem attractive for acquisition time improvement, but the
PLL can become unstable. Also, always choose a capacitor with a tight
tolerance (±20 percent or better) and low dissipation.
8.11.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the
equations here. These equations yield nominal values under these
conditions:
• Correct selection of filter capacitor, CF; see 8.11.3 Choosing a
Filter Capacitor
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters.

KACQ is the K factor when the PLL is configured in acquisition mode, and
KTRK is the K factor when the PLL is configured in tracking mode. See
8.4.2.2 Acquisition and Tracking Modes.
 V DDA 8
t =  -----------------  -----------------
ACQ  RDV  ACQ
f  K
 V DDA 4
t =  -----------------  ----------------
AL  RDV  TRK
f  K
t = t +t
Lock ACQ AL
NOTE: Inverse proportionality between the lock time and the reference
frequency
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency, see 8.4.2.3
Manual and Automatic PLL Bandwidth Modes. A certain number of
clock cycles, nACQ, is required to ascertain that the PLL is within the
tracking mode entry tolerance, ∆TRK, before exiting acquisition mode. A

certain number of clock cycles, nTRK, is required to ascertain that the

PLL is within the lock mode entry tolerance, ∆Lock. Therefore, the
acquisition time, tACQ, is an integer multiple of nACQ/fRDV, and the
acquisition to lock time, tAL, is an integer multiple of nTRK/fRDV. Also,
since the average frequency over the entire measurement period must
be within the specified tolerance, the total time usually is longer than
tLock as calculated above.
In manual mode, it is usually necessary to wait considerably longer than

tLock before selecting the PLL clock (see 8.4.3 Base Clock Selector
Circuit) because the factors described in 8.11.2 Parametric Influences
on Reaction Time may slow the lock time considerably.


(PWMMC)
9.1 Contents
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
9.4 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
9.4.1 Resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
9.4.2 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
9.5 PWM Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
9.5.1 Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
9.5.2 PWM Data Overflow and Underflow Conditions . . . . . .152
9.6 Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
9.6.1 Selecting Six Independent PWMs or Three
Complementary PWM Pairs. . . . . . . . . . . . . . . . . . . . . . .152
9.6.2 Dead-Time Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
9.6.3 Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
9.6.4 Output Port Control Register . . . . . . . . . . . . . . . . . . . . .159
9.7 Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
9.7.1 Fault Condition Input Pins. . . . . . . . . . . . . . . . . . . . . . . .164
9.7.2 Software Output Disable . . . . . . . . . . . . . . . . . . . . . . . . .168
9.7.3 Output Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
9.8 Initialization and the PWMEN Bit. . . . . . . . . . . . . . . . . . . . .169
9.9 PWM Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . .170
9.10 PWM Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . .170
9.11 PWM Operation in Break Mode . . . . . . . . . . . . . . . . . . . . . .171
9.12 Control Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
9.12.1 PWM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . .172
9.12.2 PWM Counter Modulo Registers. . . . . . . . . . . . . . . . . . .173
9.12.3 PWMx Value Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .174
9.12.4 PWM Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . .175
Freescale Semiconductor Pulse-Width Modulator for Motor Control (PWMMC) 139

Pulse-Width Modulator for Motor Control
9.12.5 PWM Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . .177

9.12.6 Dead-Time Write-Once Register . . . . . . . . . . . . . . . . . . .179
9.12.7 PWM Disable Mapping Write-Once Register . . . . . . . . .179
9.12.8 Fault Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .180
9.12.9 Fault Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
9.12.10 Fault Acknowledge Register . . . . . . . . . . . . . . . . . . . . . .182
9.12.11 PWM Output Control Register. . . . . . . . . . . . . . . . . . . . .184
9.13 PWM Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
9.2 Introduction
This section describes the pulse-width modulator for motor control
(PWMMC, version A). The MC68HC908MR8 PWM module can
generate three complementary PWM pairs or six independent PWM
signals. These PWM signals can be center-aligned or edge-aligned. A
block diagram of the PWM module is shown in Figure 9-1.
A 12-bit timer PWM counter is common to all six channels. PWM

resolution is one clock period for edge-aligned operation and two clock
periods for center-aligned operation. The clock period is dependent on
the internal operating frequency (fOP) and a programmable prescaler.
The highest resolution for edge-aligned operation is 125 ns
(fOP = 8 MHz). The highest resolution for center-aligned operation is
250 ns (fOP = 8 MHz).
When generating complementary PWM signals, the module features

automatic dead-time insertion to the PWM output pairs.
A summary of the PWM registers is shown in Figure 9-2.
140 Pulse-Width Modulator for Motor Control (PWMMC) Freescale Semiconductor

Pulse-Width Modulator for Motor Control (PWMMC)
Features
9.3 Features
Features of the PWMMC include:
• Three complimentary PWM pairs or six independent PWM signals
• Edge-aligned PWM signals or center-aligned PWM signals
• PWM signal polarity control
• Manual PWM output control through software
• Programmable fault protection
• Complimentary mode also features:
– Dead-time insertion
– Separate top/bottom pulse width correction via current sensing
or programmable software bits
8
CPU BUS
PWM1 PIN
PWM CHANNELS 1 & 2
PWM2 PIN
OUTPUT CONTROL
FAULT PROTECTION
CONTROL LOGIC BLOCK
PWM3 PIN
PWM CHANNELS 3 & 4
PWM4 PIN
PWM5 PIN
PWM CHANNELS 5 & 6
PWM6 PIN
2 FAULT
12 INTERRUPT
PINS
TIMEBASE
Figure 9-1. PWM Module Block Diagram


Read: PWMIN PWME
PWM Control Register 1 DISX DISY PWMF LDOK
Write: T N
$0020 (PCTL1)
See page 175. Reset
0 0 0 0 0 0 0 0
:
Read: 0
PWM Control Register 2 LDFQ1 LDFQ0 SEL12 SEL34 SEL56 PRSC1 PRSC0
Write:
$0021 (PCTL2)
See page 177. Reset
0 0 0 0 0 0 0 0
:
Read: FMODE FMODE

Fault Control Register FINT4 FINT1
Write: 4 1
$0022 (FCR)
See page 180. Reset
0 0 0 0 0 0 0 0
:
FFLAG FFLAG
4 1
Fault Status Register
$0023 (FSR) Write:
See page 181.
Reset
U 0 U 0 U 0 U 0
:
Read: 0 0 0 0 0 0 0 0
Fault Acknowledge FTACK FTACK
Write:
$0024 Register (FTACK) 4 1
See page 182.
Reset
0 0 0 0 0 0 0 0
:
Read: 0 OUTCT
PWM Output Control OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
Write: L
$0025 (PWMOUT)
See page 159. Reset
0 0 0 0 0 0 0 0
:
Read: 0 0 0 0 Bit 11 Bit 10 Bit 9 Bit 8

Write:
$0026 High (PCNTH)
See page 172. Reset
0 0 0 0 0 0 0 0
:
U = Unaffected X = Indeter- = Reserved = Buff-

R Bold
minate ered
Figure 9-2. Register Summary (Sheet 1 of 4)

Features

Write:
$0027 Low (PCNTL)
See page 172. Reset
0 0 0 0 0 0 0 0
:
Read: 0 0 0 0
PWM Counter Modulo Bit 11 Bit 10 Bit 9 Bit 8
Write:
$0028 Register High (PMODH)
See page 173. Reset
0 0 0 0 X X X X
:
Read:
PWM Counter Modulo Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
$0029 Register Low (PMODL)
See page 173. Reset
X X X X X X X X
:
Read:
Write:
$002A High (PVAL1H)
See page 174. Reset
0 0 0 0 0 0 0 0
:
Read:
Write:
$002B Low (PVAL1L)
See page 174. Reset
0 0 0 0 0 0 0 0
:
Read:
Write:
$002C High (PVAL2H)
See page 174. Reset
0 0 0 0 0 0 0 0
:
Read:
Write:
$002D Low (PVAL2L)
See page 174. Reset
0 0 0 0 0 0 0 0
:

R Bold
minate ered


Read:
Write:
$002E High (PVAL3H)
See page 174. Reset
0 0 0 0 0 0 0 0
:
Read:
Write:
$002F Low (PVAL3L)
See page 174. Reset
0 0 0 0 0 0 0 0
:
Read:
Write:
$0030 High (PVAL4H)
See page 174. Reset
0 0 0 0 0 0 0 0
:
Read:
Write:
$0031 Low (PVAL4L)
See page 174. Reset
0 0 0 0 0 0 0 0
:
Read:
Write:
$0032 High (PMVAL5H)
See page 174. Reset
0 0 0 0 0 0 0 0
:
Read:
Write:
$0033 Low (PVAL5L)
See page 174. Reset
0 0 0 0 0 0 0 0
:
Read:
Write:
$0034 High (PVAL6H)
See page 174. Reset
0 0 0 0 0 0 0 0
:

R Bold
minate ered

Features

Read:
Write:
$0035 Low (PMVAL6L)
See page 174. Reset
0 0 0 0 0 0 0 0
:
Read:
Dead-Time Write-Once Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
$0036 Register (DEADTM)
See page 179. Reset
1 1 1 1 1 1 1 1
:
Read:
PWM Disable Mapping Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write-Once Register Write:
$0037
(DISMAP)
See page 179. Reset 1 1 1 1 1 1 1 1
:

R Bold
minate ered

9.4 Timebase
This subsection provides for a discussion of the timebase.
9.4.1 Resolution
In center-aligned mode, a 12-bit up/down counter is used to create the

PWM period. Therefore, the PWM resolution in center-aligned mode is
two clocks (highest resolution is 250 ns @ fOP = 8 MHz) as shown in
Figure 9-3. The up/down counter uses the value in the timer modulus
register to determine its maximum count. The PWM period will equal:
(timer modulus) x (PWM clock period) x 2
For edge-aligned mode, a 12-bit up-only counter is used to create the

PWM period. Therefore, the PWM resolution in edge-aligned mode is
one clock (highest resolution is 125 ns @ fOP = 8 MHz) as shown in
Figure 9-4. Again, the timer modulus register is used to determine the
maximum count. The PWM period will equal:
(timer modulus) x (PWM clock period)
Center-aligned operation versus edge-aligned operation is determined

by the option EDGE. See 5.4 CONFIG Bits.

Timebase
UP/DOWN COUNTER
MODULUS = 4
PERIOD = 8 x (PWM CLOCK PERIOD)
PWM = 0
PWM = 1
PWM = 2
PWM = 3
PWM = 4
Figure 9-3. Center-Aligned PWM (Positive Polarity)
UP-ONLY COUNTER
MODULUS = 4
PERIOD = 4 x (PWM
CLOCK PERIOD)
PWM = 0
PWM = 1
PWM = 2
PWM = 3
PWM = 4
Figure 9-4. Edge-Aligned PWM (Positive Polarity)

9.4.2 Prescaler
To permit lower PWM frequencies, a prescaler is provided which will

divide the PWM clock frequency by 1, 2, 4, or 8. Table 9-1 shows how
setting the prescaler bits in PWM control register 2 affects the PWM
clock frequency. This prescaler is buffered and will not be used by the
PWM generator until the LDOK bit is set and a new PWM reload-cycle
begins.
Table 9-1. PWM Prescaler

Prescaler Bits
PWM Clock Frequency
PRSC1:PRSC0
00 fOP
01 fOP/2
10 fOP/4
11 fOP/8
9.5 PWM Generators

This subsection describes the pulse-width modulator (PWM) generators.
9.5.1 Load Operation
To help avoid erroneous pulse widths and PWM periods, the modulus,
prescaler, and PWM value registers are buffered. New PWM values,
counter modulus values, and prescalers can be loaded from their buffers
into the PWM module every one, two, four, or eight PWM cycles.
LDFQ1:LDFQ0 in PWM control register 2 are used to control this reload
frequency, as shown in Table 9-2. When a reload cycle arrives,
regardless of whether an actual reload occurs (as determined by the
LDOK bit), the PWM reload flag bit in PWM control register 1 will be set.
If the PWMINT bit in PWM control register 1 is set, a CPU interrupt
request will be generated when PWMF is set. Software can use this
interrupt to calculate new PWM parameters in real time for the PWM
module.

PWM Generators
Table 9-2. PWM Reload Frequency

Reload Frequency Bits
PWM Reload Frequency
LDFQ1:LDFQ0
00 Every PWM cycle
01 Every 2 PWM cycles
For ease of software, the LDFQx bits are buffered. When the LDFQx bits
are changed, the reload frequency will not change until the previous
reload cycle is completed. See Figure 9-5.
NOTE: When reading the LDFQx bits, the value is the buffered value (for
example, not necessarily the value being acted upon).
RELOAD RELOAD RELOAD RELOAD RELOAD RELOAD RELOAD
CHANGE RELOAD CHANGE RELOAD

FREQUENCY TO FREQUENCY TO
EVERY 4 CYCLES EVERY CYCLE
Figure 9-5. Reload Frequency Change
PWMINT enables CPU interrupt requests as shown in Figure 9-6. When

this bit is set, CPU interrupt requests are generated when the PWMF bit
is set. When the PWMINT bit is clear, PWM interrupt requests are
inhibited. PWM reloads will still occur at the reload rate, but no interrupt
requests will be generated.

READ PWMF AS 1,
WRITE PWMF AS 0
OR RESET
VDD
RESET
PWMF
D CPU INTERRUPT
REQUEST
LATCH
PWMINT
PWM RELOAD CK
Figure 9-6. PWM Interrupt Requests
To prevent a partial reload of PWM parameters from occurring while the

software is still calculating them, an interlock bit controlled from software
is provided. This bit informs the PWM module that all the PWM
parameters have been calculated, and it is okay to use them. A new
modulus, prescaler, and/or PWM value cannot be loaded into the PWM
module until the LDOK bit in PWM control register 1 is set. When the
LDOK bit is set, these new values are loaded into a second set of
registers and used by the PWM generator at the beginning of the next
PWM reload cycle as shown in Figure 9-7, Figure 9-8, Figure 9-9, and
Figure 9-10. After these values are loaded, the LDOK bit is cleared.
NOTE: When the PWM module is enabled (via the PWMEN bit), a load will occur
if the LDOK bit is set. Even if it is not set, an interrupt will occur if the
PWMINT bit is set. To prevent this, the software should clear the
PWMINT bit before enabling the PWM module.
LDFQ1:LDFQ0 = 00 (RELOAD EVERY CYCLE)
UP/DOWN
COUNTER
LDOK = 1 LDOK = 0 LDOK = 1 LDOK = 0

MODULUS = 3 MODULUS = 3 MODULUS = 3 MODULUS = 3
PWM VALUE= 1 PWM VALUE= 2 PWM VALUE= 2 PWM VALUE= 1
PWMF SET PWMF SET PWMF SET PWMF SET
PWM
Figure 9-7. Center-Aligned PWM Value Loading

PWM Generators
UP/DOWN
COUNTER
LDOK = 1 LDOK = 1 LDOK = 1 LDOK = 1 LDOK = 0

MODULUS = 2 MODULUS = 3 MODULUS = 2 MODULUS = 1 MODULUS = 2
PWM VALUE = 1 PWM VALUE= 1 PWMVALUE= 1 PWM VALUE= 1 PWM VALUE= 1
PWMF SET PWMF SET PWMF SET PWMF SET PWMF SET
PWM
Figure 9-8. Center-Aligned Loading of Modulus
UP-ONLY
COUNTER
LDOK = 1 LDOK = 0 LDOK = 1 LDOK = 0 LDOK = 0

MODULUS = 3 MODULUS = 3 MODULUS = 3 MODULUS = 3 MODULUS = 3
PWM VALUE= 1. PWM VALUE= 2. PWM VALUE = 2 PWM VALUE = 1 PWM VALUE = 1
PWMF SET PWMF SET PWMF SET PWMF SET PWMF SET
PWM
Figure 9-9. Edge-Aligned PWM Value Loading

UP-ONLY
COUNTER
LDOK = 1 LDOK = 1 LDOK = 1 LDOK = 0

MODULUS = 3 MODULUS = 4 MODULUS = 2 MODULUS = 1
PWM VALUE= 2 PWM VALUE = 2 PWM VALUE = 2 PWM VALUE= 2
PWMF SET PWMF SET PWMF SET PWMF SET
PWM
Figure 9-10. Edge-Aligned Modulus Loading

9.5.2 PWM Data Overflow and Underflow Conditions
The PWM value registers are 16-bit registers. Although the counter is
only 12 bits, the user may write a 16-bit signed value to a PWM value
register. As shown in Figure 9-3 and Figure 9-4, if the PWM value is
less than or equal to 0, the PWM will be inactive for the entire period.
Conversely, if the PWM value is greater than or equal to the timer
modulus, the PWM will be active for the entire period. Refer to Table 9-3.
NOTE: The terms active and inactive refer to the asserted and negated states
of the PWM signals and should not be confused with the high-
impedance state of the PWM pins.
Table 9-3. PWM Data Overflow and Underflow Conditions

PWMVALxH:PWMVALxL Condition PWM Value Used
$0000–$0FFF Normal Per registers contents
$1000–$7FFF Overflow $FFF
$8000–$FFFF Underflow $000
9.6 Output Control

This subsection discusses output control.
9.6.1 Selecting Six Independent PWMs or Three Complementary PWM Pairs
The PWM outputs can be configured as six independent PWM channels

or three complementary channel pairs. The option INDEP determines
which mode is used (see 5.4 CONFIG Bits). If complementary operation
is chosen, the PWM pins are paired as shown in Figure 9-11. Operation
of one pair is then determined by one PWM value register. This type of
operation is meant for use in motor drive circuits such as the one in
Figure 9-12.

Output Control
PWM1
PWM VALUE REGISTER PWMS 1 & 2
PWM2
(POLARITY & DEAD-TIME INSERTION)

OUTPUT CONTROL
PWM3
PWM4
PWM5
PWM6
Figure 9-11. Complementary Pairing
PWM PWM PWM

1 3 5
TO
AC
MOTOR
INPUTS
PWM PWM PWM

2 4 6
Figure 9-12. Typical AC Motor Drive
When complementary operation is used, two additional features are

provided:
• Dead-time insertion
• Separate top/bottom pulse width correction to correct for
distortions caused by the motor drive characteristics.
If independent operation is chosen, each PWM has its own PWM value
register.

9.6.2 Dead-Time Insertion
As shown in Figure 9-12, in complementary mode, each PWM pair can

be used to drive top-side/bottom-side transistors.
NOTE: When controlling DC-to-AC inverters such as this, the top and bottom
PWMs in one pair should never be active at the same time.
In Figure 9-12, if PWM1 and PWM2 were on at the same time, large
currents would flow through the two transistors as they discharge the
bus capacitor. The IGBTs could be weakened or destroyed.
Simply forcing the two PWMs to be inversions of each other is not always
sufficient. Since a time delay is associated with turning off the transistors
in the motor drive, there must be a “dead-time” between the deactivation
of one PWM and the activation of the other.
A dead-time can be specified in the dead-time write-once register. This

8-bit value specifies the number of CPU clock cycles to use for the
dead-time. The dead-time is not affected by changes in the PWM period
caused by the prescaler.
Dead-time insertion is achieved by feeding the top PWM outputs of the

PWM generator into dead-time generators, as shown in Figure 9-13.
When output control is enabled, the odd OUT bits, rather than the
PWM generator outputs, are fed into the dead-time generators. See
9.6.4 Output Port Control Register.

Output Control
OUTPUT CONTROL
(OUTCTL) OUT2
OUT4
OUT6
OUTCTL
OUT5
OUT3
OUT1
MUX
MUX
TOP/BOTTOM
GENERATION
PWMPAIR12 TOP
DEAD TIMER
PWM (TOP)
PWM(TOP) PWM1
(TOP) DEAD-TIME (PWM1)
PREDT(TOP)
PREDT (TOP) POSTDT (TOP)
OUTX BOTTOM
SELECT PWM2
(PWM2)
PWM GEN[1:6]
PWM GENERATOR
POLARITY/OUTPUT DRIVE
SEL1–SEL6 MUX
MUX
GENERATION
TOP/BOTTOM
PWMPAIR34 DEAD TIMER TOP
PWM (TOP) PWM3
6 (TOP) DEAD-TIME (PWM3)
FAULT
OUTX BOTTOM
SELECT PWM4
(PWM4)
MUX
TOP/BOTTOM
GENERATION
PWMPAIR56 TOP
DEAD TIMER
PWM (TOP) PWM5

(TOP) DEAD-TIME (PWM5)
OUTX BOTTOM
PWM6
SELECT (PWM6)
Figure 9-13. Dead-Time Generators
Whenever an input to a dead-time generator transitions, a dead-time is

inserted (for example, both PWMs in the pair are forced to their inactive
state). The BOTTOM PWM signal is generated from the TOP PWM and
the dead-time. In the case of output control enabled, the odd OUTx bits
control the top PWMs, the even OUTx bits control the bottom PWMs with
respect to the odd OUTx bits (see Table 9-4). Figure 9-14 shows the
effects of the dead-time insertion.
Examples of dead-time insertion are shown in Figure 9-14 through

Figure 9-16. Figure 9-15 shows the effects of dead-time insertion at the
duty cycle boundaries (near 0% and 100% duty cycles). Figure 9-16
shows the effects of dead-time insertion on pulse widths smaller than the
dead-time.

UP/DOWN COUNTER
MODULUS = 4
PWM VALUE = 2 PWM VALUE = 2 PWM VALUE = 3
PWM1 W/
NO DEAD-TIME
PWM2 W/
NO DEAD-TIME
PWM1 W/ 2 2 2
2
DEAD-TIME = 2
PWM2 W/ 2 2
DEAD-TIME = 2
Figure 9-14. Effects of Dead-Time Insertion
UP/DOWN COUNTER
MODULUS = 3
PWM VALUE = 1 PWM VALUE = 1 PWM VALUE = 3 PWM VALUE = 3
PWM1 W/
NO DEAD-TIME
PWM2 W/
NO DEAD-TIME
PWM1 W/
2 2
DEAD-TIME = 2
PWM2 W/
DEAD-TIME = 2 2 2
Figure 9-15. Dead-Time at Duty Cycle Boundaries

Output Control
UP/DOWN COUNTER
MODULUS = 3
PWM VALUE = 2 PWM VALUE = 3 PWM VALUE = 2 PWM VALUE= 1
PWM1 W/
NO DEAD-TIME
PWM2 W/
NO DEAD-TIME
PWM1 W/ 3 3 3
DEAD-TIME = 3
PWM2 W/ 3 3
DEAD-TIME = 3 3
Figure 9-16. Dead-Time and Small Pulse Widths
9.6.3 Output Polarity
The output polarity of the PWMs is determined by two options: TOPNEG

and BOTNEG. The top polarity option, TOPNEG, controls the polarity of
PWMs 1, 3, and 5. The bottom polarity option, BOTNEG, controls the
polarity of PWMs 2, 4, and 6. Positive polarity means that when the PWM
is active, the PWM output is high. Conversely, negative polarity means
that when the PWM is active, PWM output is low. See Figure 9-17.
NOTE: Both bits are found in the CONFIG register, which is a write-once
register. This reduces the chances of the software inadvertently
changing the polarity of the PWM signals and possibly damaging the
motor drive hardware.

CENTER-ALIGNED POSITIVE POLARITY EDGE-ALIGNED POSITIVE POLARITY
UP/DOWN COUNTER UP-ONLY COUNTER

MODULUS = 4
MODULUS = 4
PWM = 0
PWM = 0
PWM = 1
PWM = 1
PWM = 2
PWM = 2
PWM = 3
PWM = 3
PWM = 4
PWM = 4
CENTER-ALIGNED NEGATIVE POLARITY EDGE-ALIGNED NEGATIVE POLARITY
UP-ONLY COUNTER
MODULUS = 4
UP/DOWN COUNTER
MODULUS = 4
PWM = 0
PWM = 1
PWM = 0
PWM = 2
PWM = 1
PWM = 3
PWM = 2
PWM = 4
PWM = 3
PWM = 4
Figure 9-17. PWM Polarity

Output Control
9.6.4 Output Port Control Register
Conditions may arise in which the PWM pins need to be individually

controlled. This is made possible by the PWM output control register
(PWMOUT) shown in Figure 9-18.
Ad-
$0025
dress:
BIt 7 6 5 4 3 2 1 Bit 0
Read: 0 OUT-
OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
Write: CTL
Reset: 0 0 0 0 0 0 0 0
= Unimplement-
ed
Figure 9-18. PWM Output Control Register (PWMOUT)
If the OUTCTL bit is set, the PWM pins can be controlled by the OUTx
bits. These bits behave according to Table 9-4.
Table 9-4. OUTx Bits

OUTx Bit Complementary Mode Independent Mode
1 — PWM1 is active. 1 — PWM1 is active
OUT1
0 — PWM1 is inactive. 0 — PWM1 is inactive
1 — PWM2 is complement of PWM1. 1 — PWM2 is active
OUT2
OUT3
OUT4
OUT5
OUT6
When OUTCTL is set, the polarity options TOPPOL and BOTPOL will
still affect the outputs. In addition, if complementary operation is in use,
the PWM pairs will not be allowed to be active simultaneously, and
dead-time will still not be violated. When OUTCTL is set and

complimentary operation is in use, the odd OUTx bits are inputs to the
dead-time generators as shown in Figure 9-14. Dead-time is inserted
whenever the odd OUTx bit toggles as shown in Figure 9-19. Although
dead-time is not inserted when the even OUTx bits change, there will be
no dead-time violation as shown in Figure 9-20.
Setting the OUTCTL bit does not disable the PWM generator and current
sensing circuitry. They continue to run, but are no longer controlling the
output pins. In addition, OUTCTL will control the PWM pins even when
PWMEN = 0. When OUTCTL is cleared, the outputs of the PWM
generator become the inputs to the dead-time and output circuitry at the
beginning of the next PWM cycle.
NOTE: To avoid an unexpected dead-time occurrence, it is recommended that

the OUTx bits be cleared prior to entering and prior to exiting individual
PWM output control mode.
UP/DOWN COUNTER
MODULUS=4
DEAD-TIME = 2
PWM VALUE = 3
OUTCTL
OUT1
OUT2
PWM1
PWM2
PWM1/PWM2 2 2 2
DEAD-TIME
DEAD-TIME INSERTED AS PART OF DEAD-TIME INSERTED DUE DEAD-TIME INSERTED

NORMAL PWM OPERATION AS TO SETTING OF OUT1 BIT DUE TO CLEARING OF
CONTROLLED BY CURRENT OUT1 BIT
SENSING AND PWM GENERATOR
Figure 9-19. Dead-Time Insertion During OUTCTL = 1

Fault Protection
UP/DOWN COUNTER
MODULUS = 4
DEAD-TIME = 2
PWM VALUE = 3
OUTCTL
OUT1
OUT2
PWM1
PWM2
2 2 2 2
PWM1/PWM2
DEAD-TIME
DEAD-TIME INSERTED BECAUSE DEAD-TIMES INSERTED NO DEAD-TIME INSERTED
WHEN OUTCTL WAS SET, THE BECAUSE OUT1 TOGGLES, BECAUSE OUT1 IS NOT
STATE OF OUT1 WAS SUCH THAT DIRECTING PWM1 TO TOGGLING.
PWM1 WAS DIRECTED TO TOGGLE TOGGLE.
Figure 9-20. Dead-Time Insertion During OUTCTL = 1
9.7 Fault Protection

Conditions may arise in the external drive circuitry which require that the
PWM signals become inactive immediately, such as an overcurrent fault
condition. Furthermore, it may be desirable to selectively disable
PWM(s) solely with software.
One or more PWM pins can be disabled (forced to their inactive state)
by applying a logic high to either of the two external fault pins or by
writing a logic high to either of the disable bits (DISX and DISY in PWM
control register 1). Figure 9-21 shows the structure of the PWM
disabling scheme. While the PWM pins are disabled, they are forced to
their inactive state. The PWM generator continues to run — only the
output pins are disabled

DISY
CYCLE START SOFTWARE X DISABLE
S Q
BANK Y
FMODE4 FAULT PIN 4 DISABLE DISABLE
AUTO
FPIN4 MODE
LOGIC HIGH FOR FAULT S Q
TWO ONE
SAMPLE R
SHOT S Q FFLAG4
FAULT FILTER
PIN4 MANUAL
R MODE
CLEAR BY WRITING 1 TO FTACK4
INTERRUPT REQUEST
FINT4
The example is of fault pin 4 with DISY.
Note: In manual mode (FMODE = 0), fault 4 may be cleared only if a logic level low
at the input of the fault pin is present.
CYCLE START
FMODE1 FAULT PIN 1 DISABLE

FPIN1 AUTO
MODE
LOGIC HIGH FOR FAULT S Q BANK X DISABLE
FAULT TWO ONE

SAMPLE R
SHOT S Q FFLAG1
PIN1 FILTER
MANUAL
R MODE
CLEAR BY WRITING 1 TO FTACK1
INTERRUPT REQUEST
FINT1
The example is of fault pin 1.
Note: In manual mode (FMODE = 0), fault 1 may be cleared regardless of the logic level
at the input of the fault pin.
Figure 9-21. PWM Disabling Scheme
To allow for different motor configurations and the controlling of more

than one motor, the PWM disabling function is organized as two banks,
bank X and bank Y. Bank information combines with information from
the disable mapping register to allow selective PWM disabling. Fault

Fault Protection
pin 1 and PWM disable bit X constitute the disabling function of bank X.
Fault pin 4 and PWM disable bit Y constitute the disabling function of
bank Y. Figure 9-22 and Figure 9-23 show the disable mapping
write-once register and the decoding scheme of the bank which
selectively disables PWM(s). When all bits of the disable mapping
register are set, any disable condition will disable all PWMs.
A fault can also generate a CPU interrupt. Each fault pin has its own
interrupt vector.
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dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 1 1 1 1 1 1 1 1
Figure 9-22. PWM Disable Mapping Write-Once Register (DISMAP)

BIT 7
DISABLE
PWM PIN 1
BIT 6
DISABLE
BIT 5 PWM PIN 2
DISABLE
BIT 4 PWM PIN 3
BANK X
DISABLE
BIT 3
BANK Y
DISABLE DISABLE
PWM PIN 4
BIT 2
DISABLE
BIT 1 PWM PIN 5
BIT 0
DISABLE
PWM PIN 6
Figure 9-23. PWM Disabling Decode Scheme
9.7.1 Fault Condition Input Pins
A logic high level on a fault pin disables the respective PWM(s)

determined by the bank and the disable mapping register. Each fault pin
incorporates a filter to assist in rejecting spurious faults. All of the
external fault pins are software-configurable to re-enable the PWMs
either with the fault pin (automatic mode) or with software (manual
mode). Each fault pin has an associated FMODE bit to control the PWM
re-enabling method. Automatic mode is selected by setting the FMODEx
bit in the fault control register. Manual mode is selected when FMODEx
is clear.
NOTE: PORTC, when used as an input port, mirrors the state of the fault input
pins, as PORTC has the capability of being used as an output port.
When either pin of PORTC is set as an output, by setting its respective
PORTC data direction register bit, the respective fault pin logic is
disconnected from that pin and the fault input will be defaulted to normal

Fault Protection
non-fault condition to facilitate the use of PORTC as an output pin and

not interfere with the PWM generator. To regain the fault capability for
the respective fault input pin, clear the PORTC data direction register bit
for that pin.
Additionally, when the device is reset, by default, PORTC is configured

as an input. If either bit(s) of PORTC is intended to be used as an output,
the logic state of the driven device’s input is indeterminate. The state of
the driven device, if at a logic one will drive the respective bit of PORTC
input high, thus causing a fault to be input to the respective PORTC input
and to the PWM module.
After setting the PORTC data direction register, clear the respective fault
bits by writing a 1 to bit(s) 0 and or bit 6 in the FTACK Fault Acknowledge
Register (FTACK) and Fault Status Registers (FSR), based on which
PORTC bits that are used as output(s).
9.7.1.1 Fault Pin Filter
The two fault pins incorporate a filter to assist in determining a genuine

fault condition. After a fault pin has been logic low for one CPU cycle, a
rising edge (logic high) will be synchronously sampled once per CPU
cycle for two cycles. If both samples are detected logic high, the
corresponding FPIN bit and FFLAG bit will be set. The FPIN bit will
remain set until the corresponding fault pin is logic low and
synchronously sampled once in the following CPU cycle.
9.7.1.2 Automatic Mode
In automatic mode, the PWM(s) are disabled immediately once a filtered

fault condition is detected (logic high). The PWM(s) remain disabled until
the filtered fault condition is cleared (logic low) and a new PWM cycle
begins as shown in Figure 9-24. Clearing the corresponding FFLAGx
event bit will not enable the PWMs in automatic mode.

FILTERED FAULT PIN
PWM(s) ENABLED PWM(S) DISABLED (INACTIVE) PWM(S) ENABLED
Figure 9-24. PWM Disabling in Automatic Mode
The filtered fault pin’s logic state is reflected in the respective FPINx bit.
Any write to this bit is overwritten by the pin state. The FFLAGx event bit
is set with each rising edge of the respective fault pin after filtering has
been applied. To clear the FFLAGx bit, the user must write a 1 to the
corresponding FTACKx bit.
If the FINTx bit is set, a fault condition resulting in setting the

corresponding FFLAG bit will also latch a CPU interrupt request. The
interrupt request latch is not cleared until one of these actions occurs:
• The FFLAGx bit is cleared by writing a 1 to the corresponding
FTACKx bit.
• The FINTx bit is cleared. (This will not clear the FFLAGx bit.)
• Reset — A reset automatically clears all four interrupt latches.
If prior to a vector fetch the interrupt request latch is cleared by one of

the above actions, a CPU interrupt will no longer be requested. A vector
fetch does not alter the state of the PWMs, the FFLAGx event flag, or
FINTx.
NOTE: If the FFLAGx or FINTx bits are not cleared during the interrupt service
routine, the interrupt request latch will not be cleared.

Fault Protection
9.7.1.3 Manual Mode
In manual mode, the PWM(s) are disabled immediately once a filtered

fault condition is detected (logic high). The PWM(s) remain disabled until
software clears the corresponding FFLAGx event bit and a new PWM
cycle begins. In manual mode, the fault pins are grouped in pairs, each
pair sharing common functionality. A fault condition on fault 1 may be
cleared, allowing the PWM(s) to enable at the start of a PWM cycle
regardless of the logic level at the fault pin. See Figure 9-25. A fault
condition on fault 4 can be cleared, allowing the PWM(s) to enable, only
if a logic low level at the fault pin is present at the start of a PWM cycle.
See Figure 9-26.
FILTERED FAULT PIN 1
PWM(S) ENABLED PWM(S) DISABLED PWM(S) ENABLED
FFLAGx CLEARED
Figure 9-25. PWM Disabling in Manual Mode (Example 1)
FILTERED FAULT PIN 4
FFLAGx CLEARED
Figure 9-26. PWM Disabling in Manual Mode (Example 2)

The function of the fault control and event bits is the same as in
automatic mode except that the PWMs are not re-enabled until the
FFLAGx event bit is cleared by writing to the FTACKx bit and the filtered
fault condition is cleared (logic low).
9.7.2 Software Output Disable
Setting PWM disable bit DISX or DISY in PWM control register 1

immediately disables the corresponding PWM pins as determined by the
bank and disable mapping register. The PWM pin(s) remain disabled
until the PWM disable bit is cleared and a new PWM cycle begins as
shown in Figure 9-27. Setting a PWM disable bit does not latch a CPU
interrupt request, and there are no event flags associated with the PWM
disable bits.
9.7.3 Output Port Control
When operating the PWMs using the OUTx bits (OUTCTL = 1), fault
protection applies as described in this section. Due to the absence of
periodic PWM cycles, fault conditions are cleared upon each CPU cycle
and the PWM outputs are re-enabled, provided all fault clearing
conditions are satisfied.
DISABLE BIT
Figure 9-27. PWM Software Disable

Initialization and the PWMEN Bit
9.8 Initialization and the PWMEN Bit

For proper operation, all registers should be initialized and the LDOK bit
should be set before enabling the PWM via the PWMEN bit. When the
PWMEN bit is first set, a reload will occur immediately, setting the PWMF
flag and generating an interrupt if PWMINT is set. In addition, in
complementary mode, PWM value registers 1, 3, and 5 will be used for
the first PWM cycle if current sensing is selected.
NOTE: If the LDOK bit is not set when PWMEN is set after a RESET, the
prescaler and PWM values will be 0, but the modulus will be unknown.
If the LDOK bit is not set after the PWMEN bit has been cleared then set
(without a RESET), the modulus value that was last loaded will be used.
If the dead-time register (DEADTM) is changed after PWMEN or

OUTCTL is set, an improper dead-time insertion could occur. However,
the dead-time can never be shorter than the specified value.
Because of the equals-comparator architecture of this PWM, the

modulus = 0 case is considered illegal. Therefore, the modulus register
is not reset, and a modulus value of 0 will result in waveforms
inconsistent with the other modulus waveforms. See 9.12.2 PWM
Counter Modulo Registers.
When PWMEN is set, the PWM pins change from high impedance to
outputs. At this time, assuming no fault condition is present, the PWM
pins will drive according to the PWM values, polarity, and dead-time.
See the timing diagram in Figure 9-28.
CPU CLOCK
PWMEN
DRIVE ACCORDING TO PWM

VALUE, POLARITY, AND DEAD-TIME
PWM PINS HI-Z IF OUTCTL = 0 HI-Z IF OUTCTL = 0
Figure 9-28. PWMEN and PWM Pins

When the PWMEN bit is cleared, the following will occur:

• PWM pins will be three-stated unless OUTCTL = 1.
• PWM counter is cleared and will not be clocked.
• Internally, the PWM generator will force its outputs to 0 to avoid
glitches when the PWMEN is set again.
When PWMEN is cleared, these features remain active:
• All fault circuitry
• Manual PWM pin control via the PWMOUT register
• Dead-time insertion when PWM pins change via the PWMOUT
register
NOTE: The PWMF flag and pending CPU interrupts are NOT cleared when
PWMEN = 0.
9.9 PWM Operation in Wait Mode

When the microcontroller is put in low-power wait mode via the WAIT
instruction, all clocks to the PWM module will continue to run. If an
interrupt is issued from the PWM module (via a reload or a fault), the
microcontroller will exit wait mode.
Clearing the PWMEN bit before entering wait mode will reduce power
consumption in wait mode because the counter, prescaler divider, and
LDFQ divider will no longer be clocked. In addition, power will be
reduced because the PWMs will no longer toggle.
9.10 PWM Operation in Stop Mode

When the microcontroller is put in low-power wait mode via the STOP
instruction, all clocks to the PWM module will stop.
NOTE: It is imperative that the program to clear the PWMEN bit before entering
stop mode. Leaving the PWM module enabled during stop mode can
destroy power stages connected to the PWM outputs. The PWM
generator will no longer be clocked during stop mode and the PWM
outputs will no longer toggle.

PWM Operation in Break Mode
9.11 PWM Operation in Break Mode

If the microcontroller goes into break mode (or background mode), the
clocks to the PWM generator and output control blocks will freeze. This
allows the user to set a breakpoint on a development system and
examine the register contents and PWM outputs at that point. It also
allows the user to single-step through the code.
The clocks to the fault block will continue to run. Therefore, if a fault
occurs while the microcontroller is in break mode, the PWM outputs will
immediately be driven to their inactive state(s).
During break mode, the system integration module (SIM) controls

whether status bits in other modules can be cleared during the break
state. The BCFE bit in the SIM break flag control register (SBFCR)
enables software to clear status bits during the break state. Refer to
7.7.5 SIM Break Flag Control Register.

To protect the PWMF and FFLAGx bits during the break state, make
sure BCFE is a logic 0. With BCFE at logic 0 (its default state), software
can read and write the status and control registers during the break state
without affecting the PWMF and FFLAGx bits.

9.12 Control Logic Block

This subsection provides a description of the control logic block.
9.12.1 PWM Counter Registers
The PWM counter registers (PCNTH and PCNTL) display the12-bit

up/down or up-only counter. When the high byte of the counter is read,
the lower byte is latched. PCNTL will hold this latched value until it is
read.
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dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 Bit11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 9-29. PWM Counter Register High (PCNTH)
Ad-
$0027
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 9-30. PWM Counter Register Low (PCNTH)

Control Logic Block
9.12.2 PWM Counter Modulo Registers
The PWM counter modulus registers (PDMODH and PDMODL) hold a

12-bit unsigned number that determines the maximum count for the
up/down or up-only counter. In center-aligned mode, the PWM period
will be twice the modulus (assuming no prescaler). In edge-aligned
mode, the PWM period will equal the modulus.
Ad-
$0028
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0
Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0 0 0 0 X X X X
= Unimplemented X = Indeterminate
Figure 9-31. PWM Counter Modulo Register High (PDMODH)

Ad-
$0029
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: X X X X X X X X
= Unimplemented X = Indeterminate
Figure 9-32. PWM Counter Modulo Register Low (PDMODL)
To avoid erroneous PWM periods, this value is buffered and will not be
used by the PWM generator until the LDOK bit has been set and the next
PWM load cycle begins.
NOTE: When reading this register, the value read is the buffer (not necessarily
the value the PWM generator is currently using).
Because of the equals-comparator architecture of this PWM, the

modulus = 0 case is considered illegal. Therefore, the modulus register
is not reset, and a modulus value of 0 will result in waveforms
inconsistent with the other modulus waveforms. If a modulus of 0 is
loaded, the counter will continually count down from $FFF. This
operation will not be tested or guaranteed. (The user should consider it

illegal.) However, the dead-time constraints and fault conditions will still
be guaranteed.
9.12.3 PWMx Value Registers
Each of the six PWMs has a 16-bit PWM value register.
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 9-33. PWMx Value Registers High (PVALxH)
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 9-34. PWMx Value Registers Low (PVALxL)
The 16-bit signed value stored in this register determines the duty cycle
of the PWM. The duty cycle is defined as: (PWM value/modulus) x 100.
Writing a number less than or equal to 0 causes the PWM to be off for
the entire PWM period. Writing a number greater than or equal to the
12-bit modulus causes the PWM to be on for the entire PWM period.
If the complementary mode is selected, the PWM pairs share PWM

value registers.
To avoid erroneous PWM pulses, this value is buffered and will not be
used by the PWM generator until the LDOK bit has been set and the next
PWM load cycle begins.
NOTE: When reading these registers, the value read is the buffer (not
necessarily the value the PWM generator is currently using).

Control Logic Block
9.12.4 PWM Control Register 1
PWM control register 1 controls PWM enabling/disabling, the loading of

new modulus, prescaler, and PWM values, and the PWM correction
method. In addition, this register contains the software disable bits to
force the PWM outputs to their inactive states (according to the disable
mapping register).
Ad-
$0020
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: PW-
DISX DISY PWMINT PWMF LDOK
Write: MEN
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 9-35. PWM Control Register 1 (PCTL1)
DISX — Software Disable for Bank X Bit

This read/write bit allows the user to disable one or more PWM pins
in bank X. The pins that are disabled are determined by the disable
mapping write-once register.
1 = Disable PWM pins in bank X
0 = Re-enable PWM pins at beginning of next PWM cycle
DISY — Software Disable for Bank Y Bit
This read/write bit allows the user to disable one or more PWM pins
in bank Y. The pins that are disabled are determined by the disable
mapping write-once register.
1 = Disable PWM pins in Bank Y Bit
0 = Re-enable PWM pins at beginning of next PWM cycle
PWMINT — PWM Interrupt Enable Bit
This read/write bit allows the user to enable and disable PWM CPU
interrupts. If set, a CPU interrupt will be pending when the PWMF flag
is set.
1 = Enable PWM CPU interrupts
0 = Disable PWM CPU interrupts

NOTE: When PWMINT is cleared, pending CPU interrupts are inhibited.
PWMF— PWM Reload Flag

This read/write bit is set at the beginning of every reload cycle
regardless of the state of the LDOK bit. This bit is cleared by reading
PWM control register 1 with the PWMF flag set, then writing a logic 0
to PWMF. If another reload occurs before the clearing sequence is
complete, then writing logic 0 to PWMF has no effect.
1 = New reload cycle began.
0 = New reload cycle has not begun.
NOTE: When PWMF is cleared, pending PWM CPU interrupts are cleared
(excluding fault interrupts).
CAUTION: Bits 2 and/or 3 of PCTL1 are reserved and must never be set to a 1.
Setting these bits to a 1 will affect the active PWM value registers.
Undesirable results will occur.
LDOK— Load OK Bit

This read/write bit allows the counter modulus, counter prescaler, and
PWM values in the buffered registers to be used by the PWM
generator. These values will not be used until the LDOK bit is set and
a new PWM load cycle begins. LDOK may be cleared, if it is set, by
writing a logic 0 to it prior to the beginning of a new PWM load cycle.
Internally this bit is automatically cleared after the new values are
loaded.
1 = Okay to load new modulus, prescaler, and PWM values at
beginning of next PWM load cycle
0 = Not okay to load new modulus, prescaler, and PWM values
NOTE: The user should initialize the PWM registers and set the LDOK bit before
enabling the PWM.
PWMEN — PWM Module Enable Bit

This read/write bit enables and disables the PWM generator and the
PWM pins. When PWMEN is clear, the PWM generator is disabled
and the PWM pins are in the high-impedance state (unless
OUTCTL = 1). When the PWMEN bit is set, the PWM generator and
PWM pins are activated. For more information, see 9.8 Initialization
and the PWMEN Bit.
1 = PWM generator and PWM pins enabled
0 = PWM generator and PWM pins disabled

Control Logic Block
NOTE: A PWM CPU interrupt request can still be generated when LDOK is 0.
9.12.5 PWM Control Register 2
PWM control register 2 controls the PWM load frequency, the PWM
correction method, and the PWM counter prescaler. For ease of
software and to avoid erroneous PWM periods, some of these register
bits are buffered. The PWM generator will not use the prescaler value
until the LDOK bit has been set, and a new PWM cycle is starting. The
correction bits are used at the beginning of each PWM cycle (if the
ISENSx bits are configured for software correction). The load frequency
bits are not used until the current load cycle is complete.
NOTE: The user should initialize this register before enabling the PWM.
Ad-
$0021
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0
LDFQ1 LDFQ0 SEL12 SEL34 SEL56 PRSC1 PRSC0
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplement- = Buffered
Bold
ed
Figure 9-36. PWM Control Register 2 (PCTL2)
LDFQ1 and LDFQ0 — PWM Load Frequency Bits

These buffered read/write bits select the PWM CPU load frequency
according to Table 9-5.
NOTE: When reading these bits, the value read is the buffer value (not
Table 9-5. PWM Reload Frequency
Reload Frequency Bits
PWM Reload Frequency
LDFQ1:LDFQ0
00 Every PWM cycle

SEL12 — Top/Bottom Correction Bit for PWM Pair 1 (PWMs 1 and 2)

This buffered read/write bit selects which PWM value register is used
for PWM pins 1 and 2 in complementary mode.
1 = Use PWM value register 2.
NOTE: When reading this bit, the value read is the buffer value (not necessarily
the value the output control block is currently using).


PRSC1:PRSC0 — PWM Prescaler Bits

These buffered read/write bits allow the PWM clock frequency to be
modified as shown in Table 9-6.
NOTE: When reading these bits, the value read is the buffer value (not
Table 9-6. PWM Prescaler

Prescaler Bits
PWM Clock Frequency
PRSC1:PRSC0
00 fOP
01 fOP/2
10 fOP/4
11 fOP/8

Control Logic Block
NOTE: If PRSC1 and PRSC2 are set to any value other than 0, there is a one
PWM cycle latency time before the PWM pins are driven after the
PWMEN bit is set.
9.12.6 Dead-Time Write-Once Register
The dead-time write-once register (DEADTM) holds an 8-bit value which

specifies the number of CPU clock cycles to use for the dead-time when
complementary PWM mode is selected. After this register is written for
the first time, it cannot be rewritten unless a RESET occurs. The
dead-time is not affected by changes to the prescaler value.
Ad-
$0036
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: 1 1 1 1 1 1 1 1
Figure 9-37. Dead-Time Write-Once Register (DEADTM)
9.12.7 PWM Disable Mapping Write-Once Register
The PWM disable mapping write-once register (DISMAP) holds an 8-bit

value which determines which PWM pins will be disabled if an external
fault or software disable occur. For a further description of the disable
mapping, see 9.7 Fault Protection. After this register is written for the
first time, it cannot be rewritten unless a reset occurs.
Ad-
$0037
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: 1 1 1 1 1 1 1 1
Figure 9-38. PWM Disable Mapping Write-Once Register (DISMAP)

9.12.8 Fault Control Register
This register controls the fault protection circuitry.
Ad-
$0022
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: FMODE FMODE

FINT4 FINT1
Write: 4 1
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 9-39. Fault Control Register (FCR)
FMODE1 — Fault Mode Selection for Fault Pin 1 Bit (Automatic versus
Manual Mode)
This read/write bit allows the user to select between automatic and
manual mode faults. For further description of each mode, see
9.7 Fault Protection.
1 = Automatic mode
0 = Manual mode
FINT1 — Fault 1 Interrupt Enable Bit
This read/write bit allows the CPU interrupt caused by faults on fault
pin 1 to be enabled. The fault protection circuitry is independent of this
bit and will always be active. If a fault is detected, the PWM pins will
still be disabled according to the disable mapping register.
1 = Fault pin 1 will cause CPU interrupts.
0 = Fault pin 1 will not cause CPU interrupts.
FMODE4 — Fault Mode Selection for Fault Pin 4 Bit (Automatic versus
Manual Mode)
This read/write bit allows the user to select between automatic and
manual mode faults. For further description of each mode, see
9.7 Fault Protection.
1 = Automatic mode
0 = Manual mode

Control Logic Block
FINT4 — Fault 4 Interrupt Enable Bit

This read/write bit allows the CPU interrupt caused by faults on fault
pin 4 to be enabled. The fault protection circuitry is independent of this
bit and will always be active. If a fault is detected, the PWM pins will
still be disabled according to the disable mapping register.
1 = Fault pin 4 will cause CPU interrupts.
0 = Fault pin 4 will not cause CPU interrupts.
9.12.9 Fault Status Register
This read-only register indicates the current fault status.

Ad-
$0023
dress:
Bit 7 6 5 4 3 2 1 Bit 0
FFLAG FFLAG
4 1
Write:
Reset: U 0 U 0 U 0 U 0
= Unimplement- U = Unaffected
ed
Figure 9-40. Fault Status Register (FSR)
FFLAG1 — Fault Event Flag 1

The FFLAG1 event bit is set within two CPU cycles after a rising edge
on fault pin 1. To clear the FFLAG1 bit, the user must write a 1 to the
FTACK1 bit in the fault acknowledge register.
1 = A fault has occurred on fault pin 1
0 = No new fault on fault pin 1
FPIN1 — State of Fault Pin 1
This read-only bit allows the user to read the current state of fault
pin 1.
1 = Fault pin 1 is at logic 1
0 = Fault pin 1 is at logic 0

FFLAG4 — Fault Event Flag 4

The FFLAG4 event bit is set within two CPU cycles after a rising edge
on fault pin 4. To clear the FFLAG4 bit, the user must write a 1 to the
FTACK4 bit in the fault acknowledge register.
1 = A fault has occurred on fault pin 4
0 = No new fault on fault pin 4
FPIN4 — State of Fault Pin 4 Bit
This read-only bit allows the user to read the current state of fault
pin 4.
1 = Fault pin 4 is at logic 1.
0 = Fault pin 4 is at logic 0.
9.12.10 Fault Acknowledge Register
The fault acknowledge register (FTACK) is used to acknowledge and

clear the FFLAGs. In addition, it is used to monitor the current sensing
bits to test proper operation.
Ad-
$0024
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0 0 0 0
FTACK FTACK
Write:
4 1
Reset: 0 0 0 0 0 0 0 0
= Unimplement-
ed
Figure 9-41. Fault Acknowledge Register (FTACK)

Control Logic Block
FTACK1 — Fault Acknowledge 1 Bit

The FTACK1 bit is used to acknowledge and clear FFLAG1. This bit
will always read 0. Writing a 1 to this bit will clear FFLAG1. Writing a 0
will have no effect.
FTACK4 — Fault Acknowledge 4 Bit
The FTACK4 bit is used to acknowledge and clear FFLAG4. This bit
will always read 0. Writing a 1 to this bit will clear FFLAG4. Writing a 0
will have no effect.

9.12.11 PWM Output Control Register
This register is used to manually control the PWM pins.
Ad-
$0025
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 OUT-
OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
Write: CTL
Reset: 0 0 0 0 0 0 0 0
= Unimplement- U = Unaffected
ed
Figure 9-42. PWM Output Control Register (PWMOUT)
OUTCTL— Output control enable

This read/write bit allows the user to manually control the PWM pins.
When set, the PWM generator is no longer the input to the dead-time
and output circuitry. The OUTx bits determine the state of the PWM
pins. Setting the OUTCTL bit does not disable the PWM generator.
The generator continues to run, but is no longer the input to the PWM
dead-time and output circuitry. When OUTCTL is cleared, the outputs
of the PWM generator immediately become the inputs to the
dead-time and output circuitry.
1 = PWM outputs controlled manually
0 = PWM outputs determined by PWM generator

PWM Glossary
OUT6:OUT1— PWM Pin Output Control Bits

These read/write bits control the PWM pins according to Table 9-7.
Table 9-7. OUTx Bits

OUTx Bit Complementary Mode Independent Mode
1 — PWM1 is active 1 — PWM1 is active
OUT1
0 — PWM1 is inactive 0 — PWM1 is inactive
1 — PWM2 is complement of PWM 1 1 — PWM2 is active
OUT2
OUT3
1 — PWM4 is complement of PWM 3 1 — PWM4 is active
OUT4
OUT5
1 — PWM 6 is complement of PWM 5 1 — PWM6 is active
OUT6
9.13 PWM Glossary

CPU Cycle — One internal bus cycle (1/fOP)
PWM Clock Cycle (or Period) — One tick of the PWM counter (1/fOP
with no prescaler). See Figure 9-43.
PWM Cycle (or Period)

• Center-aligned mode: The time it takes the PWM counter to count
up and count down (modulus * 2/fOP assuming no prescaler). See
Figure 9-43.
• Edge-aligned mode: The time it takes the PWM counter to count
up (modulus/fOP). See Figure 9-43.

CENTER-ALIGNED MODE
PWM CLOCK CYCLE

PWM CYCLE (OR PERIOD)
EDGE-ALIGNED MODE
PWM
CLOCK
CYCLE PWM CYCLE (OR PERIOD)
Figure 9-43. PWM Clock Cycle and PWM Cycle Definitions
PWM Load Frequency — The frequency at which new PWM

parameters get loaded into the PWM. See Figure 9-44.
LDFQ1:LDFQ0 = 01 — RELOAD EVERY TWO CYCLES
PWM LOAD CYCLE

(1/PWM LOAD FREQUENCY)
RELOAD NEW RELOAD NEW
MODULUS, MODULUS,
PRESCALER, PRESCALER,
AND PWM VALUES AND PWM VALUES
IF LDOK = 1 IF LDOK = 1
Figure 9-44. PWM Load Cycle/Frequency Definition

Section 10. Monitor ROM (MON)
10.1 Contents
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
10.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . .188
10.4.2 Forced Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .190
10.4.3 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
10.4.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
10.4.5 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
10.4.6 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
10.4.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
10.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
10.2 Introduction
This section describes the monitor read-only memory (ROM). The
monitor ROM (MON) allows complete testing of the microcontroller unit
(MCU) through a 2-wire interface with a host computer.
10.3 Features
Features of the monitor ROM include:
• Normal user-mode pin functionality
• Standard mark/space non-return-to-zero (NRZ) communication
with host computer
• 9600 baud communication with host computer
• Execution of code in random-access memory (RAM) or ROM
Freescale Semiconductor Monitor ROM (MON) 187

Monitor ROM (MON)

The monitor ROM receives and executes commands from a host
computer. Figure 10-1 shows a sample circuit used to enter monitor
mode and communicate with a host computer via a standard RS-232
interface.
Simple monitor commands can access any memory address. In monitor

mode, the MCU can execute host-computer code in RAM while all MCU
pins retain normal operating mode functions. All communication
between the host computer and the MCU is through the serial
communications interface (SCI). A level-shifting RS-232 interface is
required between the SCI and the host computer. PTB1 requires a
pulldown resistor to ensure proper entry into monitor mode.
10.4.1 Entering Monitor Mode
Table 10-1 shows the pin conditions for entering monitor mode.
Table 10-1. Mode Selection

IRQ $FFFE/ External Baud
RESET PLL PTB0 PTB1 CGMOUT fop COP Comment
Pin $FFFF Clock Rate
No operation
X VSS X X X X X 0 0 Disabled 0
until reset = VDD
VDD PLL configured with

VHI or X ON VDD VSS 4.0 MHz 16.0 MHz 8.0 MHz Disabled 9600 BCS set by monitor
VHI code
PLL configured with

Blank
VDD VDD ON X X 4.0 MHz 16.0 MHz 8.0 MHz Disabled 9600 BCS set by monitor
(FF)
code
Enters monitor
mode with any
Blank f
VSS VDD OFF X X fOSC fOSC/2 fOSC/4 Disabled OSC external clock rate
(FF) /1024
within operating
spec
VDD VDD Non-blank X X X X X X Enabled X Enters user mode
X = Don’t care
PTB0 = VDD and PTB1 = VSS to enter monitor mode
PTB0 (RXD) and PTB1 (TXD) used for serial communications (all monitor mode)
188 Monitor ROM (MON) Freescale Semiconductor

Monitor ROM (MON)
VDD
10 kΩ MC68HC908MR8
RST
0.1 µF
VHI
10 kΩ
VDDA IRQ
VDDA
0.1 µF
VSSA
VREFH
VREFH
0.1 µF
1 20 CGMXFC
MC145407
+ +
10 µF 10 µF 0.02 µF
3 18
4 17 OSC1
VDD 20 pF X1 10 MΩ
10 µF 10 µF 4.00 MHz
+ +
2 19 OSC2
20 pF
DB-25
2 5 16
VSS
3 6 15
VDD
7 VDD
0.1 µF
PTB0/RXD
PTB1/TXD
10 kΩ
Figure 10-1. Monitor Mode Circuit

Monitor ROM (MON)
Enter monitor mode by applying a logic 0 and then a logic 1 to the RST
pin (see Table 10-1)
Once out of reset, the MCU waits for the host to send eight security
bytes. After receiving the security bytes, the MCU sends a break signal
(10 consecutive logic 0s) to the host computer, indicating that it is ready
to receive a command.
Monitor mode uses alternate vectors for reset and SWI. The alternate
vectors are in the $FE page instead of the $FF page and allow code
execution from the internal monitor firmware instead of user code. The
computer operating properly (COP) module is disabled in monitor mode
as long as VHI is applied to either the IRQ pin or the RST pin. Refer to
Section 7. System Integration Module (SIM) for more information on
modes of operation.
10.4.2 Forced Monitor Mode
On FLASH parts, if the voltage applied to the IRQ1 is less than VHI, the
MCU will come out of reset in user mode. The memory reset module
monitors the reset vector fetches and will assert an internal reset if it
detects that the reset vectors are erased. When the MCU comes out of
reset with its reset vector erased, it is forced into monitor mode without
requiring high voltage on the IRQ1 pin.
The computer operating properly (COP) module is disabled in forced

monitor mode. Any reset other than a power-on reset (POR) will
automatically force the MCU to come back to the forced monitor mode.
Table 10-2 is a summary of the differences between user mode and

monitor mode.
Table 10-2. Mode Differences
Functions
Modes Reset Reset SWI SWI

COP
Vector High Vector Low Vector High Vector Low
User Enabled $FFFE $FFFF $FFFC $FFFD
Monitor Disabled(1) $FEFE $FEFF $FEFC $FEFD
1. If the high voltage (VHI) is removed from the IRQ pin or the RST pin, the SIM
asserts its COP enable output.

Monitor ROM (MON)
10.4.3 Baud Rate
With a 4.0-MHz reference clock source, data is transferred between the

monitor and host at 9600 baud. The communication baud rate is
achieved by stepping up the internal CPU frequency to 8 MHz, using the
phase-locked loop (PLL). A 4.0-MHz reference frequency is necessary
in this mode as the PLL will not lock with any other reference clock.
As described in Table 10-1, on FLASH parts when VSS is applied to IRQ

with $FFFE and $FFFF = 0, the PLL setup is bypassed and the baud rate
is equal to the reference frequency divided by 1024. This facilitates a
faster communication rate in the interest of a first time programmed
device. This allows selection of other reference frequencies and thus,
facilities a faster communication rate. The reference frequency, in this
case while not utilizing the PLL, is limited to the range of fOP. Refer to
21.8 Control Timing.
10.4.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero

(NRZ) mark/space data format. See Figure 10-2 and Figure 10-3.
NEXT
START START
BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT
BIT
Figure 10-2. Monitor Data Format
NEXT
START START
$A5 BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT
BIT
START STOP
BREAK BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT NEXT
START
BIT
Figure 10-3. Sample Monitor Waveforms
The data transmit and receive rate is 9600 baud. Transmit and receive
baud rates will be identical.

Monitor ROM (MON)
10.4.5 Echoing
As shown in Figure 10-4, the monitor ROM immediately echoes each

received byte back to the PTB1/TXD pin for error checking.
SENT TO
MONITOR
READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA
ECHO
RESULT
Figure 10-4. Read Transaction
Any result of a command appears after the echo of the last byte of the
command.
10.4.6 Break Signal
A start bit, followed by nine low bits, is a break signal. See Figure 10-5.
When the monitor receives a break signal, it delays two bit times before
echoing the break signal.
MISSING STOP BIT

TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Figure 10-5. Break Transaction

Monitor ROM (MON)
10.4.7 Commands
The monitor ROM uses these commands:

• READ, read memory
• WRITE, write memory
• IREAD, indexed read
• IWRITE, indexed write
• READSP, read stack pointer
• RUN, run user program
Refer to Table 10-3 through Table 10-8.
Table 10-3. READ (Read Memory) Command

Description Read byte from memory
Operand Specifies 2-byte address in high byte:low byte order
Data returned Returns contents of specified address
Opcode $4A
Command sequence
SENT TO
MONITOR
READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA
ECHO
RESULT
Table 10-4. WRITE (Write Memory) Command

Description Write byte to memory
Operand Specifies 2-byte address in high byte:low byte order; low byte followed by data byte
Data returned None
Opcode $49
Command sequence
SENT TO
MONITOR
WRITE WRITE ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA DATA
ECHO

Monitor ROM (MON)
Table 10-5. IREAD (Indexed Read) Command

Description Read next 2 bytes in memory from last address accessed
Operand Specifies 2-byte address in high byte:low byte order
Data returned Returns contents of next two addresses
Opcode $1A
Command sequence
SENT TO
MONITOR
IREAD IREAD DATA DATA
ECHO RESULT
Table 10-6. IWRITE (Indexed Write) Command

Description Write to last address accessed + 1
Operand Specifies single data byte
Data returned None
Opcode $19
Command sequence
SENT TO
MONITOR
IWRITE IWRITE DATA DATA
ECHO
NOTE: A sequence of IREAD or IWRITE commands can sequentially access a

block of memory over the full 64-Kbyte memory map.

Monitor ROM (MON)
Table 10-7. READSP (Read Stack Pointer) Command

Description Reads stack pointer
Operand None
Data returned Returns stack pointer in high byte:low byte order
Opcode $0C
Command sequence
SENT TO
MONITOR
READSP READSP SP HIGH SP LOW
ECHO RESULT
Table 10-8. RUN (Run User Program) Command

Description Executes RTI instruction
Operand None
Data returned None
Opcode $28
Command sequence
SENT TO
MONITOR
RUN RUN
ECHO

Monitor ROM (MON)
10.5 Security
A security feature discourages unauthorized reading of ROM locations
while in monitor mode. The host can satisfy the security feature at
monitor mode entry by sending eight security bytes that match the bytes
at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain
user-defined data.
NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons,

program locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for
the host to send the eight security bytes on pin PTB0 (RXD). If the
received bytes match those at locations $FFF6–$FFFD, the host
satisfies the security feature and can read all ROM locations and
execute code from ROM. Security remains satisfied until a power-on
reset occurs. If the reset was not a power-on reset, security remains
satisfied and security code entry is not required. See Figure 10-6.
VDD
4096 + 32 CGMXCLK CYCLES
RST
24 BUS CYCLES
PA7
256 BUS CYCLES (MINIMUM)
COMMAND
BYTE 1
BYTE 2
BYTE 8
FROM HOST
PA0
1 4 1 1 2 4 1
FROM MCU
BYTE 1 ECHO
BYTE 2 ECHO
COMMAND ECHO
BYTE 8 ECHO
BREAK
Notes:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
Figure 10-6. Monitor Mode Entry Timing

Monitor ROM (MON)
Security
Upon power-on reset, if the received bytes of the security code do not
match the data at locations $FFF6–$FFFD, the host fails to satisfy the
security feature. The MCU remains in monitor mode, but reading a ROM
location returns an invalid value and trying to execute code from ROM
causes an illegal address reset. After receiving the eight security bytes
from the host, the MCU transmits a break character, signifying that it is
ready to receive a command.
NOTE: The MCU does not transmit a break character until after the host sends
the eight security bytes.
To determine whether the security code entered is correct, check to see

if bit 6 of RAM address $60 is set. If it is, then the correct security code
has been entered and ROM can be accessed.
If the security sequence fails, the device can be reset (via power-pin
reset only) and brought up in monitor mode to attempt another entry.
After failing the security sequence, the FLASH memory can also be bulk
erased by executing an erase routine that was downloaded into internal
RAM. The bulk erase operation clears the security code locations so that
all eight security bytes become $FF.

Monitor ROM (MON)

Section 11. Timer Interface A (TIMA)
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
11.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
11.4.1 TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . .204
11.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
11.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
11.4.4 Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . .207
11.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
11.6 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
11.7 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
11.8 TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .212
11.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
11.9.1 TIMA Clock Pin (PTB2/TCLKA) . . . . . . . . . . . . . . . . . . . .213
11.9.2 TIMA Channel I/O Pins (PTB3/TCH0A–PTB4/TCH1A) . . 213
11.10 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
11.10.1 TIMA Status and Control Register . . . . . . . . . . . . . . . . .214
11.10.2 TIMA Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . .216
11.10.3 TIMA Counter Modulo Registers. . . . . . . . . . . . . . . . . . .217
11.10.4 TIMA Channel Status and Control Registers. . . . . . . . .218
11.10.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . .222
Freescale Semiconductor Timer Interface A (TIMA) 199

Timer Interface A (TIMA)
11.2 Introduction
This section describes the timer interface module (TIMA). The TIMA is a
2-channel timer that provides:
• Timing reference with input capture
• Output compare
• Pulse-width modulation (PWM) functions
Refer to Figure 11-1 for a block diagram of the TIMA and to Figure 11-2
for a summary of the registers.
For further information regarding timers on M68HC08 family devices,

please consult the HC08 Timer Reference Manual, TIM08RM/AD.
11.3 Features
Features of the TIMA include:
• Two input capture/output compare channels:
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse-width modulation (PWM) signal
generation
• Programmable TIMA clock input:
– 7-frequency internal bus clock prescaler selection
– External TIMA clock input (4-MHz maximum frequency)
• Free-running or modulo up-count operation
• Toggle any channel pin on overflow
• TIMA counter stop and reset bits
200 Timer Interface A (TIMA) Freescale Semiconductor

Features
TCLK
PTB2/TCLKA
PRESCALER SELECT
INTERNAL BUS CLOCK PRESCALER
TSTOP
PS2 PS1 PS0
TRST
16-BIT COUNTER TOF INTERRUPT

TOIE LOGIC
16-BIT COMPARATOR
TMODH:TMODL
CHANNEL 0 ELS0B ELS0A

TOV0 PTB3
16-BIT COMPARATOR CH0MAX LOGIC PTB3/TCH0A
TCH0H:TCH0L CH0F
INTERRUPT
16-BIT LATCH
CH0IE LOGIC
MS0A MS0B
TOV1
16-BIT COMPARATOR CH1MAX PTB4 PTB4/TCH1A
LOGIC
TCH1H:TCH1L CH1F
16-BIT LATCH INTERRUPT
CH1IE LOGIC
MS1A
Figure 11-1. TIMA Block Diagram

Read
TOF 0 0
:
TIMA Status/Control Regis- TOIE TSTOP PS2 PS1 PS0
$000 Write
ter (TASC) 0 TRST R
E :
See page 214.
Re-
0 0 1 0 0 0 0 0
set:
Read
:
TIMA Counter Register High
$000 Write
(TACNTH) R R R R R R R R
F :
See page 216.
Re-
0 0 0 0 0 0 0 0
set:
R = Reserved
Figure 11-2. TIMA I/O Register Summary


Read
:
TIMA Counter Register Low
Write
$0010 (TACNTL) R R R R R R R R
:
See page 216.
Re-
0 0 0 0 0 0 0 0
set:
Read
:
TIMA Counter Modulo Reg- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write
$0011 ister High (TAMODH)
:
See page 217.
Re-
1 1 1 1 1 1 1 1
set:
Read
:
TIMA Counter Modulo Reg- Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write
$0012 ister Low (TAMODL)
:
See page 217.
Re-
1 1 1 1 1 1 1 1
set:
Read
CH0F
: CH0MA
TIMA Channel 0 Sta- CH0IE MS0B MS0A ELS0B ELS0A TOV0
tus/Control Register Write X
$0013 0
(TASC0) :
See page 218.
Re-
0 0 0 0 0 0 0 0
set:
Read
:
TIMA Channel 0 Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write
$0014 High (TACH0H)
:
See page 222.
Re-
Indeterminate after reset
set:
Read
:
Write
$0015 Low (TACH0L)
:
See page 218.
Re-
set:
R = Reserved
Figure 11-2. TIMA I/O Register Summary (Continued)

Features

Read
CH1F 0
: CH1MA
TIMA Channel 1 Sta- CH1IE MS1A ELS1B ELS1A TOV1
tus/Control Write X
$0016 0 R
Register (TASC1) :
See page 218.
Re-
0 0 0 0 0 0 0 0
set:
Read
:
Write
$0017 High (TACH1H)
:
See page 222.
Re-
set:
Read
:
Write
$0018 Low (TACH1L)
:
See page 222.
Re-
set:
R = Reserved
Figure 11-2. TIMA I/O Register Summary (Continued)


Figure 11-1 shows the TIMA structure. The central component of the
TIMA is the 16-bit TIMA counter that can operate as a free-running
counter or a modulo up-counter. The TIMA counter provides the timing
reference for the input capture and output compare functions. The TIMA
counter modulo registers, TAMODH–TAMODL, control the modulo
value of the TIMA counter. Software can read the TIMA counter value at
any time without affecting the counting sequence.
The two TIMA channels are programmable independently as input

capture or output compare channels.
11.4.1 TIMA Counter Prescaler
The TIMA clock source can be one of the seven prescaler outputs or the
TIMA clock pin, PTB2/TCLKA. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in
the TIMA status and control register select the TIMA clock source.
11.4.2 Input Capture
An input capture function has three basic parts:
1. Edge select logic

2. Input capture latch
3. 16-bit counter
Two 8-bit registers, which make up the 16-bit input capture register, are
used to latch the value of the free-running counter after the
corresponding input capture edge detector senses a defined transition.
The polarity of the active edge is programmable. The level transition
which triggers the counter transfer is defined by the corresponding input
edge bits (ELSxB and ELSxA in the TASC0 and TASC1 control registers
with x referring to the active channel number).
When an active edge occurs on the pin of an input capture channel, the
TIMA latches the contents of the TIMA counter into the TIMA channel
registers, TCHxH–TCHxL. Input captures can generate TIMA CPU
interrupt requests. Software can determine that an input capture event

has occurred by enabling input capture interrupts or by polling the status

flag bit.
The free-running counter contents are transferred to the TIMA channel

status and control registers TACHxH and TACHxL (see 11.10.5 TIMA
Channel Registers) on each proper signal transition regardless of
whether the TIMA channel flag (CH0F–CH1F in the TASC0–TASC1
registers) is set or clear. When the status flag is set, a CPU interrupt is
generated if enabled. The value of the count latched or captured is the
time of the event. Because this value is stored in the input capture
register two bus cycles after the actual event occurs, user software can
respond to this event at a later time and determine the actual time of the
event. However, this must be done prior to another input capture on the
same pin; otherwise, the previous time value will be lost.
By recording the times for successive edges on an incoming signal,

software can determine the period and/or pulse width of the signal. To
measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are
captured. Software should track the overflows at the 16-bit module
counter to extend its range.
Another use for the input capture function is to establish a time

reference. In this case, an input capture function is used in conjunction
with an output compare function. For example, to activate an output
signal a specified number of clock cycles after detecting an input event
(edge), use the input capture function to record the time at which the
edge occurred. A number corresponding to the desired delay is added to
this captured value and stored to an output compare register (see
11.10.5 TIMA Channel Registers). Because both input captures and
output compares are referenced to the same 16-bit modulo counter, the
delay can be controlled to the resolution of the counter independent of
software latencies.
NOTE: Reset does not affect the contents of the input capture channel register
(TACHxH–TACHxL).
11.4.3 Output Compare
With the output compare function, the TIMA can generate a periodic
pulse with a programmable polarity, duration, and frequency. When the

counter reaches the value in the registers of an output compare channel,

the TIMA can set, clear, or toggle the channel pin. Output compares can
generate TIMA CPU interrupt requests.
11.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare

pulses as described in 11.4.3 Output Compare. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIMA channel registers.
An unsynchronized write to the TIMA channel registers to change an

output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIMA overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIMA may
pass the new value before it is written.
Use these methods to synchronize unbuffered changes in the output

compare value on channel x:
• When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
• When changing to a larger output compare value, enable TIMA
overflow interrupts and write the new value in the TIMA overflow
interrupt routine. The TIMA overflow interrupt occurs at the end of
the current counter overflow period. Writing a larger value in an
output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same counter
overflow period.
11.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare

channel whose output appears on the PTB3/TCH0A pin. The TIMA
channel registers of the linked pair alternately control the output.

Setting the MS0B bit in TIMA channel 0 status and control register
(TASC0) links channel 0 and channel 1. The output compare value in the
TIMA channel 0 registers initially controls the output on the
PTB3/TCH0A pin. Writing to the TIMA channel 1 registers enables the
TIMA channel 1 registers to synchronously control the output after the
TIMA overflows. At each subsequent overflow, the TIMA channel
registers (0 or 1) that control the output are the ones written to last. TSC0
controls and monitors the buffered output compare function, and TIMA
channel 1 status and control register (TASC1) is unused. While the
MS0B bit is set, the channel 1 pin, PTB4/TCH1A, is available as a
general-purpose input/output (I/O) pin.
NOTE: In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should
track the currently active channel to prevent writing a new value to the
active channel. Writing to the active channel registers is the same as
generating unbuffered output compares.
11.4.4 Pulse-Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel,

the TIMA can generate a PWM signal. The value in the TIMA counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIMA counter
modulo registers. The time between overflows is the period of the PWM
signal.
As Figure 11-3 shows, the output compare value in the TIMA channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIMA to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIMA to set the pin if the state of the PWM
pulse is logic 0.

OVERFLOW OVERFLOW OVERFLOW
PERIOD
PULSE
WIDTH
PTBx/TCHx
OUTPUT OUTPUT OUTPUT

COMPARE COMPARE COMPARE
Figure 11-3. PWM Period and Pulse Width
The value in the TIMA counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMA counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000. See 11.10.1 TIMA Status and Control Register.
The value in the TIMA channel registers determines the pulse width of
the PWM output. The pulse width of an 8-bit PWM signal is variable in
256 increments. Writing $0080 (128) to the TIMA channel registers
produces a duty cycle of 128/256 or 50 percent.
11.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as

described in 11.4.4 Pulse-Width Modulation (PWM). The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the value currently in the TIMA channel registers.
An unsynchronized write to the TIMA channel registers to change a

pulse width value could cause incorrect operation for up to two PWM
periods. For example, writing a new value before the counter reaches
the old value but after the counter reaches the new value prevents any
compare during that PWM period. Also, using a TIMA overflow interrupt
routine to write a new, smaller pulse width value may cause the compare
to be missed. The TIMA may pass the new value before it is written to
the TIMA channel registers.

Use these methods to synchronize unbuffered changes in the PWM

pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
• When changing to a longer pulse width, enable TIMA overflow
interrupts and write the new value in the TIMA overflow interrupt
routine. The TIMA overflow interrupt occurs at the end of the
current PWM period. Writing a larger value in an output compare
interrupt routine (at the end of the current pulse) could cause two
output compares to occur in the same PWM period.
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable
0 percent duty cycle generation and removes the ability of the channel
to self-correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
11.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose

output appears on the PTB3/TCH0A pin. The TIMA channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIMA channel 0 status and control register
(TASC0) links channel 0 and channel 1. The TIMA channel 0 registers
initially control the pulse width on the PTB3/TCH0A pin. Writing to the
TIMA channel 1 registers enables the TIMA channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMA channel registers (0 or
1) that control the pulse width are the ones written to last. TASC0
controls and monitors the buffered PWM function, and TIMA channel 1
status and control register (TASC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTB4/TCH1A, is available as a general-purpose I/O
pin.

NOTE: In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as
generating unbuffered PWM signals.
11.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered

PWM signals, use this initialization procedure:
1. In the TIMA status and control register (TASC):
a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP.
b. Reset the TIMA counter and prescaler by setting the TIMA
reset bit, TRST.
2. In the TIMA counter modulo registers (TAMODH–TAMODL), write
the value for the required PWM period.
3. In the TIMA channel x registers (TACHxH–TACHxL), write the
value for the required pulse width.
4. In TIMA channel x status and control register (TASCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB–MSxA. See Table 11-2.
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. See Table 11-2.
compare can also cause incorrect PWM signal generation when
5. In the TIMA status control register (TASC), clear the TIMA stop bit,
TSTOP.

Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMA channel 0 registers (TACH0H–TACH0L)
initially control the buffered PWM output. TIMA status control register 0
(TASC0) controls and monitors the PWM signal from the linked
channels. MS0B takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on

TIMA overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0 percent duty
cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100 percent duty cycle output. See 11.10.4 TIMA
Channel Status and Control Registers.
11.5 Interrupts
These TIMA sources can generate interrupt requests:
• TIMA overflow flag (TOF) — The TOF bit is set when the TIMA
counter reaches the modulo value programmed in the TIMA
counter modulo registers. The TIMA overflow interrupt enable bit,
TOIE, enables TIMA overflow CPU interrupt requests. TOF and
TOIE are in the TIMA status and control register.
• TIMA channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIMA CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
11.6 Wait Mode

The WAIT instruction puts the MCU in low-power standby mode.
The TIMA remains active after the execution of a WAIT instruction. In

wait mode, the TIMA registers are not accessible by the CPU. Any
enabled CPU interrupt request from the TIMA can bring the MCU out of
wait mode.

If TIMA functions are not required during wait mode, reduce power
consumption by stopping the TIMA before executing the WAIT
instruction.
11.7 Stop Mode

TIMA is inactive after execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIMA
counter. TIMA operation resumes when the MCU exits stop mode after
an external interrupt.
11.8 TIMA During Break Interrupts

A break interrupt stops the TIMA counter and inhibits input captures.

Register.

To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
11.9 I/O Signals

Port B shares three of its pins with the TIMA. PTB2/TCLKA is an external
clock input to the TIMA prescaler. The two TIMA channel I/O pins are
PTB3/TCH0A and PTB4/TCH1A.

I/O Registers
11.9.1 TIMA Clock Pin (PTB2/TCLKA)
PTB2/TCLKA is an external clock input that can be the clock source for
the TIMA counter instead of the prescaled internal bus clock. Select the
PTB2/TCLKA input by writing logic 1s to the three prescaler select bits,
PS[2:0] (see 11.10.1 TIMA Status and Control Register). The
minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is:
1
------------------------------------- + t su
bus frequency
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTB2/TCLKA is available as a general-purpose I/O pin or ADC channel

when not used as the TIMA clock input. When the PTB2/TCLKA pin is
the TIMA clock input, it is an input regardless of the state of the DDRB2
bit in data direction register B.
11.9.2 TIMA Channel I/O Pins (PTB3/TCH0A–PTB4/TCH1A)
Each channel I/O pin is programmable independently as an input

capture pin or an output compare pin. PTB3/TCH0A and PTB3/TCH1A
can be configured as buffered output compare or buffered PWM pins.
11.10 I/O Registers

These I/O registers control and monitor TIMA operation:
• TIMA status and control register (TASC)
• TIMA control registers (TACNTH–TACNTL)
• TIMA counter modulo registers (TAMODH–TAMODL)
• TIMA channel status and control registers (TASC0 and TASC1)
• TIMA channel registers (TACH0H–TACH0L and
TACH1H–TACH1L)

11.10.1 TIMA Status and Control Register
The TIMA status and control register:

• Enables TIMA overflow interrupts
• Flags TIMA overflows
• Stops the TIMA counter
• Resets the TIMA counter
• Prescales the TIMA counter clock
Address $000E
:
Bit 7 6 5 4 3 2 1 Bit 0
Read: TOF 0 0
TOIE TSTOP PS2 PS1 PS0
Write: 0 TRST R
Reset: 0 0 1 0 0 0 0 0
R = Reserved
Figure 11-4. TIMA Status and Control Register (TASC)
TOF — TIMA Overflow Flag Bit

This read/write flag is set when the TIMA counter reaches the modulo
value programmed in the TIMA counter modulo registers. Clear TOF
by reading the TIMA status and control register when TOF is set and
then writing a logic 0 to TOF. If another TIMA overflow occurs before
the clearing sequence is complete, then writing logic 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic
1 to TOF has no effect.
1 = TIMA counter has reached modulo value.
0 = TIMA counter has not reached modulo value.
TOIE — TIMA Overflow Interrupt Enable Bit
This read/write bit enables TIMA overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIMA overflow interrupts enabled
0 = TIMA overflow interrupts disabled

I/O Registers
TSTOP — TIMA Stop Bit

This read/write bit stops the TIMA counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMA
counter until software clears the TSTOP bit.
1 = TIMA counter stopped
0 = TIMA counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIMA is
required to exit wait mode. Also, when the TSTOP bit is set and the timer
is configured for input capture operation, input captures are inhibited
until TSTOP is cleared.
TRST — TIMA Reset Bit

Setting this write-only bit resets the TIMA counter and the TIMA
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIMA counter is reset and always reads as logic 0. Reset clears
the TRST bit.
1 = Prescaler and TIMA counter cleared
0 = No effect
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMA
counter at a value of $0000.
PS[2:0] — Prescaler Select Bits

These read/write bits select either the PTB2/TCLKA pin or one of the
seven prescaler outputs as the input to the TIMA counter as
Table 11-1 shows. Reset clears the PS[2:0] bits.
Table 11-1. Prescaler Selection

PS[2:0] TIMA Clock Source
000 Internal bus clock ÷ 1
111 PTB2/TCLKA

11.10.2 TIMA Counter Registers
The two read-only TIMA counter registers contain the high and low bytes
of the value in the TIMA counter. Reading the high byte (TACNTH)
latches the contents of the low byte (TACNTL) into a buffer. Subsequent
reads of TACNTH do not affect the latched TACNTL value until TACNTL
is read. Reset clears the TIMA counter registers. Setting the TIMA reset
bit (TRST) also clears the TIMA counter registers.
NOTE: If TACNTH is read during a break interrupt, be sure to unlatch TACNTL

by reading TACNTL before exiting the break interrupt. Otherwise,
TACNTL retains the value latched during the break.
Register Name and Ad- TACNTH — $000F

dress:
Bit 7 6 5 4 3 2 1 Bit 0
Reset: 0 0 0 0 0 0 0 0
Register Name and Ad- TACNTL — $0010

dress:
Bit 7 6 5 4 3 2 1 Bit 0
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Figure 11-5. TIMA Counter Registers (TACNTH and TACNTL)

I/O Registers
11.10.3 TIMA Counter Modulo Registers
The read/write TIMA modulo registers contain the modulo value for the
TIMA counter. When the TIMA counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIMA counter resumes
counting from $0000 at the next timer clock. Writing to the high byte
(TMODH) inhibits the TOF bit and overflow interrupts until the low byte
(TMODL) is written. Reset sets the TIMA counter modulo registers.
Register Name and Ad- TAMODH — $0011

dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: 1 1 1 1 1 1 1 1
Register Name and Ad- TAMODL — $0012

dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: 1 1 1 1 1 1 1 1
Figure 11-6. TIMA Counter Modulo Registers (TMODH and TMODL)
NOTE: Reset the TIMA counter before writing to the TIMA counter modulo
registers.

11.10.4 TIMA Channel Status and Control Registers
Each of the TIMA channel status and control registers:

• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input
capture trigger
• Selects output toggling on TIMA overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Register Name and Ad- TASC0 — $0013

dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: CH0F CH0MA

CH0IE MS0B MS0A ELS0B ELS0A TOV0
Write: 0 X
Reset: 0 0 0 0 0 0 0 0
Register Name and Ad- TASC1 — $0016

dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: CH1F 0 CH1MA

CH1IE MS1A ELS1B ELS1A TOV1
Write: 0 R X
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Figure 11-7. TIMA Channel Status and Control Registers

(TASC0–TASC1)

I/O Registers
CHxF — Channel x Flag Bit

When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIMA
counter registers matches the value in the TIMA channel x registers.
When CHxIE = 1, clear CHxF by reading TIMA channel x status and
control register with CHxF set, and then writing a logic 0 to CHxF. If
another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMA CPU interrupts on channel x. Reset
clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIMA channel 0. Setting MS0B disables the
channel 1 status and control register and reverts TCH1A to
general-purpose I/O. Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation. See
Table 11-2.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin once PWM, input capture, or output compare
operation is enabled. Reset clears the MSxA bit. See Table 11-2.
1 = Initial output level low
0 = Initial output level high

NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIMA status and control register
(TASC).
ELSxB and ELSxA — Edge/Level Select Bits

When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port B, and pin PTBx/TCHxA is available as a general-purpose I/O
pin. However, channel x is at a state determined by these bits and
becomes transparent to the respective pin when PWM, input capture,
or output compare mode is enabled. Table 11-2 shows how ELSxA
and ELSxA work. Reset clears the ELSxB and ELSxA bits.
Table 11-2. Mode, Edge, and Level Selection

MSxB:MSxA ELSxB:ELSxA Mode Configuration
X0 00 Pin under port control:

Initialize timer
Output Output level high
X1 00 preset Pin under port control:

Initialize timer
Output level low
00 01 Capture on rising edge only

Input
00 10 Capture on falling edge only
capture
00 11 Capture on rising or falling edge
01 01 Toggle output on compare

Output
01 10 compare Clear output on compare
or PWM
01 11 Set output on compare
1X 01 Buffered Toggle output on compare

output
1X 10 compare Clear output on compare
or
1X 11 buffered Set output on compare
PWM

I/O Registers
NOTE: Before enabling a TIMA channel register for input capture operation,
make sure that the PTBx/TACHx pin is stable for at least two bus clocks.
TOVx — Toggle-On-Overflow Bit

When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIMA counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIMA counter overflow.
0 = Channel x pin does not toggle on TIMA counter overflow.
NOTE: When TOVx is set, a TIMA counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit

When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100 percent. As
Figure 11-8 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100 percent duty cycle level
until the cycle after CHxMAX is cleared.
OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW
PERIOD
PTBx/TCHx
OUTPUT OUTPUT OUTPUT OUTPUT

COMPARE COMPARE COMPARE COMPARE
CHxMAX
TOVx
Figure 11-8. CHxMAX Latency

11.10.5 TIMA Channel Registers
These read/write registers contain the captured TIMA counter value of

the input capture function or the output compare value of the output
compare function. The state of the TIMA channel registers after reset is
unknown.
In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the
TIMA channel x registers (TACHxH) inhibits input captures until the low
byte (TACHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of

the TIMA channel x registers (TACHxH) inhibits output compares until
the low byte (TACHxL) is written.
Register Name and Address: TACH0H — $0014

Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Register Name and Address: TACH0L — $0015
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Register Name and Address: TACH1H — $0017
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Register Name and Address: TACH1L — $0018
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Figure 11-9. TIMA Channel Registers (TACH0H/L–TACH1H/L)

Section 12. Timer Interface B (TIMB)
12.1 Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
12.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
12.4.1 TIMB Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . .228
12.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
12.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
12.4.4 Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . .231
12.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
12.6 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
12.7 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
12.8 TIMB During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .236
12.9 TIMB Channel I/O Pins (PTB5/TCH0B–PTB6/TCH1B) . . . .237
12.10 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
12.10.1 TIMB Status and Control Register . . . . . . . . . . . . . . . . .237
12.10.2 TIMB Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . .240
12.10.3 TIMB Counter Modulo Registers. . . . . . . . . . . . . . . . . . .241
12.10.4 TIMB Channel Status and Control Registers. . . . . . . . .242
12.10.5 TIMB Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . .245
Freescale Semiconductor Timer Interface B (TIMB) 223

Timer Interface B (TIMB)
12.2 Introduction
This section describes the timer interface module (TIMB). The TIMB is a
2-channel timer that provides:
• A timing reference with input capture
• Output compare
• Pulse width modulation (PWM) functions
Refer to Figure 12-1 for a block diagram of the TIMB and to Figure 12-2
for a summary of the registers.
For further information regarding timers on M68HC08 family devices,

please consult the HC08 Timer Reference Manual, TIM08RM/AD.
12.3 Features
Features of the TIMB include:
• Two input capture/output compare channels
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered PWM signal generation
• Programmable TIMB clock with 7-frequency internal bus clock
prescaler selection
• Free-running or modulo up-count operation
• Toggle any channel pin on overflow
• TIMB counter stop and reset bits
224 Timer Interface B (TIMB) Freescale Semiconductor

Features
INTERNAL PRESCALER SELECT

BUS CLOCK PRESCALER
TSTOP
PS2 PS1 PS0
TRST
16-BIT COUNTER TOF INTERRUPT

TOIE LOGIC
16-BIT COMPARATOR
TMODH:TMODL

TOV0
PTB5 PTB5/TCH0B
16-BIT COMPARATOR CH0MAX LOGIC
TCH0H:TCH0L CH0F
INTERRUPT
16-BIT LATCH LOGIC
MS0A CH0IE
MS0B
TOV1
PTB6 PTB6/TCH1B
16-BIT COMPARATOR CH1MAX LOGIC
TCH1H:TCH1L CH1F
INTERRUPT
16-BIT LATCH LOGIC
MS1A CH1IE
Figure 12-1. TIMB Block Diagram
Read
TOF 0 0
:
TIMB Status/Control Regis- TOIE TSTOP PS2 PS1 PS0
ter Write
$0051 0 TRST R
(TBSC) :
See page 238.
Re-
0 0 1 0 0 0 0 0
set:
Read
:
TIMB Counter Register High
Write
$0052 (TBCNTH) R R R R R R R R
:
See page 240.
Re-
0 0 0 0 0 0 0 0
set:
R = Reserved
Figure 12-2. TIMB I/O Register Summary

Read
:
TIMB Counter Register Low
Write
$0053 (TBCNTL) R R R R R R R R
:
See page 240.
Re-
0 0 0 0 0 0 0 0
set:
Read
:
TIMB Counter Modulo Reg- Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
ister High Write
$0054
(TBMODH) :
See page 241.
Re-
1 1 1 1 1 1 1 1
set:
Read
:
TIMB Counter Modulo Reg- Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ister Low Write
$0055
(TBMODL) :
See page 241.
Re-
1 1 1 1 1 1 1 1
set:
Read
CH0F
: CH0MA
TIMB Channel 0 Sta- CH0IE MS0B MS0A ELS0B ELS0A TOV0
$0056 0
(TBSC0) :
See page 242.
Re-
0 0 0 0 0 0 0 0
set:
Read
:
TIMB Channel 0 Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
High Write
$0057
(TBCH0H) :
See page 246.
Re-
set:
R = Reserved
Figure 12-2. TIMB I/O Register Summary (Continued)

Read
:
Low Write
$0058
(TBCH0L) :
See page 246.
Re-
set:
Read
CH1F 0
: CH1MA
TIMB Channel 1 Sta- CH1IE MS1A ELS1B ELS1A TOV1
$0059 0 R
(TBSC1) :
See page 246.
Re-
0 0 0 0 0 0 0 0
set:
Read
:
$005 High Write
A (TBCH1H) :
See page 246.
Re-
set:
Read
:
$005 Low Write
B (TBCH1L) :
See page 246.
Re-
set:
R = Reserved
Figure 12-2. TIMB I/O Register Summary (Continued)

Figure 12-1 shows the TIMB structure. The central component of the
TIMB is the 16-bit TIMB counter that can operate as a free-running
counter or a modulo up-counter. The TIMB counter provides the timing
reference for the input capture and output compare functions. The TIMB
counter modulo registers, TBMODH–TBMODL, control the modulo
value of the TIMB counter. Software can read the TIMB counter value at
any time without affecting the counting sequence.

The two TIMB channels are programmable independently as input

capture or output compare channels.
12.4.1 TIMB Counter Prescaler
The TIMB clock source can be one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIMB status and control register
select the TIMB clock source.
12.4.2 Input Capture
An input capture function has three basic parts:

• Edge select logic
• Input capture latch
• 16-bit counter
Two 8-bit registers, which make up the 16-bit input capture register, are
used to latch the value of the free-running counter after the
corresponding input capture edge detector senses a defined transition.
The polarity of the active edge is programmable. The level transition
which triggers the counter transfer is defined by the corresponding input
edge bits (ELSxB and ELSxA in TBSC0 through TBSC1 control registers
with x referring to the active channel number). When an active edge
occurs on the pin of an input capture channel, the TIMB latches the
contents of the TIMB counter into the TIMB channel registers,
TCHxH–TCHxL. Input captures can generate TIMB CPU interrupt
requests. Software can determine that an input capture event has
occurred by enabling input capture interrupts or by polling the status flag
bit.
The free-running counter contents are transferred to the TIMB channel

status and control register, TBCHxH–TBCHxL, (see 12.10.5 TIMB
Channel Registers) on each proper signal transition regardless of
whether the TIMB channel flag (CH0F–CH1F in TBSC0–TBSC1
registers) is set or clear. When the status flag is set, a CPU interrupt is
generated if enabled. The value of the count latched or “captured” is the
time of the event. Because this value is stored in the input capture
register two bus cycles after the actual event occurs, user software can

respond to this event at a later time and determine the actual time of the
event. However, this must be done prior to another input capture on the
same pin; otherwise, the previous time value will be lost.
By recording the times for successive edges on an incoming signal,

software can determine the period and/or pulse width of the signal. To
measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are
captured. Software should track the overflows at the 16-bit module
counter to extend its range.
Another use for the input capture function is to establish a time

reference. In this case, an input capture function is used in conjunction
with an output compare function. For example, to activate an output
signal a specified number of clock cycles after detecting an input event
(edge), use the input capture function to record the time at which the
edge occurred. A number corresponding to the desired delay is added to
this captured value and stored to an output compare register (see
12.10.5 TIMB Channel Registers). Because both input captures and
output compares are referenced to the same 16-bit modulo counter, the
delay can be controlled to the resolution of the counter independent of
software latencies.
NOTE: Reset does not affect the contents of the input capture channel register
(TBCHxH–TBCHxL).

12.4.3 Output Compare
With the output compare function, the TIMB can generate a periodic
pulse with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIMB can set, clear, or toggle the channel pin. Output compares can
generate TIMB CPU interrupt requests.
12.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare

pulses as described in 12.4.3 Output Compare. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIMB channel registers.
An unsynchronized write to the TIMB channel registers to change an

output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIMB overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIMB may
pass the new value before it is written.
Use these methods to synchronize unbuffered changes in the output

compare value on channel x:
• When changing to a smaller value, enable channel x output
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
• When changing to a larger output compare value, enable TIMB
overflow interrupts and write the new value in the TIMB overflow
interrupt routine. The TIMB overflow interrupt occurs at the end of
the current counter overflow period. Writing a larger value in an
output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same counter
overflow period.

12.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare

channel whose output appears on the PTB5/TCH0B pin. The TIMB
channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMB channel 0 status and control register
(TBSC0) links channel 0 and channel 1. The output compare value in the
TIMB channel 0 registers initially controls the output on the
PTB5/TCH0B pin. Writing to the TIMB channel 1 registers enables the
TIMB channel 1 registers to synchronously control the output after the
TIMB overflows. At each subsequent overflow, the TIMB channel
registers (0 or 1) that control the output are the ones written to last. TSC0
controls and monitors the buffered output compare function, and TIMB
channel 1 status and control register (TBSC1) is unused. While the
MS0B bit is set, the channel 1 pin, PTB6/TCH1B, is available as a
general-purpose input/output (I/O) pin.
NOTE: In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should
track the currently active channel to prevent writing a new value to the
active channel. Writing to the active channel registers is the same as
generating unbuffered output compares.
12.4.4 Pulse-Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel,

the TIMB can generate a PWM signal. The value in the TIMB counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIMB counter
modulo registers. The time between overflows is the period of the PWM
signal.
As Figure 12-3 shows, the output compare value in the TIMB channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIMB to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIMB to set the pin if the state of the PWM
pulse is logic 0.

OVERFLOW OVERFLOW OVERFLOW
PERIOD
PULSE
WIDTH
PTBx/TCHx
OUTPUT OUTPUT OUTPUT

COMPARE COMPARE COMPARE
Figure 12-3. PWM Period and Pulse Width
The value in the TIMB counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMB counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000 (see 12.10.1 TIMB Status and Control Register).
The value in the TIMB channel registers determines the pulse width of
the PWM output. The pulse width of an 8-bit PWM signal is variable in
256 increments. Writing $0080 (128) to the TIMB channel registers
produces a duty cycle of 128/256 or 50 percent.
12.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as

described in 12.4.4 Pulse-Width Modulation (PWM). The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the value currently in the TIMB channel registers.
An unsynchronized write to the TIMB channel registers to change a

pulse width value could cause incorrect operation for up to two PWM
periods. For example, writing a new value before the counter reaches
the old value but after the counter reaches the new value prevents any
compare during that PWM period. Also, using a TIMB overflow interrupt
routine to write a new, smaller pulse width value may cause the compare
to be missed. The TIMB may pass the new value before it is written to
the TIMB channel registers.

Use these methods to synchronize unbuffered changes in the PWM

pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
• When changing to a longer pulse width, enable TIMB overflow
interrupts and write the new value in the TIMB overflow interrupt
routine. The TIMB overflow interrupt occurs at the end of the
current PWM period. Writing a larger value in an output compare
interrupt routine (at the end of the current pulse) could cause two
output compares to occur in the same PWM period.
compare also can cause incorrect PWM signal generation when
12.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose

output appears on the PTB5/TCH0B pin. The TIMB channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIMB channel 0 status and control register
(TBSC0) links channel 0 and channel 1. The TIMB channel 0 registers
initially control the pulse width on the PTB5/TCH0B pin. Writing to the
TIMB channel 1 registers enables the TIMB channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMB channel registers (0 or
1) that control the pulse width are the ones written to last. TBSC0
controls and monitors the buffered PWM function, and TIMB channel 1
status and control register (TBSC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTB6/TCH1B, is available as a general-purpose I/O
pin.

NOTE: In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as
generating unbuffered PWM signals.
12.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered

PWM signals, use this initialization procedure:
1. In the TIMB status and control register (TBSC):

a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP.
b. Reset the TIMB counter and prescaler by setting the TIMB
reset bit, TRST.
2. In the TIMB counter modulo registers (TBMODH–TBMODL), write
the value for the required PWM period.
3. In the TIMB channel x registers (TBCHxH–TBCHxL), write the
value for the required pulse width.
4. In TIMB channel x status and control register (TBSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB–MSxA. See Table 12-2.
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. See Table 12-2.
compare can also cause incorrect PWM signal generation when
5. In the TIMB status control register (TBSC), clear the TIMB stop bit,
TSTOP.

Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMB channel 0 registers (TBCH0H–TBCH0L)
initially control the buffered PWM output. TIMB status control register 0
(TBSC0) controls and monitors the PWM signal from the linked
channels. MS0B takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on

TIMB overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0 percent duty
cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100 percent duty cycle output. See 12.10.4 TIMB
Channel Status and Control Registers.
12.5 Interrupts
These TIMB sources can generate interrupt requests:
• TIMB overflow flag (TOF) — The TOF bit is set when the TIMB
counter reaches the modulo value programmed in the TIMB
counter modulo registers. The TIMB overflow interrupt enable bit,
TOIE, enables TIMB overflow CPU interrupt requests. TOF and
TOIE are in the TIMB status and control register.
• TIMB channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIMB CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
12.6 Wait Mode

The WAIT instruction puts the MCU in low-power standby mode.
The TIMB remains active after the execution of a WAIT instruction. In

wait mode, the TIMB registers are not accessible by the CPU. Any
enabled CPU interrupt request from the TIMB can bring the MCU out of
wait mode.

If TIMB functions are not required during wait mode, reduce power
consumption by stopping the TIMB before executing the WAIT
instruction.
12.7 Stop Mode

TIMB is inactive after execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIMB
counter.
TIMB operation resumes when the MCU exits stop mode after an
external interrupt.
12.8 TIMB During Break Interrupts

A break interrupt stops the TIMB counter and inhibits input captures.

Register.


TIMB Channel I/O Pins (PTB5/TCH0B–PTB6/TCH1B)
12.9 TIMB Channel I/O Pins (PTB5/TCH0B–PTB6/TCH1B)

Port B shares two of its pins with the TIMB. The two TIMB channel I/O
pins are PTB5/TCH0B and PTB6/TCH1B.
Each channel I/O pin is programmable independently as an input

capture pin or an output compare pin. PTB5/TCH0B and PTB6/TCH1B
can be configured as buffered output compare or buffered PWM pins.
12.10 I/O Registers

These I/O registers control and monitor TIMB operation:
• TIMB status and control register (TBSC)
• TIMB control registers (TBCNTH–TBCNTL)
• TIMB counter modulo registers (TBMODH–TBMODL)
• TIMB channel status and control registers (TBSC0 and TBSC1)
• TIMB channel registers (TBCH0H–TBCH0L and
TBCH1H–TBCH1L)
12.10.1 TIMB Status and Control Register
The TIMB status and control register:

• Enables TIMB overflow interrupts
• Flags TIMB overflows
• Stops the TIMB counter
• Resets the TIMB counter
• Prescales the TIMB counter clock

Address $0051
:
Bit 7 6 5 4 3 2 1 Bit 0
Read: TOF 0 0
TOIE TSTOP PS2 PS1 PS0
Write: 0 TRST R
Reset: 0 0 1 0 0 0 0 0
R = Reserved
Figure 12-4. TIMB Status and Control Register (TBSC)
TOF — TIMB Overflow Flag Bit

This read/write flag is set when the TIMB counter reaches the modulo
value programmed in the TIMB counter modulo registers. Clear TOF
by reading the TIMB status and control register when TOF is set and
then writing a logic 0 to TOF. If another TIMB overflow occurs before
the clearing sequence is complete, then writing logic 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic
1 to TOF has no effect.
1 = TIMB counter has reached modulo value.
0 = TIMB counter has not reached modulo value.
TOIE — TIMB Overflow Interrupt Enable Bit
This read/write bit enables TIMB overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIMB overflow interrupts enabled
0 = TIMB overflow interrupts disabled
TSTOP — TIMB Stop Bit
This read/write bit stops the TIMB counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMB
counter until software clears the TSTOP bit.
1 = TIMB counter stopped
0 = TIMB counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIMB is
required to exit wait mode. Also, when the TSTOP bit is set and the timer
is configured for input capture operation, input captures are inhibited
until TSTOP is cleared.

I/O Registers
TRST — TIMB Reset Bit

Setting this write-only bit resets the TIMB counter and the TIMB
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIMB counter is reset and always reads as logic 0. Reset clears
the TRST bit.
1 = Prescaler and TIMB counter cleared
0 = No effect
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMB
counter at a value of $0000.
PS[2:0] — Prescaler Select Bits

These read/write bits select one of the seven prescaler outputs as the
input to the TIMB counter as Table 12-1 shows. Reset clears the
PS[2:0] bits.
Table 12-1. Prescaler Selection

PS[2:0] TIMB Clock Source
000 Internal Bus Clock ÷ 1
111 Invalid: do not use this value

12.10.2 TIMB Counter Registers
The two read-only TIMB counter registers contain the high and low bytes
of the value in the TIMB counter. Reading the high byte (TBCNTH)
latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL
is read. Reset clears the TIMB counter registers. Setting the TIMB reset
bit (TRST) also clears the TIMB counter registers.
NOTE: If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL

by reading TBCNTL before exiting the break interrupt. Otherwise,
TBCNTL retains the value latched during the break.
Register Name and Ad- TBCNTH — $0052

dress:
Bit 7 6 5 4 3 2 1 Bit 0
Reset: 0 0 0 0 0 0 0 0
Register Name and Ad- TBCNTL — $0053

dress:
Bit 7 6 5 4 3 2 1 Bit 0
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Figure 12-5. TIMB Counter Registers (TBCNTH and TBCNTL)

I/O Registers
12.10.3 TIMB Counter Modulo Registers
The read/write TIMB modulo registers contain the modulo value for the
TIMB counter. When the TIMB counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIMB counter resumes
counting from $0000 at the next timer clock. Writing to the high byte
(TMODH) inhibits the TOF bit and overflow interrupts until the low byte
(TMODL) is written. Reset sets the TIMB counter modulo registers.
Register Name and Ad- TBMODH — $0054

dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: 1 1 1 1 1 1 1 1
Register Name and Ad- TBMODL — $0055

dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: 1 1 1 1 1 1 1 1
Figure 12-6. TIMB Counter Modulo Registers (TMODH and TMODL)
NOTE: Reset the TIMB counter before writing to the TIMB counter modulo
registers.

12.10.4 TIMB Channel Status and Control Registers
Each of the TIMB channel status and control registers:

• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input
capture trigger
• Selects output toggling on TIMB overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Register Name and Ad- TBSC0 — $0056

dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: CH0F CH0MA
CH0IE MS0B MS0A ELS0B ELS0A TOV0
Write: 0 X
Reset: 0 0 0 0 0 0 0 0
Register Name and Ad- TBSC1 — $0059

dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: CH1F 0 CH1MA
CH1IE MS1A ELS1B ELS1A TOV1
Write: 0 R X
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Figure 12-7. TIMB Channel Status and Control Registers

(TBSC0–TBSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIMB
counter registers matches the value in the TIMB channel x registers.

I/O Registers
When CHxIE = 1, clear CHxF by reading TIMB channel x status and

control register with CHxF set, and then writing a logic 0 to CHxF. If
another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMB CPU interrupts on channel x. Reset
clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIMB channel 0. Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation. See
Table 12-2.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin once PWM, input capture, or output compare
operation is enabled. Reset clears the MSxA bit. See Table 12-2.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIMB status and control register
(TBSC).

ELSxB and ELSxA — Edge/Level Select Bits

When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port B, and pin PTBx/TCHxB is available as a general-purpose I/O
pin. However, channel x is at a state determined by these bits and
becomes transparent to the respective pin when PWM, input capture,
or output compare mode is enabled. Table 12-2 shows how ELSxA
and ELSxA work. Reset clears the ELSxB and ELSxA bits.
Table 12-2. Mode, Edge, and Level Selection

MSxB:MSxA ELSxB:ELSxA Mode Configuration
X0 00 Pin under port control;
Initialize timer
Output Output level high
X1 00 preset Pin under port control;
Initialize timer
Output level low
00 01 Capture on rising edge only
Input
00 10 Capture on falling edge only
capture
00 11 Capture on rising or falling edge
01 01 Toggle output on compare
Output
01 10 compare Clear output on compare
or PWM
01 11 Set output on compare
1X 01 Buffered Toggle output on compare
output
1X 10 Clear output on compare
compare
or
1X 11 buffered Set output on compare
PWM
NOTE: Before enabling a TIMB channel register for input capture operation,
make sure that the PTBx/TBCHx pin is stable for at least two bus clocks.

I/O Registers
TOVx — Toggle-On-Overflow Bit

When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIMB counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIMB counter overflow.
0 = Channel x pin does not toggle on TIMB counter overflow.
NOTE: When TOVx is set, a TIMB counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit

When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100 percent. As
Figure 12-8 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100 percent duty cycle level
until the cycle after CHxMAX is cleared.
OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW
PERIOD
PTBx/TCHx
OUTPUT OUTPUT OUTPUT OUTPUT

COMPARE COMPARE COMPARE COMPARE
CHxMAX
TOVx
Figure 12-8. CHxMAX Latency
12.10.5 TIMB Channel Registers
These read/write registers contain the captured TIMB counter value of

the input capture function or the output compare value of the output
compare function. The state of the TIMB channel registers after reset is
unknown.

In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the
TIMB channel x registers (TBCHxH) inhibits input captures until the low
byte (TBCHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of

the TIMB channel x registers (TBCHxH) inhibits output compares until
the low byte (TBCHxL) is written.
Register Name and Address: TBCH0H — $0057
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Register Name and Address: TBCH0L — $0058
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Register Name and Address: TBCH1H — $005A
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Register Name and Address: TBCH1L — $005B
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Figure 12-9. TIMB Channel Registers (TBCH0H/L–TBCH1H/L)

Section 13. Serial Communications Interface (SCI)
13.1 Contents
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
13.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
13.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
13.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
13.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
13.5 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
13.6 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
13.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . .262
13.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
13.8.1 PTE2/TxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . .263
13.8.2 PTB0/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . .263
13.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
13.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .264
13.9.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
13.9.5 SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
13.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
13.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . .276
Freescale Semiconductor Serial Communications Interface (SCI) 247

Serial Communications Interface (SCI)
13.2 Introduction
This section describes the serial communications interface (SCI) module
which allows high-speed asynchronous communications with peripheral
devices and other microcontroller units (MCUs).
13.3 Features
Features of the SCI module include:
• Full duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• 32 programmable baud rates
• Programmable 8-bit or 9-bit character length
• Separately enabled transmitter and receiver
• Separate receiver and transmitter cpu interrupt requests
• Separate receiver and transmitter
• Programmable transmitter output polarity
• Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
248 Serial Communications Interface (SCI) Freescale Semiconductor

• Interrupt-driven operation with eight interrupt flags:

– Transmitter empty
– Transmission complete
– Receiver full
– Idle receiver input
– Receiver overrun
– Noise error
– Framing error
– Parity error
• Receiver framing error detection
• Hardware parity checking
• 1/16 bit-time noise detection

The SCI allows full-duplex, asynchronous, NRZ serial communication
among the MCU and remote devices, including other MCUs. The
transmitter and receiver of the SCI operate independently, although they
use the same baud rate generator. During normal operation, the CPU
monitors the status of the SCI, writes the data to be transmitted, and
processes received data.
Figure 13-1 shows the structure of the SCI module. Figure 13-2
provides a summary of the input/output (I/O) registers.

INTERNAL BUS
SCI DATA SCI DATA

REGISTER REGISTER
TRANSMITTER
INTERRUPT
INTERRUPT
INTERRUPT
RECEIVER
CONTROL
CONTROL
CONTROL
ERROR
RECEIVE TRANSMIT
PTB0/RxD SHIFT REGISTER SHIFT REGISTER PTB1/TxD
TXINV
SCTIE
R8
TCIE
T8
SCRIE
ILIE
TE
SCTE
RE
TC
RWU
SCRF OR ORIE
SBK
IDLE NF NEIE
FE FEIE
PE PEIE
LOOPS
LOOPS ENSCI
WAKEUP RECEIVE FLAG TRANSMIT

CONTROL CONTROL CONTROL CONTROL
BKF M
ENSCI WAKE
RPF
ILTY
PRE- BAUD RATE PEN
fOP ÷4 SCALER GENERATOR PTY
fOP = F bus frequency
÷ 16 DATA SELECTION
CONTROL
Figure 13-1. SCI Module Block Diagram

Read: LOOP
SCI Control Register 1 ENSCI TXINV M WAKE ILTY PEN PTY
$0038 (SCC1) Write: S
See page 264.
Reset: 0 0 0 0 0 0 0 0
Read:
SCI Control Register 2 SCTIE TCIE SCRIE ILIE TE RE RWU SBK
$0039 (SCC2) Write:
See page 267.
Reset: 0 0 0 0 0 0 0 0
Read: R8 0 0
SCI Control Register 3 T8 ORIE NEIE FEIE PEIE
$003A (SCC3) Write: R R R
See page 270.
Reset: U U 0 0 0 0 0 0

$003B (SCS1) Write: R R R R R R R R
See page 271.
Reset: 1 1 0 0 0 0 0 0

$003C (SCS2) Write: R R R R R R R R
See page 275.
Reset: 0 0 0 0 0 0 0 0
SCI Data Register
$003D (SCDR) Write: T7 T6 T5 T4 T3 T2 T1 T0
See page 276.
Read: 0 0 0
SCI Baud Rate Register SCP1 SCP0 SCR2 SCR1 SCR0
$003E (SCBR) Write: R R R
See page 276.
Reset: 0 0 0 0 0 0 0 0
R = Reserved U = Unaffected
Figure 13-2. SCI I/O Register Summary
13.4.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format

illustrated in Figure 13-3.

8-BIT DATA FORMAT

BIT M IN SCC1 CLEAR POSSIBLE
PARITY
BIT NEXT
START START
BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT
BIT
9-BIT DATA FORMAT

BIT M IN SCC1 SET POSSIBLE
PARITY
BIT NEXT
START START
BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP BIT
BIT
Figure 13-3. SCI Data Formats
13.4.2 Transmitter
Figure 13-4 shows the structure of the SCI transmitter.
13.4.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCC1) determines character length.
When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is
the ninth bit (bit 8).
13.4.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character

out to the PTB1/TxD pin. The SCI data register (SCDR) is the write-only
buffer between the internal data bus and the transmit shift register.
To initiate an SCI transmission:

1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI)
in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable
bit (TE) in SCI control register 2 (SCC2).
3. Clear the SCI transmitter empty bit by first reading SCI status
register 1 (SCS1) and then writing to the SCDR.
4. Repeat step 3 for each subsequent transmission.

At the start of a transmission, transmitter control logic automatically

loads the transmit shift register with a preamble of logic 1s. After the
preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least
significant bit (LSB) position of the transmit shift register. A logic 1 stop
bit goes into the most significant bit (MSB) position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the
SCDR transfers a byte to the transmit shift register. The SCTE bit
indicates that the SCDR can accept new data from the internal data bus.
If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the
SCTE bit generates a transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the

PTB1/TxD pin goes to the idle condition, logic 1. If at any time software
clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and
receiver relinquish control of the port B pins.
13.4.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit
shift register with a break character. A break character contains all logic
0s and has no start, stop, or parity bit. Break character length depends
on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic
continuously loads break characters into the transmit shift register. After
software clears the SBK bit, the shift register finishes transmitting the
last break character and then transmits at least one logic 1. The
automatic logic 1 at the end of a break character guarantees the
recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by

eight or nine logic 0 data bits and a logic 0 where the stop bit should be.

INTERNAL BUS
PRE- BAUD
÷4 ÷ 16 SCI DATA REGISTER
SCALER DIVIDER
fOP
SCP1
11-BIT
START
TRANSMIT
STOP
SCP0
SHIFT REGISTER
SCR1
H 8 7 6 5 4 3 2 1 0 L PTB1/TxD
SCR2
SCR0
MSB
TXINV
LOAD FROM SCDR

PEN PARITY
SHIFT ENABLE
PTY GENERATION
PREAMBLE
BREAK
ALL 0s
ALL 1s
T8
TRANSMITTER
CONTROL LOGIC
TRANSMITTER CPU
INTERRUPT REQUEST
SCTE SBK
SCTE
LOOPS
SCTIE
SCTIE ENSCI
TC
TC TE
TCIE
TCIE
Figure 13-4. SCI Transmitter
Receiving a break character has these effects on SCI registers:
• Sets the framing error bit (FE) in SCS1

• Sets the SCI receiver full bit (SCRF) in SCS1
• Clears the SCI data register (SCDR)
• Clears the R8 bit in SCC3
• Sets the break flag bit (BKF) in SCS2
• May set the overrun (OR), noise flag (NF), parity error (PE), or
reception-in-progress flag (RPF) bits

13.4.2.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit.
Idle character length depends on the M bit in SCC1. The preamble is a
synchronizing idle character that begins every transmission.
If the TE bit is cleared during a transmission, the PTB1/TxD pin becomes

idle after completion of the transmission in progress. Clearing and then
setting the TE bit during a transmission queues an idle character to be
sent after the character currently being transmitted.
NOTE: When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the PTB1/TxD pin. Setting
TE after the stop bit appears on PTB1/TxD causes data previously
written to the SCDR to be lost.
A good time to toggle the TE bit is when the SCTE bit becomes set and
just before writing the next byte to the SCDR.
13.4.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)

reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
See 13.9.1 SCI Control Register 1.
13.4.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the SCI
transmitter:
• SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2
enables the SCTE bit to generate transmitter CPU interrupt
requests.
• Transmission complete (TC) — The TC bit in SCS1 indicates that
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to
generate transmitter CPU interrupt requests.

13.4.3 Receiver
Figure 13-5 shows the structure of the SCI receiver.
INTERNAL BUS
SCR1
SCP1 SCR2 SCI DATA REGISTER
SCP0 SCR0
PRE- BAUD
÷4 ÷ 16
START
SCALER DIVIDER
STOP
11-BIT
fOP RECEIVE SHIFT REGISTER
DATA
PTB0/Rx RECOVERY H 8 7 6 5 4 3 2 1 0 L
ALL 0s
BKF
ALL 1s
MSB
RPF
ERROR CPU INTERRUPT REQUEST
M
CPU INTERRUPT REQUEST
SCRF RWU
WAKE WAKEUP
IDLE
ILTY LOGIC
PEN PARITY R8
PTY CHECKING
IDLE
ILIE
ILIE
SCRF
SCRIE
SCRIE
OR
OR
ORIE
ORIE
NF
NF
NEIE
NEIE
FE
FE
FEIE
FEIE
PE
PE
PEIE
PEIE
Figure 13-5. SCI Receiver Block Diagram

13.4.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCC1) determines character length.
When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the
ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth
bit (bit 7).
13.4.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in

from the PTB0/RxD pin. The SCI data register (SCDR) is the read-only
buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE,
in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt
request.
13.4.3.3 Data Sampling
The receiver samples the PTB0/RxD pin at the RT clock rate. The RT
clock is an internal signal with a frequency 16 times the baud rate. To
adjust for baud rate mismatch, the RT clock is resynchronized at these
times (see Figure 13-6):
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
return a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples return a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.

START BIT LSB

PTB0/RxD
START BIT START BIT DATA

SAMPLES QUALIFICATION VERIFICATION SAMPLING
RT
CLOCK
RT10
RT11
RT12
RT13
RT14
RT15
RT16
RT CLOCK
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT1
RT2
RT3
RT4
STATE
RT CLOCK
RESET
Figure 13-6. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7. Table 13-1 summarizes the results of
the start bit verification samples.
Table 13-1. Start Bit Verification

RT3, RT5, and RT7 Start Bit
Noise Flag
Samples Verification
000 Yes 0
001 Yes 1
010 Yes 1
011 No 0
100 Yes 1
101 No 0
110 No 0
111 No 0
If start bit verification is not successful, the RT clock is reset and a new
search for a start bit begins.

To determine the value of a data bit and to detect noise, recovery logic
takes samples at RT8, RT9, and RT10. Table 13-2 summarizes the
results of the data bit samples.
Table 13-2. Data Bit Recovery
RT8, RT9, and RT10 Data Bit
Noise Flag
Samples Determination
000 0 0
001 0 1
010 0 1
011 1 1
100 0 1
101 1 1
110 1 1
111 1 0
NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If
any or all of the RT8, RT9, and RT10 start bit samples are logic 1s
following a successful start bit verification, the noise flag (NF) is set and
the receiver assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at
RT8, RT9, and RT10. Table 13-3 summarizes the results of the stop bit
samples.
Table 13-3. Stop Bit Recovery
RT8, RT9, and RT10 Framing
Noise Flag
Samples Error Flag
000 1 0
001 1 1
010 1 1
011 0 1
100 1 1
101 0 1
110 0 1
111 0 0

13.4.3.4 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error bit, FE, in
SCS1. The FE flag is set at the same time that the SCRF bit is set. A
break character that has no stop bit also sets the FE bit.
13.4.3.5 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are
disabled.
Depending on the state of the WAKE bit in SCC1, either of two

conditions on the PTB0/RxD pin can bring the receiver out of the standby
state:
• Address mark — An address mark is a logic 1 in the most
significant bit position of a received character. When the WAKE bit
is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI
receiver full bit, SCRF. Software can then compare the character
containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and
processes the characters that follow. If they are not the same,
software can set the RWU bit and put the receiver back into the
standby state.
• Idle input line condition — When the WAKE bit is clear, an idle
character on the PTB0/RxD pin wakes the receiver from the
standby state by clearing the RWU bit. The idle character that
wakes the receiver does not set the receiver idle bit, IDLE, or the
SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines
whether the receiver begins counting logic 1s as idle character bits
after the start bit or after the stop bit.
NOTE: Clearing the WAKE bit after the PTB0/RxD pin has been idle can cause
the receiver to wake up immediately.

13.4.3.6 Receiver Interrupts
These sources can generate CPU interrupt requests from the SCI
receiver:
• SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that
the receive shift register has transferred a character to the SCDR.
SCRF can generate a receiver CPU interrupt request. Setting the
SCI receive interrupt enable bit, SCRIE, in SCC2 enables the
SCRF bit to generate receiver CPU interrupts.
• Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11
consecutive logic 1s shifted in from the PTB0/RxD pin. The idle
line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to
generate CPU interrupt requests.
13.4.3.7 Error Interrupts
These receiver error flags in SCS1 can generate CPU interrupt requests:
• Receiver overrun (OR) — The OR bit indicates that the receive
shift register shifted in a new character before the previous
character was read from the SCDR. The previous character
remains in the SCDR, and the new character is lost. The overrun
interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI
error CPU interrupt requests.
• Noise flag (NF) — The NF bit is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, in SCC3 enables
NF to generate SCI error CPU interrupt requests.
• Framing error (FE) — The FE bit in SCS1 is set when a logic 0
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI
error CPU interrupt requests.
• Parity error (PE) — The PE bit in SCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU
interrupt requests.

13.5 Wait Mode

The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
The SCI module remains active after the execution of a WAIT

instruction. In wait mode the SCI module registers are not accessible by
the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
13.6 Stop Mode

The SCI module is inactive after execution of a STOP instruction. The
STOP instruction does not affect register conditions of the SCI. SCI
operation resumes when the MCU exits stop mode after an external
interrupt.
13.7 SCI During Break Module Interrupts

other modules can be cleared during interrupts generated by the break
module. The BCFE bit in the SIM break flag control register (SBFCR)
enables software to clear status bits during the break state.


I/O Signals
13.8 I/O Signals

Port B shares two of its pins with the SCI module. The two SCI I/O pins
are:
• PTB1/TxD — Transmit data
• PTB0/RxD — Receive data
13.8.1 PTE2/TxD (Transmit Data)
The PTB1/TxD pin is the serial data output from the SCI transmitter. The
SCI shares the PTB1/TxD pin with port B. When the SCI is enabled, the
PTB1/TxD pin is an output regardless of the state of the DDRF1 bit in
data direction register B (DDRB).
13.8.2 PTB0/RxD (Receive Data)
The PTB0/RxD pin is the serial data input to the SCI receiver. The SCI
shares the PTB0/RxD pin with port B. When the SCI is enabled, the
PTB0/RxD pin is an input regardless of the state of the DDRB0 bit in data
direction register B (DDRB).
13.9 I/O Registers

These I/O registers control and monitor SCI operation:
• SCI control register 1 (SCC1)
• SCI status register 1 (SCS1)
• SCI status register 2 (SCS2)
• SCI data register (SCDR)
• SCI baud rate register (SCBR)

13.9.1 SCI Control Register 1
SCI control register 1 (SCC1):

• Enables loop mode operation
• Enables the SCI
• Controls output polarity
• Controls character length
• Controls SCI wake-up method
• Controls idle character detection
• Enables parity function
• Controls parity type
Ad-
$0038
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
LOOPS ENSCI TXINV M WAKE ILTY PEN PTY
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 13-7. SCI Control Register 1 (SCC1)
LOOPS — Loop Mode Select Bit

This read/write bit enables loop mode operation. In loop mode the
PTB0/RxD pin is disconnected from the SCI, and the transmitter
output goes into the receiver input. Both the transmitter and the
receiver must be enabled to use loop mode. Reset clears the LOOPS
bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator.
Clearing ENSCI sets the SCTE and TC bits in SCI status register 1
and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled

I/O Registers
TXINV — Transmit Inversion Bit

This read/write bit reverses the polarity of transmitted data. Reset
clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE: Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
M — Mode (Character Length) Bit

This read/write bit determines whether SCI characters are eight or
nine bits long. (See Table 13-4.) The ninth bit can serve as an extra
stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Condition Bit
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit (MSB) position of a
received character or an idle condition on the PTB0/RxD pin. Reset
clears the WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the SCI starts counting logic 1s
as idle character bits. The counting begins either after the start bit or
after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit may cause false recognition of an idle
character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit.
0 = Idle character bit count begins after start bit.

PEN — Parity Enable Bit

This read/write bit enables the SCI parity function (see Table 13-4).
When enabled, the parity function inserts a parity bit in the most
significant bit position (see Figure 13-3). Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks
for odd parity or even parity (see Table 13-4). Reset clears the PTY
bit.
1 = Odd parity
0 = Even parity
NOTE: Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 13-4. Character Format Selection

Control Bits Character Format
Character
Start Data Stop
M PEN:PTY Parity Length
Bits Bits Bits
(Bits)
0 0X 1 8 None 1 10
1 0X 1 9 None 1 11
0 10 1 7 Even 1 10
0 11 1 7 Odd 1 10
1 10 1 8 Even 1 11
1 11 1 8 Odd 1 11

I/O Registers

• Enables these CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt
requests
– Enables the TC bit to generate transmitter CPU interrupt
requests
– Enables the SCRF bit to generate receiver CPU interrupt
requests
– Enables the IDLE bit to generate receiver CPU interrupt
requests
• Enables the transmitter
• Enables the receiver
• Enables SCI wake up
• Transmits SCI break characters
Ad-
$0039
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
Write:
Reset: 0 0 0 0 0 0 0 0
SCTIE — SCI Transmit Interrupt Enable Bit

This read/write bit enables the SCTE bit to generate SCI transmitter
CPU interrupt requests. Setting the SCTIE bit in SCC3 enables SCTE
CPU interrupt requests. Reset clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt

TCIE — Transmission Complete Interrupt Enable Bit

This read/write bit enables the TC bit to generate SCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver
CPU interrupt requests. Setting the SCRIE bit in SCC3 enables the
SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE
bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU
interrupt requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PTB1/TxD pin. If software clears the TE bit, the transmitter completes
any transmission in progress before the PTB1/TxD returns to the idle
condition (logic 1). Clearing and then setting TE during a transmission
queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RE — Receiver Enable Bit

Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver but does not affect receiver interrupt flag bits.
Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled

I/O Registers
NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RWU — Receiver Wakeup Bit

This read/write bit puts the receiver in a standby state during which
receiver interrupts are disabled. The WAKE bit in SCC1 determines
whether an idle input or an address mark brings the receiver out of the
standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break
character followed by a logic 1. The logic 1 after the break character
guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s
between them. Reset clears the SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit.
Toggling SBK too early causes the SCI to send a break character
instead of a preamble.

• Stores the ninth SCI data bit received and the ninth SCI data bit to
be transmitted
• Enables SCI receiver full (SCRF)
• Enables SCI transmitter empty (SCTE)
• Enables the following interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
– Parity error interrupts

Ad-
$003A
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: R8 0 0
T8 ORIE NEIE FEIE PEIE
Write: R R R
Reset: U U 0 0 0 0 0 0
R = Reserved U = Unaffected
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write
ninth bit (bit 8) of the transmitted character. T8 is loaded into the
transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
generated by the noise error bit, NE. Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled

I/O Registers
FEIE — Receiver Framing Error Interrupt Enable Bit

generated by the framing error bit, FE. Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI receiver CPU interrupt requests
generated by the parity error bit, PE. Reset clears PEIE. See 13.9.4
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
13.9.4 SCI Status Register 1
SCI status register 1 (SCS1) contains flags to signal these conditions:

• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
Ad- $003B
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Reset: 1 1 0 0 0 0 0 0
R = Reserved
Figure 13-10. SCI Status Register 1 (SCS1)

SCTE — SCI Transmitter Empty Bit

This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal
operation, clear the SCTE bit by reading SCS1 with SCTE set and
then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete Bit
This read-only bit is set when the SCTE bit is set, and no data,
preamble, or break character is being transmitted. TC generates an
SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also
set. TC is cleared automatically when data, preamble, or break is
queued and ready to be sent. There may be up to 1.5 transmitter
clocks of latency between queueing data, preamble, and break and
the transmission actually starting. Reset sets the TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. SCRF can generate an SCI
receiver CPU interrupt request. When the SCRIE bit in SCC2 is set,
SCRF generates a CPU interrupt request. In normal operation, clear
the SCRF bit by reading SCS1 with SCRF set and then reading the
SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an SCI error CPU
interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit
by reading SCS1 with IDLE set and then reading the SCDR. After the
receiver is enabled, it must receive a valid character that sets the
SCRF bit before an idle condition can set the IDLE bit. Also, after the

I/O Registers
IDLE bit has been cleared, a valid character must again set the SCRF
bit before an idle condition can set the IDLE bit. Reset clears the IDLE
bit.
1 = Receiver input idle
0 = Receiver input active or idle since the IDLE bit was cleared
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the
SCDR before the receive shift register receives the next character.
The OR bit generates an SCI error CPU interrupt request if the ORIE
bit in SCC3 is also set. The data in the shift register is lost, but the data
already in the SCDR is not affected. Clear the OR bit by reading SCS1
with OR set and then reading the SCDR. Reset clears the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of
SCS1 and SCDR in the flag-clearing sequence. Figure 13-11 shows
the normal flag-clearing sequence and an example of an overrun
caused by a delayed flag-clearing sequence. The delayed read of
SCDR does not clear the OR bit because OR was not set when SCS1
was read. Byte 2 caused the overrun and is lost. The next
flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is
important to know which byte is lost due to an overrun, the
flag-clearing routine can check the OR bit in a second read of SCS1
after reading the data register.
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the
PTB0/RxD pin. NF generates an NF CPU interrupt request if the NEIE
bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then
reading the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected

FE — Receiver Framing Error Bit

This clearable, read-only bit is set when a logic 0 is accepted as the
stop bit. FE generates an SCI error CPU interrupt request if the FEIE
bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
NORMAL FLAG CLEARING SEQUENCE

SCRF = 1
SCRF = 0
SCRF = 1
SCRF = 0
SCRF = 1
SCRF = 0
BYTE 1 BYTE 2 BYTE 3 BYTE 4
READ SCS1 READ SCS1 READ SCS1

SCRF = 1 SCRF = 1 SCRF = 1
OR = 0 OR = 0 OR = 0
READ SCDR READ SCDR READ SCDR

BYTE 1 BYTE 2 BYTE 3
DELAYED FLAG CLEARING SEQUENCE

SCRF = 1
SCRF = 1
SCRF = 0
SCRF = 1
SCRF = 0
OR = 1
OR = 1
OR = 1
OR = 0
BYTE 1 BYTE 2 BYTE 3 BYTE 4
READ SCS1 READ SCS1

SCRF = 1 SCRF = 1
OR = 0 OR = 1
READ SCDR READ SCDR
BYTE 1 BYTE 3
Figure 13-11. Flag Clearing Sequence

I/O Registers
13.9.5 SCI Status Register 2
SCI status register 2 (SCS2) contains flags to signal these conditions:

• Break character detected
• Incoming data
Ad-
$003C
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Figure 13-12. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit

This clearable, read-only bit is set when the SCI detects a break
character on the PTB0/RxD pin. In SCS1, the FE and SCRF bits are
also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request. Clear BKF
by reading SCS2 with BKF set and then reading the SCDR. Once
cleared, BKF can become set again only after logic 1s again appear
on the PTB0/RxD pin followed by another break character. Reset
clears the BKF bit.
1 = Break character detected
0 = No break character detected
RPF —Reception-in-Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the
RT1 time period of the start bit search. RPF does not generate an
interrupt request. RPF is reset after the receiver detects false start bits
(usually from noise or a baud rate mismatch, or when the receiver
detects an idle character. Polling RPF before disabling the SCI
module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress

13.9.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus
and the receive and transmit shift registers. Reset has no effect on data
in the SCI data register.
Ad-
$003D
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Figure 13-13. SCI Data Register (SCDR)
R7/T7:R0/T0 — Receive/Transmit Data Bits

Reading address $003D accesses the read-only received data bits,
R7:R0. Writing to address $003D writes the data to be transmitted,
T7:T0. Reset has no effect on the SCI data register.
13.9.7 SCI Baud Rate Register
The SCI baud rate register (SCBR) selects the baud rate for both the
receiver and the transmitter.
Ad-
$003E
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0
SCP1 SCP0 SCR2 SCR1 SCR0
Write: R R R
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Figure 13-14. SCI Baud Rate Register (SCBR)

I/O Registers
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits

These read/write bits select the baud rate prescaler divisor as shown
in Table 13-5. Reset clears SCP1 and SCP0.
Table 13-5. SCI Baud Rate Prescaling
SCP1:SCP0 Prescaler Divisor (PD)
00 1
01 3
10 4
11 13
SCR2–SCR0 — SCI Baud Rate Select Bits

These read/write bits select the SCI baud rate divisor as shown in
Table 13-6. Reset clears SCR2–SCR0.
Table 13-6. SCI Baud Rate Selection

SCR2:SCR1:SCR0 Baud Rate Divisor (BD)
000 1
001 2
010 4
011 8
100 16
101 32
110 64
111 128
Use this formula to calculate the SCI baud rate:

Baud rate = fOP / 64 x PD x BD
where:
fOP = clock source (fBus)
PD = prescaler divisor
BD = baud rate divisor
Table 13-7 shows the SCI baud rates that can be generated with a
4.00-MHz crystal and the CGM set for an fOP of 8.00 MHz and with a
4.9152-MHz crystal with the CGM set for an an fOP of 7.3728 MHz.

Table 13-7. SCI Baud Rate Selection Examples

Prescaler
SCR2:SCR1: Baud Rate Baud Rate Baud Rate
SCP1:SCP0 Divisor
SCR0 Divisor (BD) (fOP = 7.3728 MHz) (fOP = 8.00 MHz)
(PD)
00 1 000 1 115,200.00 125,000.00
00 1 001 2 57,600.00 62,500.00
00 1 010 4 28,800.00 31,250.00
00 1 011 8 14,400.00 15,625.00
00 1 100 16 7200.00 7812.50
00 1 101 32 3600.00 3906.25
00 1 110 64 1800.00 1953.13
00 1 111 128 900.00 976.56
01 3 000 1 38,400.00 41,666.67
01 3 001 2 19,200.00 20,833.33
01 3 010 4 9600.00 10,416.67
01 3 011 8 4800.00 5208.33
01 3 100 16 2400.00 2604.17
01 3 101 32 1200.00 1302.08
01 3 110 64 600.00 651.04
01 3 111 128 300.00 325.52
10 4 000 1 28,800.00 31,250.00
10 4 001 2 14,400.00 15,625.50
10 4 010 4 7200.00 7812.50
10 4 011 8 3600.00 3906.25
10 4 100 16 1800.00 1953.13
10 4 101 32 900.00 976.56
10 4 110 64 450.00 488.28
10 4 111 128 225.00 244.14
11 13 000 1 8861.54 9615.38
11 13 001 2 4430.77 4807.69
11 13 010 4 2215.38 2403.85
11 13 011 8 1107.69 1201.92
11 13 100 16 553.85 600.96
11 13 101 32 276.92 300.48
11 13 110 64 138.46 150.24
11 13 111 128 69.23 75.12

Section 14. Input/Output (I/O) Ports
14.1 Contents
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
14.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
14.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
14.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . .282
14.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
14.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
14.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . .285
14.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
14.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
14.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . .288
14.2 Introduction
Fourteen bidirectional input-output (I/O) pins, two input pins, and six
output pins form three parallel ports.
When using the 28-pin package versions of the MC68HC908MR8, set

the data direction register bits in DDRA such that bits 6, 5, and 4 are
written to a logic 1 (along with any other output bits on PORTA). Setting
PORTA’s data direction register bits 6, 5, and 4 will terminate the input
buffers on that port.
NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. (PWM6–PWM1 pins require no termination). Although the I/O ports
do not require termination for proper operation, termination reduces
excess current consumption and the possibility of electrostatic damage.
Freescale Semiconductor Input/Output (I/O) Ports 279

Input/Output (I/O) Ports
Read:
Port A Data Register PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
$0000 (PTA) Write:
See page 281.
Read:
Port B Data Register PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001 (PTB) Write:
See page 284.
Read:
Port C Data Register PTC1 PTC0
$0002 (PTC) Write:
See page 287.
$0003 Unimplemented
Read: DDRA DDRA DDRA DDRA DDRA DDRA DDRA

Data Direction Register A
$0004 (DDRA) Write: 6 5 4 3 2 1 0
See page 282.
Reset: 0 0 0 0 0 0 0 0
Read: DDRB DDRB DDRB DDRB DDRB DDRB DDRB

Data Direction Register B
$0005 (DDRB) Write: 6 5 4 3 2 1 0
See page 284.
Reset: 0 0 0 0 0 0 0 0
Read: DDRC DDRC

Data Direction Register C
$0006 (DDRC) Write: 1 0
See page 287.
Reset: U U U U U U 0 0
= Unimple- = Reserved = Unaffected

R U
mented
Figure 14-1. I/O Port Register Summary
280 Input/Output (I/O) Ports Freescale Semiconductor

Port A
14.3 Port A
Port A is a 7-bit, general-purpose, bidirectional I/O port.
14.3.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the eight
port A pins.
Ad-
$0000
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
Write:
= Unimplemented
Figure 14-2. Port A Data Register (PTA)
PTA[6:0] — Port A Data Bits

These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.

14.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is

an input or an output. Writing a logic 1 to a DDRA bit enables the output
buffer for the corresponding port A pin; a logic 0 disables the output
buffer.
Ad-
$0004
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 14-3. Data Direction Register A (DDRA)
DDRA[6:0] — Data Direction Register A Bits

These read/write bits control port A data direction. Reset clears
DDRA[6:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 14-4 shows the port A I/O logic.

Port A
READ DDRA ($0004)
WRITE DDRA ($0004)

DDRAx
INTERNAL DATA BUS

RESET
WRITE PTA ($0000)

PTAx PTAx
READ PTA ($0000)
Figure 14-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 14-1 summarizes
the operation of the port A pins.
Table 14-1. Port A Pin Functions

Accesses
DDRA PTA I/O Pin Accesses to PTA
to DDRA
Bit Bit Mode
Read/Write Read Write
0 X(1) Input, Hi-Z(2) DDRA[6:0] Pin PTA[6:0](3)
1 X Output DDRA[6:0] PTA[6:0] PTA[6:0]

1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.

14.4 Port B
Port B is a 7-bit general-purpose bidirectional I/O port that shares its pins
with the serial communications interface (SCI) module.
14.4.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight
port B pins.
Ad-
$0001
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
= Unimplemented
Figure 14-5. Port B Data Register (PTB)
PTB[6:0] — Port B Data Bits

These read/write bits are software-programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.

Port B
14.4.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is

an input or an output. Writing a logic 1 to a DDRB bit enables the output
buffer for the corresponding port B pin; a logic 0 disables the output
buffer.
Ad-
$0005
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 14-6. Data Direction Register B (DDRB)
DDRB[6:0] — Data Direction Register B Bits

These read/write bits control port B data direction. Reset clears
DDRB[6:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 14-7 shows the port B I/O logic.

READ DDRB ($0005)
WRITE DDRB ($0005)

DDRBx
INTERNAL DATA BUS

RESET
WRITE PTB ($0001)

PTBx PTBx
READ PTB ($0001)
Figure 14-7. Port B I/O Circuit
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the operation of the port B pins.
Table 14-2. Port B Pin Functions

Accesses
DDRB PTB Accesses to PTB
I/O Pin Mode to DDRB
Bit Bit
Read/Write Read Write
0 X(1) Input, Hi-Z(2) DDRB[6:0] Pin PTB[6:0](3)
1 X Output DDRB[6:0] PTB[6:0] PTB[6:0]

1. X = don’t care
2. Hi-Z = high impedance
14.5 Port C
Port C is a 2-bit special-purpose I/O port sharing its pins with the pulse
width modulator for motor control module (PMC) FAULT input pins.
These two pins mirror the state of FAULT1 and FAULT4 pins. Level
changes on these input pins will be interpreted as fault conditions.
The port C data register contains a data latch for each of the two port
pins.

Port C
Port C bit 1 is not used on the 28-pin packages. For that reason, a
pull-down resistor is connected to VSS to prevent a false fault input on
FAULT4.
NOTE: PORTC has the capability of being used as an output port. When either
pin of PORTC is set as an output, by setting its respective PORTC data
direction register bit, the respective fault pin logic is disconnected from
that pin and the fault input will be defaulted to normal non-fault condition
to facilitate the use of PORTC as an output pin and not interfere with the
PWM generator. To regain the fault capability for the respective fault
input pin, clear the PORTC data direction register bit for that pin.
14.5.1 Port C Data Register
The port C data register (PTC) contains a data latch for each of the two
port C pins.
Ad-
$0002
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PTC1 PTC0
Write:
= Unimplemented
Figure 14-8. Port C Data Register (PTC)
PTC[1:0] — Port C Data Bits

These read/write bits are software programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data.

14.5.2 Data Direction Register C
Data direction register C (DDRC) determines whether each port C pin is

an input or an output. Writing a logic 1 to a DDRC bit enables the output
buffer for the corresponding port C pin; a logic 0 disables the output
buffer.
Ad-
$0006
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
DDRC1 DDRC0
Write:
Reset: U U U U U U 0 0
= Unimplemented U = Unaffected
Figure 14-9. Data Direction Register C (DDRC)
DDRC[1:0] — Data Direction Register C Bits

These read/write bits control port C data direction. Reset clears
DDRC[1:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 14-10 shows the port C I/O logic.

Port C
READ DDRC ($0006)
WRITE DDRC ($0006)

DDRCx
INTERNAL DATA BUS

RESET
WRITE PTC ($0002)

PTCx PTCx
READ PTC ($0002)
Figure 14-10. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx
data latch. When bit DDRCx is a logic 0, reading address $0002 reads
the operation of the port C pins.
Table 14-3. Port C Pin Functions
DDRC PTC Accesses to DDRC Accesses to PTC

I/O Pin Mode
Bit Bit Read/Write Read Write
0 X(1) Input, Hi-Z(2) DDRC[1:0] Pin PTC[1:0](3)
1 X Output DDRC[1:0] PTC[1:0] PTC[1:0]

1. X = don’t care
2. Hi-Z = high impedance on PTC0 and a pull-down RPD on PTC1


Section 15. Computer Operating Properly (COP)
15.1 Contents
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
15.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
15.4.2 COPCTL Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
15.4.3 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
15.4.4 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
15.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
15.4.6 COP Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
15.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
15.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
15.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
15.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
15.10 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . .295
15.2 Introduction
This section describes the computer operating properly module (COP,
version B), a free-running counter that generates a reset if allowed to
overflow. The COP module helps software recover from runaway code.
Prevent a COP reset by periodically clearing the COP counter.
Freescale Semiconductor Computer Operating Properly (COP) 291

Computer Operating Properly (COP)

Figure 15-1 shows the structure of the COP module.
SIM
CGMXCLK 13-BIT SIM COUNTER SIM RESET CIRCUIT
SIM RESET STATUS REGISTER
CLEAR ALL BITS
CLEAR BITS 12–4

INTERNAL RESET SOURCES(1)
RESET VECTOR FETCH
COPCTL WRITE
COP MODULE
6-BIT COP COUNTER

COPD (FROM CONFIG)
RESET CLEAR
COPCTL WRITE COP COUNTER
Note: See 7.4.2 Active Resets from Internal Sources.
Figure 15-1. COP Block Diagram
Read
Low byte of reset vector
:
COP Control Register
Write:
$FFFF (COPCTL) Clear COP counter
See page 294.
Reset
Unaffected by reset
:
Figure 15-2. COP I/O Register Summary
292 Computer Operating Properly (COP) Freescale Semiconductor

I/O Signals
The COP counter is a free-running, 6-bit counter preceded by the 13-bit

system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
218–24 CGMXCLK cycles. With a 4.9152-MHz crystal, the COP timeout
period is 53.3 ms. Writing any value to location $FFFF before overflow
occurs clears the COP counter and prevents reset.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR) (see 7.7.4 SIM Reset
Status Register).
NOTE: Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
15.4 I/O Signals

This subsection describes the signals shown in Figure 15-1.
15.4.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency

is equal to the crystal frequency.
15.4.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 15.5 COP
Control Register) clears the COP counter and clears bits 12–4 of the
SIM counter. Reading the COP control register returns the reset vector.
15.4.3 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096
CGMXCLK cycles after power-up.

15.4.4 Internal Reset
An internal reset clears the SIM counter and the COP counter.
15.4.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the SIM counter.
15.4.6 COP Disable
The COP disable (COPD) signal reflects the state of the COP disable bit
(COPD) in the configuration register (CONFIG). See 5.4 CONFIG Bits.
15.5 COP Control Register

The COP control register (COPCTL) is located at address $FFFF and
overlaps the reset vector. Writing any value to $FFFF clears the COP
counter and starts a new timeout period. Reading location $FFFF
returns the low byte of the reset vector.
Ad-
$FFFF
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: Low byte of reset vector
Write: Clear COP counter
Figure 15-3. COP Control Register (COPCTL)
15.6 Interrupts
The COP does not generate CPU interrupt requests.

Monitor Mode
15.7 Monitor Mode

The COP is disabled in monitor mode when VDD + VHI is present on the
IRQ pin or on the RST pin.
15.8 Wait Mode

The WAIT instruction puts the MCU in low power-consumption standby
mode.
The COP continues to operate during wait mode.
15.9 Stop Mode

Stop mode turns off the COP prescaler clock. Service the COP
immediately before entering or after exiting stop mode to ensure a full
COP timeout period after entering or exiting stop mode.
15.10 COP Module During Break Mode

The COP is disabled during a break interrupt when VDD + VHI is present
on the RST pin.


Section 16. External Interrupt (IRQ)
16.1 Contents
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
16.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
16.5 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
16.6 IRQ Module During Wait Mode . . . . . . . . . . . . . . . . . . . . . .302
16.7 IRQ Module During Stop Mode . . . . . . . . . . . . . . . . . . . . . .302
16.8 IRQ Module During Break Mode . . . . . . . . . . . . . . . . . . . . .302
16.9 IRQ Status and Control Register. . . . . . . . . . . . . . . . . . . . .303
16.2 Introduction
This section describes the external interrupt module, which supports
external interrupt functions.
16.3 Features
Features of the IRQ module include:
• A dedicated external interrupt pin, IRQ
• Hysteresis buffers
Freescale Semiconductor External Interrupt (IRQ) 297

External Interrupt (IRQ)

A logic 0 applied to any of the external interrupt pins can latch a CPU
interrupt request. Figure 16-1 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector
fetch.
• Software clear — Software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (ISCR). Writing a logic 1 to the ACK1 bit clears the
IRQ latch.
• Reset — A reset automatically clears both interrupt latches.
ACK1
VDD
CLR
D Q SYNCHRO- IRQ
NIZER INTERRUPT
IRQ CK
REQUEST
IRQ
LATCH
IMASK1
MODE1
HIGH- TO MODE
VOLTAGE SELECT
DETECT LOGIC
Figure 16-1. IRQ Module Block Diagram

Read: 0 0 0 0 0 IMASK MODE
IRQ Status/Control Register IRQF
$003F (ISCR) Write: R R R R ACK1 1 1
See page 303.
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Figure 16-2. IRQ I/O Register Summary
298 External Interrupt (IRQ) Freescale Semiconductor

The external interrupt pins are falling-edge-triggered and are

software-configurable to be both falling-edge and low-level-triggered.
The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ
pin.
When the interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level-triggered, the

interrupt latch remains set until both of these occur:
• Vector fetch, software clear, or reset
• Return of the interrupt pin to logic 1
The vector fetch or software clear can occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending.
When set, the IMASK1 bit in the ISCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK bit is clear.
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
See Figure 16-3.

FROM RESET
YES
I BIT SET?
NO
YES
INTERRUPT?
NO
STACK CPU REGISTERS

SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI YES
INSTRUCTION?
NO
RTI YES
INSTRUCTION? UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 16-3. IRQ Interrupt Flowchart

IRQ Pin
16.5 IRQ Pin

A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch.
A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE1 bit is set, the IRQ pin is both falling-edge-sensitive and
low-level-sensitive. With MODE1 set, both of these actions must occur
to clear the IRQ latch:
• Vector fetch, software clear, or reset — A vector fetch generates
an interrupt acknowledge signal to clear the latch. Software can
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK1 bit in the interrupt status and control register (ISCR).
The ACK1 bit is useful in applications that poll the IRQ pin and
require software to clear the IRQ latch. Writing to the ACK1 bit can
also prevent spurious interrupts due to noise. Setting ACK1 does
not affect subsequent transitions on the IRQ pin. A falling edge
that occurs after writing to the ACK1 bit latches another interrupt
request. If the IRQ mask bit, IMASK1, is clear, the CPU loads the
program counter with the vector address at locations $FFFA and
$FFFB.
• Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic
0, the IRQ latch remains set.
The vector fetch or software clear and the return of the IRQ pin to logic
1 can occur in any order. The interrupt request remains pending as long
as the IRQ pin is at logic 0.
If the MODE1 bit is clear, the IRQ pin is falling-edge-sensitive only. With
MODE1 clear, a vector fetch or software clear immediately clears the
IRQ latch.
Use the branch if IRQ pin high (BIH) or branch if IRQ pin low (BIL)
instruction to read the logic level on the IRQ pin.
NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.

16.6 IRQ Module During Wait Mode

The IRQ module remains active in wait mode. Clearing the IMASK1 bit
in the IRQ status and control register (ISCR) enables IRQ central
processor unit (CPU) interrupt requests to bring the microcontroller unit
(MCU) out of wait mode.
16.7 IRQ Module During Stop Mode

The IRQ module remains active in stop mode. Clearing the IMASK1 bit
in the IRQ status and control register (ISCR) enables IRQ CPU interrupt
requests to bring the MCU out of stop mode.
16.8 IRQ Module During Break Mode

The system integration (SIM) module controls whether the IRQ interrupt
latch can be cleared during the break state. The BCFE bit in the SIM
break flag control register (SBFCR) enables software to clear the latches
during the break state. See 7.7.5 SIM Break Flag Control Register.
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
To protect the latches during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK1 bit in the
IRQ status and control register during the break state has no effect on
the IRQ latches. See 16.9 IRQ Status and Control Register.

IRQ Status and Control Register
16.9 IRQ Status and Control Register

The IRQ status and control register (ISCR) has these functions:
• Clears the IRQ interrupt latch
• Masks IRQ interrupt requests
• Controls triggering sensitivity of the IRQ interrupt pin
Ad-
$003F
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0
IRQF IMASK1 MODE1
Write: R R R R ACK1
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Figure 16-4. IRQ Status and Control Register (ISCR)
ACK1 — IRQ Interrupt Request Acknowledge Bit

Writing a logic 1 to this write-only bit clears the IRQ latch. ACK1
always reads as logic 0. Reset clears ACK1.
IMASK1 — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK1.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE1 — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE1.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
IRQF — IRQ Flag
This read-only bit acts as a status flag, indicating an IRQ event
occurred.
1 = External IRQ event occurred.
0 = External IRQ event did not occur.


Section 17. Low-Voltage Inhibit (LVI)
17.1 Contents
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
17.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
17.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
17.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . .307
17.4.3 False Reset Protection. . . . . . . . . . . . . . . . . . . . . . . . . . .307
17.4.4 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
17.5 LVI Status and Control Register . . . . . . . . . . . . . . . . . . . . .308
17.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
17.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
17.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
17.2 Introduction
This section describes the low-voltage inhibit (LVI) module, which
monitors the voltage on the VDD pin and can force a reset when the VDD
voltage falls to the LVI trip voltage.
17.3 Features
Features of the LVI module include:
• Programmable LVI reset
• Programmable power consumption
• Digital filtering of VDD pin level
• Selectable LVI trip voltage
Freescale Semiconductor Low-Voltage Inhibit (LVI) 305

Low-Voltage Inhibit (LVI)

Figure 17-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator.
The LVI power bit, LVIPWR, enables the LVI to monitor VDD voltage. The
LVI reset bit, LVIRST, enables the LVI module to generate a reset when
VDD falls below a voltage, VLVRX, and remains at or below that level for
nine or more consecutive CGMXCLK.
• VLVRX and VLVHX are determined by the TRPSEL bit in the LVI
status and control register (LVISCR). See Figure 17-2.
• LVIPWR and LVIRST are in the configuration (CONFIG) register.
See 5.4 CONFIG Bits.
Once an LVI reset occurs, the MCU remains in reset until VDD rises
above a voltage, VLVRX + VLVHX. VDD must be above VLVRX + VLVHX for
only one central processor unit (CPU) cycle to bring the microcontroller
unit (MCU) out of reset. See 7.4.2.5 Low-Voltage Inhibit (LVI) Reset.
The output of the comparator controls the state of the LVIOUT flag in the
LVISCR.
NOTE: An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
VDD
LVIPWR
FROM CONFIG
CPU CLOCK FROM CONFIG

LVIRST
LOW VDD VDD > LVITRIP = 0 VDD LVI RESET
DETECTOR VDD < LVITRIP = 1 DIGITAL FILTER
TRPSEL
FROM LVISCR ANLGTRIP LVIOUT
Figure 17-1. LVI Module Block Diagram
306 Low-Voltage Inhibit (LVI) Freescale Semiconductor


Read LVI-
0 0 0 0 0 0
: OUT TRPS-
LVI Status and Control Regis-
ter Write EL
$FE0F R R R R R R R
(LVISCR) :
See page 308.
Re-
0 0 0 0 0 0 0 0
set:
R = Reserved
Figure 17-2. LVI I/O Register Summary
17.4.1 Polled LVI Operation
In applications that can operate at VDD levels below VLVRX, software can
monitor VDD by polling the LVIOUT bit. In the configuration register, the
LVIPWR bit must be at logic 1 to enable the LVI module, and the LVIRST
bit must be at logic 0 to disable LVI resets. TRPSEL in the LVISCR
selects VLVRX. See 5.4 CONFIG Bits.
17.4.2 Forced Reset Operation
In applications that require VDD to remain above VLVRX, enabling LVI

resets allows the LVI module to reset the MCU when VDD falls to the
VLVRX level and remains at or below that level for nine or more
consecutive CPU cycles. In the CONFIG register, the LVIPWR and
LVIRST bits must be at logic 1 to enable the LVI module and to enable
LVI resets. TRPSEL in the LVISCR selects VLVRX.
17.4.3 False Reset Protection
The VDD pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU, VDD must
remain at or below VLVRX for nine or more consecutive CPU cycles. VDD
must be above VLVRX + VLVHX for only one CPU cycle to bring the MCU
out of reset. TRPSEL in the LVISCR selects VLVRX + VLVHX.

17.4.4 LVI Trip Selection
The TRPSEL bit allows the user to choose between 5 percent and
10 percent tolerance when monitoring the supply voltage. The
10 percent option is enabled out of reset. Writing a logic 1 to TRPSEL
will enable the 5 percent option.
NOTE: The MCU is guaranteed to operate at a minimum supply voltage. The trip
point (VLVR1 or VLVR2) may be lower than this.
17.5 LVI Status and Control Register

The LVI status register flags VDD voltages below the VLVRX level.
Ad-
$FE0F
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: LVIOUT 0 TRPS- 0 0 0 0 0
Write: R R EL R R R R R
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Figure 17-3. LVI Status and Control Register (LVISCR)
LVIOUT — LVI Output Bit

This read-only flag becomes set when the VDD voltage falls below the
VLVRX voltage for 32 to 40 CGMXCLK cycles. See Table 17-1. Reset
clears the LVIOUT bit.
Table 17-1. LVIOUT Bit Indication

VDD
LVIOUT
At level: For number of CGMXCLK cycles:
VDD > VLVRX + VLVHX Any 0
VDD < VLVRX < 32 CGMXCLK CYCLES 0
VDD < VLVRX Between 32 and 40 CGMXCLK cycles 0 or 1
VDD < VLVRX > 40 CGMXCLK cycles 1

LVI Interrupts
Table 17-1. LVIOUT Bit Indication

VDD
LVIOUT
At level: For number of CGMXCLK cycles:
VLVRX < VDD < VLVRX + VLVHX Any Previous value
TRPSEL — LVI Trip Select Bit

This bit selects the LVI trip point. Reset clears this bit.
1 = 5 percent tolerance. The trip point and recovery point are
determined by VLVR1 and VLVH1 respectively.
0 = 10 percent tolerance. The trip point and recovery point are
determined by VLVR2 and VLVH2 respectively.
NOTE: If LVIPWR and LVIRST are at logic 1, note that when changing the
tolerance, LVI reset will be generated if the supply voltage is below the
trip point.
17.6 LVI Interrupts

The LVI module does not generate interrupt requests.
17.7 Wait Mode

The WAIT instruction puts the microcontroller unit (MCU) in low
power-consumption standby mode.
With the LVIPWR bit in the configuration register programmed to logic 1,

the LVI module is active after a WAIT instruction.
With the LVIRST bit in the configuration register programmed to logic 1,

the LVI module can generate a reset and bring the MCU out of wait
mode.
17.8 Stop Mode

The STOP instruction puts the MCU in low power-consumption standby
mode.

With the LVIPWR bit in the configuration register programmed to logic 1,

the LVI module is active after a STOP instruction.
With the LVIRST bit in the configuration register programmed to logic 1,

the LVI module can generate a reset and bring the MCU out of stop
mode.

Section 18. Analog-to-Digital Converter (ADC)
18.1 Contents
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
18.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
18.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
18.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
18.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
18.4.4 Continuous Conversion. . . . . . . . . . . . . . . . . . . . . . . . . .315
18.4.5 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
18.4.6 Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
18.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
18.6 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
18.7 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
18.8.1 ADC Voltage Reference Pin (VREFH) . . . . . . . . . . . . . . . .317
18.8.2 ADC Voltage In (ADVIN). . . . . . . . . . . . . . . . . . . . . . . . . .318
18.8.3 ADC External Connection . . . . . . . . . . . . . . . . . . . . . . . .318
18.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
18.9.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . .319
18.9.2 ADC Data Register High . . . . . . . . . . . . . . . . . . . . . . . . .322
18.9.3 ADC Data Register Low . . . . . . . . . . . . . . . . . . . . . . . . . .323
18.9.4 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
Freescale Semiconductor Analog-to-Digital Converter (ADC) 311

Analog-to-Digital Converter (ADC)
18.2 Introduction
This section describes the 10-bit analog-to-digital converter (ADC).
For further information regarding analog-to-digital converters on

Freescale microcontrollers, please consult the HC08 ADC Reference
Manual, ADCRM/AD.
18.3 Features
Features of the ADC module include:
• Four to seven channels with multiplexed input
• Linear successive approximation
• 10-bit resolution, 8-bit accuracy
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock
• Left or right justified result.
• Left justified sign data mode
• High impedance buffered ADC input

Depending on the package option, up to seven ADC channels are
available for sampling external sources at pins PTA6/ATD6:PT00/ATD0.
To achieve the best possible accuracy, these pins are implemented as
input-only pins when the analog-to-digital (A/D) feature is enabled. An
analog multiplexer allows the single ADC to select one of the seven ADC
channels as ADC voltage IN (ADCVIN). ADCVIN is converted by the
successive approximation algorithm. When the conversion is completed,
the ADC places the result in the ADC data register (ADRH and ADRL)
and sets a flag or generates an interrupt. See Figure 18-1.
312 Analog-to-Digital Converter (ADC) Freescale Semiconductor

INTERNAL
DATA BUS
PTAx
ADC CHANNEL X
READ PTA
DISABLE
ADC DATA REGISTERS
CONVERSION ADC VOLTAGE IN

ADC COMPLETE ADVIN CHANNEL
INTERRUPT ADC ADCH6:ADCH0
INTERRUPT LOGIC SELECT
AIEN
ADC CLOCK
CGMXCLK
CLOCK
GENERATOR
fOP
ADIV[2:0] ADICLK
Figure 18-1. ADC Block Diagram
18.4.1 ADC Port I/O Pins
PTA6/ATD6:PTA0/ATD6 are general-purpose input/output (I/O) pins

that are shared with the ADC channels.
The channel select bits define which ADC channel/port pin will be used
as the input signal. The ADC overrides the port logic when that port is
selected by the ADC multiplexer. The remaining ADC channels/port pins
are controlled by the port logic and can be used as general-purpose
input/output (I/O) pins. Writes to the port register or data direction
register (DDR) will not have any effect on the port pin that is selected by
the ADC. Read of a port pin which is in use by the ADC will return a
logic 0.

18.4.2 Voltage Conversion
When the input voltage to the ADC equals VREFH, the ADC converts the
signal to $3FF (full scale). If the input voltage equals VSS, the ADC
converts it to $000. Input voltages between VREFH and VREFL are
straight-line linear conversions. All other input voltages will result in
$3FF if greater than VREFH and $000 if less than VSS.
NOTE: Input voltage should not exceed the analog supply voltages.
18.4.3 Conversion Time
Conversion starts after a write to the ADC status and control register
(ADSCR). A conversion is between 16 and 17 ADC clock cycles,
therefore:
16 to 17 ADC cycles
Conversion time =
ADC frequency
Number of bus cycles = conversion time x bus frequency
The ADC conversion time is determined by the clock source chosen and
the divide ratio selected. The clock source is either the bus clock or
CGMXCLK and is selectable by ADICLK located in the ADC clock
register. For example, if CGMXCLK is 4 MHz and is selected as the ADC
input clock source, the ADC input clock /4 prescale is selected:
16 to 17 ADC cycles
Conversion time = = 16 to 17 µs
4 MHz/4
NOTE: The ADC frequency must be between fADIC minimum and fADIC
maximum to meet A/D specifications.
Since an ADC cycle may be comprised of several bus cycles (four in the
prior example) and the start of a conversion is initiated by a bus cycle
write to the ADSCR, from zero to four additional bus cycles may occur
before the start of the initial ADC cycle. This results in a fractional ADC
cycle and is represented as the 17th cycle.

18.4.4 Continuous Conversion
In the continuous conversion mode, the ADC data registers (ADRH and
ADRL) will be filled with new data after each conversion. Data from the
previous conversion will be overwritten whether that data has been read
or not. Conversions will continue until the ADCO bit is cleared. The
COCO bit is set after the first conversion and will stay set for the next
several conversions until the next write of the ADC status and control
register or the next read of the ADC data register.
18.4.5 Result Justification
The conversion result may be formatted in four different ways:
1. Left justified
2. Right justified
3. Left justified sign data mode
4. 8-bit truncation mode
All four of these modes are controlled using MODE0 and MODE1 bits
located in the ADC clock register (ADCLK).
Left justification will place the eight most significant bits (MSB) in the
corresponding ADC data register high, ADRH. This may be useful if the
result is to be treated as an 8-bit result where the two least significant
bits (LSB), located in the ADC data register low, ADRL, can be ignored.
However, ADRL must be read after ADRH or else the interlocking will
prevent all new conversions from being stored.
Right justification will place only the two MSBs in the corresponding ADC
data register high, ADRH, and the eight LSBs in ADC data register low,
ADRL. This mode of operation is typically used when a 10-bit unsigned
result is desired.
Left justified sign data mode is similar to left justified mode with one
exception. The MSB of the 10-bit result, AD9 located in ADRH, is
complemented. This mode of operation is useful when a result,
represented as a signed magnitude from mid-scale, is needed.
Finally, 8-bit truncation mode will place the eight MSBs in ADC data
register low, ADRL. The two LSBs are dropped. This mode of operation

is used when compatibility with 8-bit ADC designs are required. No

interlocking between ADRH and ADRL is present.
NOTE: Quantization error is affected when only the most significant eight bits
are used as a result. See Figure 18-2.
8-BIT 10-BIT
RESULT RESULT IDEAL8-BIT CHARACTERISTIC
WITH QUANTIZATION = ±1/2
003 10-BIT TRUNCATED
TO 8-BIT RESULT
00B
00A
IDEAL 10-BIT CHARACTERISTIC
009 WITH QUANTIZATION = ±1/2
002 008
007
006
005
001 004
003 WHEN TRUNCATION IS USED,

ERROR FROM IDEAL 8 BIT = 3/8 LSB
002 DUE TO NON-IDEAL QUANTIZATION.
001
000 000
1/2 2 1/2 4 1/2 6 1/2 8 1/2 INPUT VOLTAGE
1 1/2 3 1/2 5 1/2 7 1/2 9 1/2 REPRESENTED AS 10-BIT
INPUT VOLTAGE
1/2 1 1/2 2 1/2 REPRESENTED AS 8-BIT
Figure 18-2. 8-Bit Truncation Mode Error
18.4.6 Monotonicity
The conversion process is monotonic and has no missing codes.
18.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit is at logic 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.

Wait Mode
18.6 Wait Mode

The WAIT instruction can put the MCU in low power-consumption
standby mode.
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting ADCH[4:0] in the ADC status and control
register before executing the WAIT instruction.
18.7 Stop Mode

The STOP instruction can put the MCU in low power-consumption
standby mode.
The ADC module becomes inactive after the execution of a STOP

instruction. Any pending conversion is aborted. ADC conversions
resume when the MCU exits stop mode after an external interrupt. Allow
one conversion cycle to stabilize the analog circuitry after exiting stop
mode.
18.8 I/O Signals

The ADC module has seven input signals that are shared with port A.
18.8.1 ADC Voltage Reference Pin (VREFH)
VREFH is the power supply for setting the reference voltage. Connect the
VREFH pin to the same voltage potential as VDDA. There will be a finite
current associated with VREFH.
NOTE: Route VREFH carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.

18.8.2 ADC Voltage In (ADVIN)
ADVIN is the input voltage signal from one of the seven ADC channels
to the ADC module.
18.8.3 ADC External Connection
18.8.3.1 VREFH
Both ac and dc current are drawn through VREFH. The ac current is in the
form of current spikes required to supply charge to the capacitor array at
each successive approximation step. The dc current flows through the
internal resistor string. The best external component to meet both these
current demands is a capacitor in the 0.01 µF to 1 µF range with good
high-frequency characteristics. This capacitor is connected between
VREFH and VSS and must be placed as close as possible to the package
pins. Resistance in the path is not recommended because the dc current
will cause a voltage drop which could result in conversion errors.
18.8.3.2 ANx
Empirical data shows that capacitors from the analog inputs to VRL
improve ADC performance. 0.01 µF and 0.1 µF capacitors with good
high-frequency characteristics are sufficient. These capacitors must be
placed as close as possible to the package pins.
18.8.3.3 Grounding
In cases where separate power supplies are used for analog and digital
power, the ground connection between these supplies should be at the
VSS pin. This should be the only ground connection between these
supplies if possible. The VSS pin makes a good single-point ground
location.

I/O Registers
18.9 I/O Registers

These I/O registers control and monitor operation of the ADC:
• ADC status and control register (ADSCR)
• ADC data registers (ADRH and ARDL)
• ADC control register (ADCR)
• ADC clock register (ADCLK)
18.9.1 ADC Status and Control Register
These paragraphs describe the function of the ADC status and control
register (ADSCR). Writing ADSCR aborts the current conversion and
initiates a new conversion.
Ad-
$0040
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write:
Reset: 0 0 0 1 1 1 1 1
Figure 18-3. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit

When AIEN bit is a logic 0, the COCO is a read-only bit which is set
each time a conversion is completed except in the continuous
conversion mode where it is set after the first conversion. This bit is
cleared whenever the ADC status and control register is written or
whenever the ADC data register is read.
If AIEN bit is a logic 1, the COCO is a read/write bit which selects the
CPU to service the ADC interrupt request. Reset clears this bit.
1 = Conversion completed (AIEN = 0) interrupt (AIEN = 1)
0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN = 1)

AIEN — ADC Interrupt Enable Bit

When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the
ADR register at the end of each conversion. Only one conversion is
allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field
which is used to select one of the ADC channels detailed in Table
18-1. Take care to prevent switching noise from corrupting the analog
signal when simultaneously using a port pin as both an analog and
digital input.
The ADC subsystem is turned off when the channel select bits are all
set to 1. This feature allows for reduced power consumption for the
MCU when the ADC is not used.
NOTE: Recovery from the disabled state requires one conversion cycle to
stabilize.
The voltage levels supplied from internal reference nodes as specified in

Table 18-1 are used to verify the operation of the ADC converter both in
production test and for user applications.

I/O Registers
Table 18-1. Mux Channel Select

ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input select
0 0 0 0 0 PTA0
0 0 0 0 1 PTA1
0 0 0 1 0 PTA2
0 0 0 1 1 PTA3
0 0 1 0 0 PTA4
0 0 1 0 1 PTA5
0 0 1 1 0 PTA6
0 0 1 1 1 Unused*
0 1 0 0 0 Unused*
0 1 0 0 1 Unused*
0 1 0 1 0 Unused*
0 1 0 1 1 Ø
0 1 1 0 0 Ø
0 1 1 0 1 Ø
0 1 1 1 0 Ø
0 1 1 1 1 Ø
1 0 0 0 0 Ø
1 1 0 1 0 Unused*
1 1 0 1 1 Reserved**
1 1 1 0 0 Unused*
1 1 1 0 1 VREFH
1 1 1 1 0 VSS
1 1 1 1 1 ADC power off

* If any unused channels are selected, the resulting ADC conversion will be unknown.
** Used for factory testing.

18.9.2 ADC Data Register High
In left justified mode, this 8-bit result register holds the eight MSBs of the
10-bit result. This register is updated each time an ADC single channel
conversion completes. Reading ADRH latches the contents of ADRL
until ADRL is read. Until ADRL is read, all subsequent ADC results will
be lost.
Ad-
$0041
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Reset: Unaffected by Reset
R = Reserved
Figure 18-4. ADC Data Register High (ADRH)

Left Justified Mode
In right justified mode, this 8-bit result register holds the two MSBs of the
10-bit result. All other bits read as 0. This register is updated each time
a single channel ADC conversion completes. Reading ADRH latches the
contents of ADRL until ADRL is read. Until ADRL is read, all subsequent
ADC results will be lost.
Ad-
$0041
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0 0 AD9 AD8
R = Reserved
Figure 18-5. ADC Data Register High (ADRH)

Right Justified Mode

I/O Registers
18.9.3 ADC Data Register Low
In left justified mode, this 8-bit result register holds the two LSBs of the
10-bit result. All other bits read as 0. This register is updated each time
a single channel ADC conversion completes. Reading ADRH latches the
contents of ADRL until ADRL is read. Until ADRL is read all subsequent
ADC results will be lost.
Ad-
$0042
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: AD1 AD0 0 0 0 0 0 0
R = Reserved
Figure 18-6. ADC Data Register Low (ADRL)

Left Justified Mode
In right justified mode, this 8-bit result register holds the eight LSBs of
the 10-bit result. This register is updated each time an ADC conversion
completes. Reading ADRH latches the contents of ADRL until ADRL is
read. Until ADRL is read all subsequent ADC results will be lost.
Ad-
$0042
dress:
Bit 7 6 5 4 3 2 1 Bit 0
R = Reserved

Right Justified Mode

In 8-bit mode, this 8-bit result register holds the eight MSBs of the 10-bit
result. This register is updated each time an ADC conversion completes.
In 8-bit mode, this register contains no interlocking with ADRH.
Ad-
$0042
dress:
Bit 7 6 5 4 3 2 1 Bit 0
R = Reserved

8-Bit Mode
18.9.4 ADC Clock Register
This register selects the clock frequency for the ADC, selecting between
modes of operation.
Ad-
$0043
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 0
Write: R
Reset: 0 0 0 0 0 1 0 0
R = Reserved
Figure 18-9. ADC Clock Register (ADCLK)
ADIV2:ADIV0 — ADC Clock Prescaler Bits

ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 18-2
shows the available clock configurations. The ADC clock should be
set to between 500 kHz and 1 MHz.

I/O Registers
Table 18-2. ADC Clock Divide Ratio
ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 ADC input clock /1
1 X X ADC input clock /16

X = don’t care
ADICLK — ADC Input Clock Select Bit

ADICLK selects either bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
If the external clock (CGMXCLK) is equal or greater than 1 MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at fADIC, correct
operation can be guaranteed.
1 = Internal bus clock
0 = External clock, CGMXCLK
CGMXCLK or bus frequency

fADIC =
ADIV[2:0]
MODE1:MODE0 — Modes of Result Justification Bits

MODE1:MODE0 selects among four modes of operation. The
manner in which the ADC conversion results will be placed in the ADC
data registers is controlled by these modes of operation. Reset
returns right-justified mode.
00 = 8-bit truncation mode
01 = Right justified mode
10 = Left justified mode
11 = Left justified sign data mode


Section 19. Power-On Reset (POR)
19.1 Contents
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
19.2 Introduction
This section describes the power-on reset (POR) module.

The POR module provides a known, stable signal to the MCU at
power-on. This signal tracks VDD until the MCU generates a feedback
signal to indicate that it is properly initialized. At this time, the POR drives
its output low. The POR is not a brown-out detector, low-voltage
detector, or glitch detector. VDD at the POR must go completely to 0 to
reset the MCU. To detect power-loss conditions, use a low-voltage
inhibit module (LVI) or other suitable circuit.
Freescale Semiconductor Power-On Reset (POR) 327

Power-On Reset (POR)
328 Power-On Reset (POR) Freescale Semiconductor

Section 20. Break (BRK)
20.1 Contents
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
20.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
20.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . .330
20.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . .332
20.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .332
20.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . .332
20.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
20.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
20.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
20.6 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .333
20.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . .333
20.6.2 Break Address Registers. . . . . . . . . . . . . . . . . . . . . . . . .334
20.6.3 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . .336
20.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . .337
20.2 Introduction
This section describes the break (BRK) module. The break module can
generate a break interrupt that stops normal program flow at a defined
address to enter a background program.
Freescale Semiconductor Break (BRK) 329

Break (BRK)
20.3 Features
Features of the break module include:
• Accessible input/output (I/O) registers during the break interrupt
• Central processor unit (CPU) generated break interrupts
• Software-generated break interrupts
• Computer operating properly (COP) disabling during break
interrupts

When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).
These events can cause a break interrupt to occur:

• A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
• Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break

address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the microcontroller unit
(MCU) to normal operation. Figure 20-1 shows the structure of the break
module.
20.4.1 Flag Protection During Break Interrupts
The BCFE bit in the system integration module (SIM) break flag control
register (SBFCR) enables software to clear status bits during the break
state.
330 Break (BRK) Freescale Semiconductor

Break (BRK)
IAB15–IAB8
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB15–IAB0
CONTROL BREAK
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB7–IAB0
Figure 20-1. Break Module Block Diagram
Read
0 0 0 1 0 0 BW 0
:
SIM Break Status
$FE0 Write
Register (SBSR) R R R R R R NOTE R
0 :
See page 336.
Re-
0 0 0 1 0 0 0 0
set:
Read
:
SIM Break Flag Con- BCFE R R R R R R R
$FE0 Write
trol Register (SBFCR)
3 :
See page 337.
Re-
0
set:
Read
:
Break Address Regis- Bit 15 14 13 12 11 10 9 Bit 8
$FE0 Write
ter High (BRKH)
C :
See page 334.
Re-
0 0 0 0 0 0 0 0
set:
Figure 20-2. I/O Register Summary

Break (BRK)
Read
:
Break Address Regis- Bit 7 6 5 4 3 2 1 Bit 0
$FE0 Write
ter Low (BRKL)
D :
See page 334.
Re-
0 0 0 0 0 0 0 0
set:
Read
0 0 0 0 0 0
:
Break Status and BRKE BRKA
$FE0 Control Register Write
E (BRKSCR) :
See page 333.
Re-
0 0 0 0 0 0 0 0
set:
Note: Writing a logic 0 clears = Unimplemented = Reserved

R
BW.
Figure 20-2. I/O Register Summary
20.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:

• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in

progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
20.4.3 TIM During Break Interrupts
A break interrupt stops the timer counters.
20.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when VTST is present on

the RST pin.

Break (BRK)
Low-Power Modes
20.5 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
20.5.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if SBSW
is set. Clear the BW bit by writing logic 0 to it.
20.5.2 Stop Mode
A break interrupt causes exit from stop mode and sets the SBSW bit in
the break status register.
20.6 Break Module Registers

These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• SIM break status register (SBSR)
• SIM break flag control register (SBFCR)
20.6.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module
enable and status bits.
Ad-
$FE0E
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Figure 20-3. Break Status and Control Register (BRKSCR)

Break (BRK)
Read: 0 0 0 0 0 0
BRKE BRKA
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplement-
ed
Figure 20-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit

This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = When read, break address match
0 = When read, no break address match
20.6.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low
bytes of the desired breakpoint address. Reset clears the break address
registers.
Ad-
$FE0C
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 20-4. Break Address Register High (BRKH)

Break (BRK)
Break Module Registers
Ad-
$FE0D
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Bit 7 6 5 4 3 2 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 20-5. Break Address Register Low (BRKL)

Break (BRK)
20.6.3 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from wait mode. The flag is useful in applications
requiring a return to wait mode after exiting from a break interrupt.
Ad-
$FE00
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 1 0 0 BW 0
Write: R R R R R R Note R
Reset: 0 0 0 1 0 0 0 0
Note: Writing a logic 0 = Reserved

R
clears BW.
Figure 20-6. SIM Break Status Register (SBSR)
BW — Break Wait Bit

This read/write bit is set when a break interrupt causes an exit from
wait mode. Clear BW by writing a logic 0 to it. Reset clears BW.
1 = Break interrupt during wait mode
0 = No break interrupt during wait mode
BW can be read within the break interrupt routine. The user can modify
the return address on the stack by subtracting 1 from it. The example
code shown in Figure 20-7 works if the H register was stacked in the
break interrupt routine. Execute this code at the end of the break
interrupt routine.

Break (BRK)
Break Module Registers
HIBYTE EQU 5
LOBYTE EQU 6
; If not BW, do RTI
BRCLR BW,BSR, RETURN ; See if wait mode or stop
; mode was exited by break.
TST LOBYTE,SP ; If RETURNLO is not 0,
BNE DOLO ; then just decrement low byte.
DEC HIBYTE,SP ; Else deal with high byte also.
DOLO DEC LOBYTE,SP ; Point to WAIT/STOP opcode.
RETURN PULH ; Restore H register.
RTI
Figure 20-7. Example Code
20.6.4 SIM Break Flag Control Register
The SIM break flag control register (SBFCR) contains a bit that enables
software to clear status bits while the MCU is in a break state.
Ad-
$FE03
dress:
Bit 7 6 5 4 3 2 1 Bit 0
Read:
BCFE R R R R R R R
Write:
Reset: 0
R = Reserved
Figure 20-8. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit

This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break

Break (BRK)

Section 21. Electrical Specifications
21.1 Contents
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
21.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . .340
21.4 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . .341
21.5 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .342
21.6 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . .343
21.7 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
21.8 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
21.9 TImer Interface Module Characteristics . . . . . . . . . . . . . . .346
21.10 Clock Generation Module Component Specifications . . . 347
21.11 CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .347
21.12 CGM Acquisition/Lock Time Specifications. . . . . . . . . . . .348
21.13 Analog-to-Digital Converter (ADC) Characteristics. . . . . . 349
21.2 Introduction
This section contains electrical and timing specifications. These values
are design targets and have not yet been fully characterized.
Freescale Semiconductor Electrical Specifications 339

Electrical Specifications
21.3 Absolute Maximum Ratings

Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
NOTE: This device is not guaranteed to operate properly at the maximum

ratings. Refer to 21.6 DC Electrical Characteristics for guaranteed
operating conditions.
Characteristic(1) Symbol Value Unit
Supply voltage VDD –0.3 to +6.0 V
VSS – 0.3
Input voltage VIn V
to VDD + 0.3
Input high voltage VHI VDD + 4 V
Maximum current per pin

I ± 25 mA
excluding VDD and VSS
Storage temperature tSTG –55 to +150 °C
Maximum current out of VSS IMVSS 100 mA
Maximum current Into VDD IMVDD 100 mA
1. Voltages are referenced to VSS.
NOTE: This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIn and VOut be constrained to the
range VSS ≤ (VIn or VOut) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD).
340 Electrical Specifications Freescale Semiconductor

Functional Operating Range
21.4 Functional Operating Range
Characteristic Symbol Value Unit
Operating temperature range(1)

MC68HC908MR8CP –40 to +85
MC68HC908MR8CFA –40 to +85
MC68HC908MR8CDW –40 to +85
MC68HC908MR8VFA –40 to +105
TA °C
MC68HC908MR8VP –40 to +105
MC68HC908MR8VDW –40 to +105
MC68HC908MR8MFA –40 to +125
MC68HC908MR8MP –40 to +125
MC68HC908MR8MDW –40 to +125
Operating voltage range VDD 5.0 ± 10% V
1. Contact a Freescale representative for temperature availability.

C = Extended temperature range (–40 to +85°C)
V = Industrial temperature range (–40 to +105°C)
M = Automotive temperature range (–40 to +125°C)

21.5 Thermal Characteristics
Characteristic Symbol Value Unit
Thermal resistance
32-pin LQFP
θJA 68.9(1) °C/W
28-pin PDIP —
28-pin SOIC —
I/O pin power dissipation PI/O User determined W
PD = (IDD x VDD)
Power dissipation(2) PD
+ PI/O = K/(TJ + 273°C)
W
PD x (TA + 273°C)
Constant(3) K W/°C
+ PD2 x θJA
Average junction temperature TJ TA + (PD x θJA) °C
Maximum junction temperature TJM 125 °C
1. 32-pin LQFP resistance measured at 200 ft/min.

2. Power dissipation is a function of temperature.
3. K is a constant unique to the device. K can be determined for a known TA and measured
PD. With this value of K, PD and TJ can be determined for any value of TA.

DC Electrical Characteristics
21.6 DC Electrical Characteristics
Characteristic(1) Symbol Min Typ(2) Max Unit
Output high voltage

ILoad = –2.0 mA for all I/O pins except: VDD –0.8
Port A bits 0 and 1
Port B bits 5 and 6
VOH — — V
ILoad = –7.0 mA for: VDD –1.0
Port A bits 0 and 1 and port B bits 5–6,
a maximum of four 15-mA outputs may be active
at any time
Output low voltage

ILoad = 1.6 mA for all I/O pins except: — — 0.4
Port A bits 0 and 1
Port B bits 5 and 6
VOL V
ILoad = 15 mA for: — — 1.5
Port A bits 0 and 1 and Port B bits 5–6,
a maximum of four 15-mA outputs may be active
at any time
Input high voltage

VIH 0.7 x VDD — VDD V
All ports, IRQs, RESET, OSC1
Input low voltage

VIL VSS — 0.3 x VDD V
All ports, IRQs, RESET, OSC1
VDD supply current

Run(3) — — 40 mA
Wait(4) — — 12 mA
Stop(5)
IDD
Up to 85°C — — 5 µA
Above 85°C — — 15 µA
25°C with LVI enabled — — 350 µA
Quiescent(5) — — 100 µA
I/O ports high-impedance leakage current IIL — — ±10 µA
Input current except PTC1/FAULT4 IIn — — ±1 µA
Input current PTC1/FAULT4 IIn 80 208 µA
Capacitance COut — — 12
pF
Ports (as input or output) CIn — — 8
Low-voltage inhibit falling VLVRF1 4.0 4.4 — V
Low-voltage reset/recover hysteresis VLVH1 20 50 — mV
Low-voltage recover rising VLVRR1 — 4.5 4.75 V

Characteristic(1) Symbol Min Typ(2) Max Unit
— Continued
Low-voltage inhibit falling VLVRF2 3.8 4.1 — V
Low-voltage reset/recover hysteresis VLVH2 50 100 — mV
Low-voltage recover rising VLVRR2 — 4.2 4.6 V
POR re-arm voltage(6) VPOR 0 — 100 mV
POR rise time ramp rate(7) RPOR 0.035 — — V/ms
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 8.2 MHz); all inputs 0.2 V from rail; no dc
loads; less than 100 pF on all outputs; CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly
affects run IDD; measured with all modules enabled
4. Wait IDD measured using external square wave clock source (fOSC = 8.2 MHz); all inputs 0.2 V from rail; no dc loads; less
than 100 pF on all outputs; CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD;
measured with PLL and LVI enabled
5. Quiescent IDD measured with PLL and LVI disengaged; OCS1 grounded; no port pins sourcing current. It is measured
through combination of VDD and VDDA.
6. Maximum is highest guaranteed voltage for POR.
7. Maximum is the highest possible voltage for POR. If minimum VDD is not reached before the internal POR reset is released,
RST must be driven low externally until minimum VDD is reached.

Memory Characteristics
21.7 Memory Characteristics

Characteristic Symbol Min Typ Max Unit
RAM data retention voltage VRDR 1.3 — — V
FLASH program bus clock frequency — 1 — — MHz
FLASH read bus clock frequency fRead(1) 32k — 8.4M Hz
FLASH page erase time tErase(2) 1 — — ms
FLASH mass erase time tMErase(3) 4 — — ms
FLASH PGM/ERASE to HVEN set up time tnvs 10 — — µs

FLASH high-voltage hold time tnvh 5 — — µs
FLASH high-voltage hold time (mass erase) tnvhl 100 — — µs
FLASH program hold time tpgs 5 — — µs
FLASH program time tPROG 30 — 40 µs
FLASH return to read time trcv(4) 1 — — µs
FLASH cumulative program HV period tHV(5) — — 4 ms
FLASH row erase endurance(6) — 10k 100k(7) — Cycles
FLASH row program endurance(8) — 10k 100k(7) — Cycles
FLASH data retention time(9) — 10 100(10) — Years

Notes:
1. fRead is defined as the frequency range for which the FLASH memory can be read.
2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH
memory.
3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH
memory.
4. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing
HVEN to logic 0.
5. tHV is defined as the cumulative high voltage programming time to the same row before next erase.
tHV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG × 64) ≤ tHV max.
6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at
least this many erase / program cycles.
7. FLASH endurance is a function of the temperature at which erasure occurs. Typical endurance degrades when the tem-
perature while erasing is less than 25°C.
8. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at
least this many erase / program cycles.
9. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum
time specified.
10. Freescale performs reliability testing for data retention. These tests are based on samples tested at elevated tempera-
tures. Due to the higher activation energy of the elevated test temperature, calculated life tests correspond to more than
100 years of operation/storage at 55°C

21.8 Control Timing
Characteristic(1) Symbol Min Max Unit
Frequency of operation(2)
Crystal option fOSC 1 8 MHz
External clock option(3) dc(4) 32.8
Internal operating frequency fOP — 8.2 MHz
RESET input pulse width low(5) tIRL 50 — ns
1. VDD = 5.0 Vdc ± 10%; VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted
2. See 21.8 Control Timing for more information.
3. No more than 10 percent duty cycle deviation from 50 percent.
4. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor-
mation.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause reset.
21.9 TImer Interface Module Characteristics
Characteristic Symbol Min Max Unit
tTIH
Input capture pulse width 125 — ns
tTIL
tTCH
Input clock pulse width (1/fOP) + 5 — ns
tTCL

Clock Generation Module Component Specifications
21.10 Clock Generation Module Component Specifications
Characteristic Symbol Min Typ Max Notes
Consult crystal
Crystal load capacitance CL — — —
manufacturing data
Consult crystal
Crystal fixed capacitance C1 — 2 * CL —
manufacturing data
Consult crystal
Crystal tuning capacitance C2 — 2 * CL —
manufacturing data
Feedback bias resistor RB — 22 MΩ —
Series resistor RS 0 330 kΩ 1 MΩ Not required
CFACT*
Filter capacitor CF — — —
(VDDA/fXCLK)
CBYP must provide low ac

impedance from
f = fXCLK/100 to
Bypass capacitor CBYP — 0.1 µF —
100 * fVCLK, so series
resistance must be
considered.
21.11 CGM Operating Conditions
Characteristic Symbol Min Typ Max
Crystal reference frequency fXCLK 1 MHz — 8 MHz
Range nominal multiplier fNOM — 4.9152 MHz —
VCO center-of-range frequency fVRS 4.9152 MHz — 32.8 MHz
VCO frequency multiplier N 1 — 15
VCO center of range multiplier L 1 — 15
VCO operating frequency fVCLK fVRSMIN — fVRSMAX

21.12 CGM Acquisition/Lock Time Specifications
Description Symbol Min Typ Max Notes
Filter capacitor multiply factor CFACT — 0.0154 — F/sV
Acquisition mode time factor KACQ — 0.1135 — V
Tracking mode time factor KTRK — 0.0174 — V
(8 * VDDA)/ If CF chosen
Manual mode time to stable tACQ — —
(fXCLK * KACQ) correctly
Manual stable to lock time tAL — —
(fXCLK * KTRK) correctly
Manual acquisition time tLock — tACQ + tAL — —
Tracking mode entry frequency

∆TRK 0 — ±3.6% —
tolerance
Acquisition mode entry frequency

∆ACQ ±6.3% — ±7.2% —
tolerance
Lock entry frequency tolerance ∆Lock 0 — ±0.9% —
Lock exit frequency tolerance ∆UNL ±0.9% — ±1.8% —
Reference cycles per acquisition

nACQ — 32 — —
mode measurement
Reference cycles per tracking mode

nTRK — 128 — —
measurement
Automatic mode time to stable tACQ nACQ/fXCLK —
(fXCLK * KACQ) correctly
Automatic stable to lock time tAL nTRK/fXCLK —
(fXCLK * KTRK) correctly
Automatic lock time tLock — tACQ + tAL — —
± (fCRYS) N = VCO
PLL jitter (deviation of average bus
fJ 0 — * (0.025 %) freq. mult.
frequency over 2 ms)
* (N/4) (GBNT)

Analog-to-Digital Converter (ADC) Characteristics
21.13 Analog-to-Digital Converter (ADC) Characteristics
Characteristic Symbol Min Typ Max Unit Notes
A/D reference voltage VREFH 4.5 — 5.5 V —
Input voltages VADIN 0 — VREFH V VADIN <= VREFH
Resolution BAD 10 — 10 Bits —
Includes
Absolute accuracy AAD — — 4 Counts
quantization
ADC internal clock fADIC 500 k — 1M Hz tAIC = 1/fADIC
Conversion range RAD VSSA — VREFH V —
Power-up time tADPU 16 — tAIC cycles —
Conversion time tADC 16 — 17 tAIC cycles —
Sample time tADS 5 — — tAIC cycles —
Monotonicity MAD Guaranteed
Zero input reading ZADI 000 — 003 Hex VADIN = VSSA
Full-scale reading FADI 3FD — 3FF Hex VADIN = VREFH
Not
Input capacitance CADI — — 30 pF
characterized
Absolute accuracy Includes

AAD — — ±1 Counts
(8-bit truncation mode) quantization
Quantization error +7/8

— — — LSB —
(8-bit truncation mode) –1/8


Section 22. Mechanical Specifications
22.1 Contents
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
22.3 32-Pin LQFP (Case #873A). . . . . . . . . . . . . . . . . . . . . . . . . .352
22.4 28-Pin PDIP (Case #710). . . . . . . . . . . . . . . . . . . . . . . . . . . .353
22.5 28-Pin SOIC (Case #751F) . . . . . . . . . . . . . . . . . . . . . . . . . .353
22.2 Introduction
The MC68HC908MR8 is available in these packages:
• 32-pin low-profile quad flat pack (LQFP)
• 28-pin dual in-line package (PDIP)
• 28-pin small outline package (SOIC)
The package information contained in this section is the latest available

at the time of this publication. To make sure that you have the latest
package specifications, please visit the Freescale website at
http://freescale.com. Follow World Wide Web on-line instructions to
retrieve the current mechanical specifications.
Freescale Semiconductor Mechanical Specifications 351

Mechanical Specifications
22.3 32-Pin LQFP (Case #873A)
–T–, –U–, –Z–

A 4X
A1 0.20 (0.008) AB T–U Z
32 25
–T– –U–
B V AE
P
B1 DETAIL Y
8 17
V1
AE
9 DETAIL Y
4X
–Z–
9 S1 0.20 (0.008) AC T–U Z NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
S Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
DETAIL AD 4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
G AT DATUM PLANE –AB–.
–AB– 5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
SEATING 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PLANE
–AC– PROTRUSION. ALLOWABLE PROTRUSION IS
0.10 (0.004) AC 0.250 (0.010) PER SIDE. DIMENSIONS A AND B
AC T–U Z
BASE DO INCLUDE MOLD MISMATCH AND ARE

METAL
DETERMINED AT DATUM PLANE –AB–.
ÉÉ
7. DIMENSION D DOES NOT INCLUDE DAMBAR
N PROTRUSION. DAMBAR PROTRUSION SHALL
ÉÉ
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
ÉÉ
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
M
0.0076 (0.0003).
0.20 (0.008)
F D
9. EXACT SHAPE OF EACH CORNER MAY VARY
ÉÉ
FROM DEPICTION.
8X M_
R J MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 7.000 BSC 0.276 BSC
A1 3.500 BSC 0.138 BSC
SECTION AE–AE B 7.000 BSC 0.276 BSC
C E B1 3.500 BSC 0.138 BSC
C 1.400 1.600 0.055 0.063
D 0.300 0.450 0.012 0.018
E 1.350 1.450 0.053 0.057
F 0.300 0.400 0.012 0.016
W Q_ G 0.800 BSC 0.031 BSC
H K H 0.050 0.150 0.002 0.006
0.250 (0.010)
J 0.090 0.200 0.004 0.008

GAUGE PLANE
X
K 0.500 0.700 0.020 0.028
M 12_ REF 12_ REF
DETAIL AD N 0.090 0.160 0.004 0.006
P 0.400 BSC 0.016 BSC
Q 1_ 5_ 1_ 5_
R 0.150 0.250 0.006 0.010
S 9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
V 9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
W 0.200 REF 0.008 REF
X 1.000 REF 0.039 REF
352 Mechanical Specifications Freescale Semiconductor

28-Pin PDIP (Case #710)
22.4 28-Pin PDIP (Case #710)
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
28 15 2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
B MOLD FLASH.
MILLIMETERS INCHES
1 14 DIM MIN MAX MIN MAX
A 36.45 37.21 1.435 1.465
A L B 13.72 14.22 0.540 0.560
C C 3.94 5.08 0.155 0.200
D 0.36 0.56 0.014 0.022
N F 1.02 1.52 0.040 0.060
G 2.54 BSC 0.100 BSC
H 1.65 2.16 0.065 0.085
J 0.20 0.38 0.008 0.015
H G J K 2.92 3.43 0.115 0.135
K M
F D L 15.24 BSC 0.600 BSC
SEATING M 0° 15° 0° 15°
PLANE
N 0.51 1.02 0.020 0.040
22.5 28-Pin SOIC (Case #751F)
-A-
28 15 NOTES:
1. DIMENSIONING AND TOLERANCING PER
14X P ANSI Y14.5M, 1982.
-B- 0.010 (0.25) M B M 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
1 14 4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
28X D DAMBAR PROTRUSION SHALL BE 0.13
M (0.005) TOTAL IN EXCESS OF D
0.010 (0.25) M T A S B S
DIMENSION AT MAXIMUM MATERIAL
R X 45° CONDITION.
MILLIMETERS INCHES
-T- C DIM MIN MAX MIN MAX
A 17.80 18.05 0.701 0.711
-T- B 7.40 7.60 0.292 0.299
26X G SEATING C 2.35 2.65 0.093 0.104
PLANE
D 0.35 0.49 0.014 0.019
K
F F 0.41 0.90 0.016 0.035
G 1.27 BSC 0.050 BSC
J 0.23 0.32 0.009 0.013
J K 0.13 0.29 0.005 0.011
M 0° 8° 0° 8°
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
Freescale Semiconductor Mechanical Specifications 353

354 Mechanical Specifications Freescale Semiconductor

Section 23. Ordering Information
23.1 Contents
23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
23.3 MC Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
23.2 Introduction
This section contains instructions for ordering the MC68HC908MR8.
23.3 MC Order Numbers

Table 23-1. MC Order Numbers
Operating
(1) Temperature Range
MC Order Number
(°C)
MC68HC908MR8CFA – 40 to + 85
MC68HC908MR8CP – 40 to + 85
MC68HC908MR8CDW – 40 to + 85
MC68HC908MR8VFA – 40 to + 105
MC68HC908MR8VP – 40 to + 105
MC68HC908MR8VDW – 40 to + 105
MC68HC908MR8MFA – 40 to + 125
MC68HC908MR8MP – 40 to + 125
MC68HC908MR8MDW – 40 to + 125
1. FA = quad flat pack
P = plastic dual in line package
DW = Small outline integrated circuit (SOIC) package
Freescale Semiconductor Ordering Information 355

Ordering Information
356 Ordering Information Freescale Semiconductor

Revision History
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
Changes from Rev 3.0 published in April 2002 to Rev 4.0 published in
July 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Introduction
This section contains the revision history for the MC68HC908MR8
advance information data book.
Changes from Rev 3.0 published in April 2002 to Rev 4.0 published in July
2002
Section Page (in Rev 0.4) Description of change
Electrical VOL max updated for ILoad = 15 mA

343
Specifications Stop IDD limits updated for different temperature specs
Freescale Semiconductor Revision History 357

Revision History
358 Revision History Freescale Semiconductor

Glossary
A — See accumulator (A).
accumulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the
accumulator to hold operands and results of arithmetic and logic operations.
acquisition mode — A mode of PLL operation during startup before the PLL locks on a
frequency. Also see tracking mode.
address bus — The set of wires that the CPU or DMA uses to read and write memory locations.
addressing mode — The way that the CPU determines the operand address for an instruction.
The M68HC08 CPU has 16 addressing modes.
ALU — See arithmetic logic unit (ALU).
arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform
arithmetic, logic, and manipulation operations on operands.
asynchronous — Refers to logic circuits and operations that are not synchronized by a common
reference signal
baud rate — The total number of bits transmitted per unit of time.
BCD — See binary-coded decimal (BCD)

binary — Relating to the base 2 number system
binary number system — The base 2 number system, having two digits, 0 and 1. Binary
arithmetic is convenient in digital circuit design because digital circuits have two permissible
voltage levels, low and high. The binary digits 0 and 1 can be interpreted to correspond to the
two digital voltage levels.
binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10
decimal digits and that retains the same positional structure of a decimal number. For
example,
234 (decimal) = 0010 0011 0100 (BCD)

bit — A binary digit. A bit has a value of either logic 0 or logic 1.
branch instruction — An instruction that causes the CPU to continue processing at a memory
location other than the next sequential address.
break module — A module in the M68HC08 Family. The break module allows software to halt
program execution at a programmable point to enter a background routine.
breakpoint — A number written into the break address registers of the break module. When a
number appears on the internal address bus that is the same as the number in the break
address registers, the CPU executes the software interrupt instruction (SWI).
break interrupt — A software interrupt caused by the appearance on the internal address bus
of the same value that is written in the break address registers.
bus — A set of wires that transfers logic signals.
bus clocks — There are two bus clocks, IT12 and IT23. These clocks are generated by the CGM
and distributed throughout the MCU by the SIM. The frequency of the bus clocks, or operating
frequency, is fOP. While the frequency of these two clocks is the same, the phase is different.
byte — A set of eight bits.
C — The carry/borrow bit in the condition code register. The CPU08 sets the carry/borrow bit
when an addition operation produces a carry out of bit 7 of the accumulator or when a
subtraction operation requires a borrow. Some logical operations and data manipulation
instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and
shifts and rotates).
CCR — See condition code register.
central processor unit (CPU) — The primary functioning unit of any computer system. The
CPU controls the execution of instructions.
CGM — See clock generator module (CGM).
clear — To change a bit from logic 1 to logic 0; the opposite of set.
clock — A square wave signal used to synchronize events in a computer.
clock generator module (CGM) — A module in the M68HC08 Family. The CGM generates a
base clock signal from which the system clocks are derived. The CGM may include a crystal
oscillator circuit and/or phase-locked loop (PLL) circuit.

comparator — A device that compares the magnitude of two inputs. A digital comparator defines
the equality or relative differences between two binary numbers.
computer operating properly module (COP) — A counter module in the M68HC08 Family that
resets the MCU if allowed to overflow.
condition code register (CCR) — An 8-bit register in the CPU08 that contains the interrupt
mask bit and five bits that indicate the results of the instruction just executed.
control bit — One bit of a register manipulated by software to control the operation of the
module.
control unit — One of two major units of the CPU. The control unit contains logic functions that
synchronize the machine and direct various operations. The control unit decodes instructions
and generates the internal control signals that perform the requested operations. The outputs
of the control unit drive the execution unit, which contains the arithmetic logic unit (ALU), CPU
registers, and bus interface.
COP — See computer operating properly module (COP).
counter clock — The input clock to the TIM counter. This clock is an output of the prescaler
sub-module. The frequency of the counter clock is fTCNT, and the period is tTCNT.
CPU — See central processor unit (CPU).
CPU08 — The central processor unit of the M68HC08 Family.
CPU cycles — A CPU clock cycle is one period of the internal bus-rate clock, fOP, normally
derived by dividing a crystal oscillator source by two or more so the high and low times will
be equal. The length of time required to execute an instruction is measured in CPU clock
cycles.
CPU registers — Memory locations that are wired directly into the CPU logic instead of being
part of the addressable memory map. The CPU always has direct access to the information
in these registers. The CPU registers in an M68HC08 are:
• A, 8-bit accumulator
• H:X, 16-bit index register
• SP, 16-bit stack pointer
• PC, 16-bit program counter
• CCR, condition code register containing the V, H, I, N, Z, and C bits

CSIC — customer-specified integrated circuit
cycle time — The period of the operating frequency: tCYC = 1/fOP.
decimal number system — Base 10 numbering system that uses the digits zero through nine.
direct memory access module (DMA) — A M68HC08 Family module that can perform data
transfers between any two CPU-addressable locations without CPU intervention. For
transmitting or receiving blocks of data to or from peripherals, DMA transfers are faster and
more code-efficient than CPU interrupts.
DMA — See direct memory access module (DMA).
DMA service request — A signal from a peripheral to the DMA module that enables the DMA
module to transfer data.
duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is
usually represented by a percentage.
EEPROM — Electrically erasable, programmable, read-only memory. A non-volatile type of

memory that can be electrically reprogrammed.
EPROM — Erasable, programmable, read-only memory. A non-volatile type of memory that can
be erased by exposure to an ultraviolet light source and then reprogrammed.
exception — An event such as an interrupt or a reset that stops the sequential execution of the
instructions in the main program.
external interrupt module (IRQ) — A module in the M68HC08 Family with both dedicated
external interrupt pins and port pins that can be enabled as interrupt pins.
fetch — To copy data from a memory location into the accumulator.
firmware — Instructions and data programmed into non-volatile memory.
free-running counter — A device that counts from zero to a predetermined number, then rolls
over to zero and begins counting again.
full-duplex transmission — Communication on a channel in which data can be sent and

received simultaneously.
H — The upper byte of the 16-bit index register (H:X) in the CPU08.

H — The half-carry bit in the condition code register of the CPU08. This bit indicates a carry from
the low-order four bits of the accumulator value to the high-order four bits. The half-carry bit
is required for binary-coded decimal arithmetic operations. The decimal adjust accumulator
(DAA) instruction uses the state of the H and C bits to determine the appropriate correction
factor.
hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A
through F.
high byte — The most significant eight bits of a word.
illegal address — An address not within the memory map.
illegal opcode — A non-existent opcode.
I — The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts
are disabled.
index register (H:X) — A 16-bit register in the CPU08. The upper byte of H:X is called H. The
lower byte is called X. In the indexed addressing modes, the CPU uses the contents of H:X
to determine the effective address of the operand. H:X can also serve as a temporary data
storage location.
input/output (I/O) — Input/output interfaces between a computer system and the external world.
A CPU reads an input to sense the level of an external signal and writes to an output to
change the level on an external signal.
instructions — Operations that a CPU can perform. Instructions are expressed by programmers
as assembly language mnemonics. A CPU interprets an opcode and its associated
operand(s) and instruction.
interrupt — A temporary break in the sequential execution of a program to respond to signals

from peripheral devices by executing a subroutine.
interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to
execute a subroutine.
I/O — See input/output (I/0).
IRQ — See external interrupt module (IRQ).
jitter — Short-term signal instability.
latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power
is applied to the circuit.

latency — The time lag between instruction completion and data movement.
least significant bit (LSB) — The rightmost digit of a binary number.
logic 1 — A voltage level approximately equal to the input power voltage (VDD).
logic 0 — A voltage level approximately equal to the ground voltage (VSS).
low byte — The least significant eight bits of a word.
low voltage inhibit module (LVI) — A module in the M68HC08 Family that monitors power
supply voltage.
LVI — See low-voltage inhibit module (LVI).

M68HC08 — A Freescale family of 8-bit MCUs.
mark/space — The logic 1/logic 0 convention used in formatting data in serial communication.
mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used
in integrated circuit fabrication to transfer an image onto silicon.
mask option — An optional microcontroller feature that the customer chooses to enable or
disable.
MCU — Microcontroller unit. See microcontroller.
memory location — Each M68HC08 memory location holds one byte of data and has a unique
address. To store information in a memory location, the CPU places the address of the
location on the address bus, the data information on the data bus, and asserts the write
signal. To read information from a memory location, the CPU places the address of the
location on the address bus and asserts the read signal. In response to the read signal, the
selected memory location places its data onto the data bus.
memory map — A pictorial representation of all memory locations in a computer system.
microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU,

memory, a clock oscillator, and input/output (I/O) on a single integrated circuit.
modulo counter — A counter that can be programmed to count to any number from zero to its
maximum possible modulus.
monitor ROM — A section of ROM that can execute commands from a host computer for testing
purposes.
most significant bit (MSB) — The leftmost digit of a binary number.

multiplexer — A device that can select one of a number of inputs and pass the logic level of that
input on to the output.
N — The negative bit in the condition code register of the CPU08. The CPU sets the negative bit
when an arithmetic operation, logical operation, or data manipulation produces a negative
result.
nibble — A set of four bits (half of a byte).
object code — The output from an assembler or compiler that is itself executable machine code
or is suitable for processing to produce executable machine code.
opcode — A binary code that instructs the CPU to perform an operation.
open-drain — An output that has no pullup transistor. An external pullup device can be
connected to the power supply to provide the logic 1 output voltage.
operand — Data on which an operation is performed. Usually, a statement consists of an

operator and an operand. For example, the operator may be an add instruction, and the
operand may be the quantity to be added.
oscillator — A circuit that produces a constant frequency square wave that is used by the
computer as a timing and sequencing reference.
overflow — A quantity that is too large to be contained in one byte or one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted.
In a system that uses odd parity, every byte is expected to have an odd number of logic 1s.
In an even parity system, every byte should have an even number of logic 1s. In the
transmitter, a parity generator appends an extra bit to each byte to make the number of logic
1s odd for odd parity or even for even parity. A parity checker in the receiver counts the
number of logic 1s in each byte. The parity checker generates an error signal if it finds a byte
with an incorrect number of logic 1s.
PC — See program counter (PC).
peripheral — A circuit not under direct CPU control.
phase-locked loop (PLL) — An oscillator circuit in which the frequency of the oscillator is
synchronized to a reference signal.
PLL — See phase-locked loop (PLL).

pointer — Pointer register. An index register is sometimes called a pointer register because its
contents are used in the calculation of the address of an operand and, therefore, points to the
operand.
polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different
voltage levels, VDD and VSS.
polling — Periodically reading a status bit to monitor the condition of a peripheral device.
port — A set of wires for communicating with off-chip devices.
prescaler — A circuit that generates an output signal related to the input signal by a fractional
scale factor such as 1/2, 1/8, 1/10, etc.
program — A set of computer instructions that causes a computer to perform a desired

operation or operations.
program counter (PC) — A 16-bit register in the CPU08. The PC register holds the address of
the next instruction or operand that the CPU will use.
pull — An instruction that copies into the accumulator the contents of a stack RAM location. The
stack RAM address is in the stack pointer.
pullup — A transistor in the output of a logic gate that connects the output to the logic 1 voltage
of the power supply.
pulse-width — The amount of time a signal is on as opposed to being in its off state.
pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a

signal with a constant frequency.
push — An instruction that copies the contents of the accumulator to the stack RAM. The stack
RAM address is in the stack pointer.
PWM period — The time required for one complete cycle of a PWM waveform.
PMC — Pulse width modulated motor control module
RAM — Random access memory. All RAM locations can be read or written by the CPU. The
contents of a RAM memory location remain valid until the CPU writes a different value or until
power is turned off.
RC circuit — A circuit consisting of capacitors and resistors having a defined time constant.
read — To copy the contents of a memory location to the accumulator.

register — A circuit that stores a group of bits.
reserved memory location — A memory location that is used only in special factory test modes.
Writing to a reserved location has no effect. Reading a reserved location returns an
unpredictable value.
reset — To force a device to a known condition.
ROM — Read-only memory. A type of memory that can be read but cannot be changed (written).
The contents of ROM must be specified before manufacturing the MCU.
SCI — See serial communication interface module (SCI).
serial — Pertaining to sequential transmission over a single line.
serial communication interface module (SCI) — A module in the M68HC08 Family that
supports asynchronous communication.
serial peripheral interface module (SPI) — A module in the M68HC08 Family that supports
synchronous communication.
set — To change a bit from logic 0 to logic 1; opposite of clear.
shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to
them and that can shift the logic levels to the right or left through adjacent circuits in the chain.
signed — A binary number notation that accommodates both positive and negative numbers.
The most significant bit is used to indicate whether the number is positive or negative,
normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the
magnitude of the number.
SIM — See system integration module (SIM).
software — Instructions and data that control the operation of a microcontroller.
software interrupt (SWI) — An instruction that causes an interrupt and its associated vector
fetch.
SPI — See serial peripheral interface module (SPI).
stack — A portion of RAM reserved for storage of CPU register contents and subroutine return
addresses.
stack pointer (SP) — A 16-bit register in the CPU08 containing the address of the next available
storage location on the stack.
start bit — A bit that signals the beginning of an asynchronous serial transmission.

status bit — A register bit that indicates the condition of a device.
stop bit — A bit that signals the end of an asynchronous serial transmission.
subroutine — A sequence of instructions to be used more than once in the course of a program.
The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each
place in the main program where the subroutine instructions are needed, a jump or branch to
subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the flow
of the main program to execute the instructions in the subroutine. When the RTS instruction
is executed, the CPU returns to the main program where it left off.
synchronous — Refers to logic circuits and operations that are synchronized by a common
reference signal.
system integration module (SIM) — One of a number of modules that handle a variety of
control functions in the modular M68HC08 Family. The SIM controls mode of operation,
resets and interrupts, and system clock distribution.
TIM — See timer interface module (TIM).
timer interface module (TIM) — A module used to relate events in a system to a point in time.
timer — A module used to relate events in a system to a point in time.
toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0.
tracking mode — Mode of low-jitter PLL operation during which the PLL is locked on a
frequency. Also see acquisition mode.
two’s complement — A means of performing binary subtraction using addition techniques. The
most significant bit of a two’s complement number indicates the sign of the number (1
indicates negative). The two’s complement negative of a number is obtained by inverting
each bit in the number and then adding 1 to the result.
unbuffered — Utilizes only one register for data; new data overwrites current data.
unimplemented memory location — A memory location that is not used. Writing to an

unimplemented location has no effect. Reading an unimplemented location returns an
unpredictable value. Executing an opcode at an unimplemented location causes an illegal
address reset.
V — The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when
a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and
BLT use the overflow bit.

variable — A value that changes during the course of program execution.
VCO — See voltage-controlled oscillator.
vector — A memory location that contains the address of the beginning of a subroutine written
to service an interrupt or reset.
voltage-controlled oscillator (VCO) — A circuit that produces an oscillating output signal of a

frequency that is controlled by a dc voltage applied to a control input.
waveform — A graphical representation in which the amplitude of a wave is plotted against time.
wired-OR — Connection of circuit outputs so that if any output is high, the connection point is
high.
word — A set of two bytes (16 bits).
write — The transfer of a byte of data from the CPU to a memory location.
X — The lower byte of the index register (H:X) in the CPU08.
Z — The zero bit in the condition code register of the CPU08. The CPU08 sets the zero bit when
an arithmetic operation, logical operation, or data manipulation produces a result of $00.


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MC68HC908MR8 — Rev 4.1 Technical Data

Section 1. General Description . . . . . . . . . . . . . . . . . . . . 29

MC68HC908MR8 — Rev 4.1 Technical Data

Freescale Semiconductor List of Paragraphs 5

Section 20. Break (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . 329

Technical Data MC68HC908MR8 — Rev 4.1

6 List of Paragraphs Freescale Semiconductor

Section 1. General Description

Section 2. Memory Map

MC68HC908MR8 — Rev 4.1 Technical Data

Freescale Semiconductor Table of Contents 7

Section 3. Random-Access Memory (RAM)

Section 4. FLASH Memory

Section 5. Configuration Register (CONFIG)

Section 6. Central Processor Unit (CPU)

Technical Data MC68HC908MR8 — Rev 4.1

8 Table of Contents Freescale Semiconductor

6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Section 7. System Integration Module (SIM)

MC68HC908MR8 — Rev 4.1 Technical Data

Freescale Semiconductor Table of Contents 9

7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Section 8. Clock Generator Module (CGM)

Technical Data MC68HC908MR8 — Rev 4.1

10 Table of Contents Freescale Semiconductor

8.10 CGM During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Section 9. Pulse-Width Modulator for Motor Control

MC68HC908MR8 — Rev 4.1 Technical Data

Freescale Semiconductor Table of Contents 11

9.12 Control Logic Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Section 10. Monitor ROM (MON)

Section 11. Timer Interface A (TIMA)

Technical Data MC68HC908MR8 — Rev 4.1

12 Table of Contents Freescale Semiconductor

11.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Section 12. Timer Interface B (TIMB)

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12.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

Section 13. Serial Communications Interface (SCI)

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13.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .262

Section 14. Input/Output (I/O) Ports

Section 15. Computer Operating Properly (COP)

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15.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Section 16. External Interrupt (IRQ)

Section 17. Low-Voltage Inhibit (LVI)

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17.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

Section 18. Analog-to-Digital Converter (ADC)

Section 19. Power-On Reset (POR)

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