GS12070 Final Data Sheet Rev6

GS12070
UHD-SDI Gearbox
Key Features Description

• Fully standards compliant turnkey solution enabling a The GS12070 is a highly configurable UHD-SDI Gearbox
simplified UHD-SDI interface which performs multiplexing and de-multiplexing
• Converts between HD-SDI, 3G-SDI, 6G UHD-SDI, and necessary to facilitate conversions between SMPTE ST
12G UHD-SDI using MUX (Multiplex) and DeMUX
(Demultiplex) modes 425-3 and/or ST 425-5 (multi-link 3G-SDI) Interface and
• Quad Link 3G-SDI Single Link 12G UHD-SDI SMPTE ST 2081-1 (6G UHD-SDI) and/or ST 2082-1 (12G
• Quad Link (1.5Gb/s x 4) HD-SDI  Single Link 6Gb/s UHD-SDI) Interfaces. The Gearbox also supports conversion
• Quad Link 6G UHD-SDI Dual Link 12G UHD-SDI between 4 x HD-SDI and 6Gb/s SDI.
• Quad Link 3G-SDI (ST 425-5/6)  Dual Link 6G
UHD-SDI ST 425-5 ST 2081-11 ST 2082-10
• Dual Link 6G UHD-SDI  Single Link 12G UHD-SDI Quad-link 3G Dual-link 6G Single-link 12G
• Dual Link 3G-SDI (ST 425-3) Single Link 6G
UHD-SDI 3840 x 2160
p60
• Dual Link (1.5Gb/s x 2) HD-SDI Single Link 3Gb/s 4:2:2 10-bit
• Bypass modes for all supported rates, including SD
4 x 3G ↔ 2 x 6G 2 x 6G ↔ 12G
• Automatic skew compensation for multi-link inputs
• Automatic input link order handling for multi-link 4 x 3G ↔ 12G
3Gb/s input
• Configurable Serial Output assignment Example of Multiplexing ST 425-5 into ST 2081-1 (6Gb/s) and
• Configurable multi-link output delay ST 2082-1 (12Gb/s)
• 100Ω Differential Inputs
• Input trace equalization up to 12dB
• Four 100Ω Differential Outputs For the supported SMPTE conversions, the SMPTE ST 352
• Individually selectable output swing payload identification will be automatically detected and
• Reference Clock/Crystal Input — 27MHz replaced based on the user selected conversion mode. This
• GSPI Serial Control and Monitoring Interface can be bypassed for proprietary multiplexing and
• Automatic and manual SMPTE ST 352M handling demultiplexing links.
• 12mm x 12mm 196-Ball BGA (0.8mm pitch)
• Pb-free/Halogen-free/RoHS/WEEE compliant package The device incorporates the ability to reorder the output
serial stream and duplicate outputs to unused output
channels or route any input channel.
Applications
• Next Generation 3D/2D HFR HDTV and 2K D-Cinema, The GS12070 has the ability to automatically compensate
UHDTV1 and 4K D-Cinema end-equipment: Cameras, for up to 400ns of skew between QL 6Gb/s or DL 12Gb/s
Monitors, Switchers, etc. inputs and 800ns of skew between DL 6Gb/s and QL 3Gb/s
• Next Generation 3G-SDI, 6G UHD-SDI, and 12G inputs. This aids in any lane-to-lane variance introduced by
UHD-SDI infrastructures designed in support of
UHDTV1, UHDTV2, 4K D-Cinema and 3D HFR, HDR cable mismatch or upstream routing and distribution
production image formats, and 6G UHD-SDI/12G equipment.
UHD-SDI multiplexing and de-multiplexing for 
integration into legacy infrastructure.
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GS12070 www.semtech.com 1 of 109

Final Data Sheet Rev.6 Semtech
PDS-061012 February 2018 Proprietary & Confidential

VCC_IO VCC_A_1V8 VCC_A_1V1 VCC_CORE VSS
DDI0 Input Video DDO0

Rx Tx
Detection and Status
DDI0 DDO0
DDI1
Input Video DDO1
Rx Tx
Detection and Status
DDI1 MUX/ DDO1
DEMUX
ST 352 & Channel

Reassignment
CRC
DDI2 insertion
Input Video DDO2
Rx Detection and Status Tx
DDI2 DDO2
DDI3
Input Video DDO3
Rx Detection and Status Tx
DDI3
DDO3
ISP[3:0]
XTAL_IN RX_CLK_[3:0]
XTAL_OUT
STAT[15:0]
REFCLK_SEL[1:0] Control, JTAG
GSPI Controller
TIM_OUT[3:0]
RESET
SYS_RESET
TD1
TX_PCLK[1:0]
BYPASS
SD_BYPASS[3:0]
MUX/DEMUX
MODE_SEL[2:0]
PID_MODE[1:0]
SDOUT
SDIN
TMS
TRST
TDO
SCLK
TCK
DEMUX_INPUT_SELECT
SEC_LINK_ENABLE
LINK_ASGMT
CS
REXT_RX
REXT_TX
GS12070 Block Diagram

Revision History
Version ECO Date Changes and/or Modifications
Added Section 3.12.3, PRBS Data Bypass.

6 040676 February 2018 Added Section 3.5.1, DDI CDR Reference Clock
Configuration.
Added Section 2.4, Latency.

Added Section 3.9.3, Input Tx Clock Selection.
Added Section 3.14, Embedded Video Pattern
Generator.
5 035260 January 2017 Added Host Interface Register Map, Section 4.
Added Figure 3-12 GL12G-SL6G Output Link
Assignment.
Added Figure 6-4 GS12070 Marking Diagram
Updated Section 2.2, Section 2.3, Table 6-1
Added Section 3.3.4 on output power down.

Added Section 3.2 on device reset.
4 034133 November 2016
Updated Figure , Table 2-1, Table 2-2, Table 2-3,
Table 3-35
3 034034 October 2016 Updates to add information to Section 3.
Updated pin names in Figure 1-1, Table 1-1,

2 028141 October 2015
Table 3-7, and Table 3-8.
1 026325 June 2015 Minor correction on Page 1.
0 025710 June 2015 New document.
Contents
1. Pin Out.................................................................................................................................................................6
1.1 Pin Assignment ...................................................................................................................................6
1.2 Pin Descriptions ..................................................................................................................................7
2. Electrical Characteristics............................................................................................................................. 11
2.1 Absolute Maximum Ratings ........................................................................................................ 11
2.2 DC Electrical Characteristics ........................................................................................................ 11
2.3 AC Electrical Characteristics ......................................................................................................... 14
2.4 Latency ................................................................................................................................................ 15
3. Detailed Description.................................................................................................................................... 16
3.1 Power Supply Considerations ..................................................................................................... 16
3.1.1 Power Connections ............................................................................................................ 16
3.1.2 Power On Sequence........................................................................................................... 16
3.1.3 Device Initialization ............................................................................................................ 17
3.2 Power On Reset ................................................................................................................................ 17
3.3 Serial Data Inputs ............................................................................................................................. 18
3.3.1 Input Signal Interface Levels ........................................................................................... 18
3.3.2 Input Trace Equalization ................................................................................................... 18

3.3.3 Input Signal Present ........................................................................................................... 19
3.3.4 Input Power-Down ............................................................................................................. 19
3.4 Serial Data Outputs ......................................................................................................................... 19
3.4.1 DDO Output Swing............................................................................................................. 19
3.4.2 Output Idle............................................................................................................................. 20
3.4.3 Output Power-Down.......................................................................................................... 20
3.4.4 Output Driver Disable........................................................................................................ 22
3.5 Reference Clock ................................................................................................................................ 22
3.5.1 DDI CDR Reference Clock Configuration .................................................................... 22
3.6 Digital I/O ........................................................................................................................................... 23
3.7 Modes of Operation ........................................................................................................................ 23
3.7.1 Operating Mode Selection............................................................................................... 23
3.8 Input Serial Receiver and Input Processing Operation ...................................................... 24
3.8.1 Input Data Rate .................................................................................................................... 24
3.8.2 Input Loop Bandwidth ...................................................................................................... 25
3.8.3 Automatic Skew Tolerance .............................................................................................. 26
3.8.4 Status Reporting .................................................................................................................. 26
3.9 Serial Transmitter Operation ....................................................................................................... 28
3.9.1 Output Assignment ............................................................................................................ 28
3.9.2 Output Loop Bandwidth................................................................................................... 29
3.9.3 Transmitter Input Clock Selection................................................................................. 30
3.10 Multiplex Mode .............................................................................................................................. 30
3.10.1 Conversion Selection....................................................................................................... 30
3.10.2 Multiplexing Paths............................................................................................................ 32
3.10.3 SMPTE Compatibility ....................................................................................................... 33
3.10.4 Lost Input............................................................................................................................. 33
3.10.5 Automatic Input Link Ordering.................................................................................... 34
3.10.6 MUX Manual Input Channel Assignment................................................................. 34
3.11 Demultiplex Mode ........................................................................................................................ 35
3.11.1 Conversion Selection....................................................................................................... 35
3.11.2 Demultiplexing Paths...................................................................................................... 37
3.11.3 SMPTE Compatibility ....................................................................................................... 39
3.11.4 Lane Delay ........................................................................................................................... 39
3.11.5 DeMUX Output Link Assignment................................................................................ 40
3.12 Bypass Mode ................................................................................................................................... 42
3.12.1 Input Stream Data Rate Detection.............................................................................. 42
3.12.2 SD Bypass Mode ................................................................................................................ 42
3.12.3 PRBS Data Bypass.............................................................................................................. 42
3.13 Payload ID Handling .................................................................................................................... 43
3.13.1 Detection of Payload ID.................................................................................................. 43
3.13.2 Automatic Insertion of Payload ID.............................................................................. 46
3.13.3 Manual Insertion of Payload ID.................................................................................... 49
3.14 Embedded Video Pattern Generator ..................................................................................... 52
3.15 GSPI Host Interface ....................................................................................................................... 54
3.15.1 CS Pin..................................................................................................................................... 54
3.15.2 SDIN Pin................................................................................................................................ 55
3.15.3 SDOUT Pin ........................................................................................................................... 55

3.15.4 SCLK Pin................................................................................................................................ 56
3.15.5 Command Word 1 Description .................................................................................... 57
3.15.6 GSPI Transaction Timing ................................................................................................ 59
3.15.7 Single Read/Write Access............................................................................................... 61
3.15.8 Auto-increment Read/Write Access ........................................................................... 62
3.15.9 Setting a Device Unit Address...................................................................................... 62
3.15.10 Default GSPI Operation ................................................................................................ 63
4. Host Interface Register Map...................................................................................................................... 64
4.1 Control Registers ............................................................................................................................. 64
4.2 Register Descriptions ..................................................................................................................... 67
4.2.1 GS12070 Control and Status Register.......................................................................... 67
4.2.2 Rx Control and Status Register ....................................................................................... 93
4.2.3 Tx Control and Status Registers ..................................................................................... 95
4.2.4 Video Pattern Generator Control Registers ............................................................... 99
5. Application Information...........................................................................................................................103
5.1 Typical Application Circuit .........................................................................................................103
6. Package & Ordering Information ..........................................................................................................105
6.1 Package Dimensions ....................................................................................................................105
6.2 Recommended PCB Footprint ..................................................................................................106
6.3 Packaging Data ..............................................................................................................................106
6.4 Solder Reflow Profile ....................................................................................................................107
6.5 Marking Diagram ...........................................................................................................................107
6.6 Ordering Information ...................................................................................................................108

1. Pin Out
1.1 Pin Assignment

1 2 3 4 5 6 7 8 9 10 11 12 13 14 Legend:
MUX/ MODE_ High-speed differential inputs

A VSS DDO1 DDO1 DDO0 DDO0 VSS BYPASS STAT0 STAT1 STAT2 STAT3 VSS
DEMUX SEL0
High-speed differential outputs
SD_ SD_ SD_ SD_ MODE_ MODE_
B DDO2 VSS VSS VSS VSS STAT4 STAT5 RX_CLK_0
BYPASS0 BYPASS1 BYPASS2 BYPASS3 SEL1 SEL2
Reference clock
C DDO2 VSS VCC_IO RSVD RSVD RSVD RSVD RSVD VSS VSS RSVD STAT6 STAT7 RX_CLK_1 Digital control and
status — Input
Low-speed digital control and
D DDO3 VSS VCC_IO RSVD RSVD VCC_IO RSVD RSVD VSS VCC_IO RSVD STAT8 STAT9 RX_CLK_2 status (static) — Output
Clock and Timing — Output

E DDO3 VSS VCC_A_1V8 VCC_A_1V1 RSVD RSVD VSS VSS RSVD RSVD RSVD STAT10 STAT11 RX_CLK_3
VCC
F VSS VSS RSVD SYS_RESET NC NC VCC_CORE VSS VSS VSS RSVD STAT12 STAT13 TIM_OUT0
1.8V supply
XTAL_
G VSS VCC_A_1V8 VCC_A_1V1 VSS VCC_CORE VSS VCC_CORE VSS VCC_CORE RSVD STAT14 STAT15 TIM_OUT1
IN 1.1V supply
XTAL_ PID_ I/O supply

H VSS VCC_A_1V8 VCC_A_1V1 VSS VCC_CORE VSS VCC_CORE VSS VCC_IO RSVD RSVD TIM_OUT2
OUT MODE0
GND
J PID_
VSS VSS REXT_TX RSVD NC NC VCC_CORE VSS VSS VSS RSVD RSVD TIM_OUT3
MODE1
RESET
LINK_
K DDI3 VSS VCC_A_1V8 VCC_A_1V1 NC NC VSS VSS RSVD RSVD RSVD RSVD RESET
ASGMT
SEC_LINK_ DEMUX_
L DDI3 VSS REXT_RX TMS TRST VCC_IO VSS VSS VSS VCC_IO RSVD RSVD INPUT_
ENABLE
SELECT
M REFCLK_ REFCLK_
DDI2 VSS VCC_IO TDI TDO TCK VSS VSS RSVD RSVD CS RSVD
SEL0 SEL1
N
DDI2 VSS VSS VSS VSS RSVD VSS VSS VSS ISP0 ISP1 ISP2 ISP3 SCLK
P VSS DDI1 DDI1 DDI0 DDI0 RSVD REF_IN REF_OUT VSS TX_PCLK0 TX_PCLK1 SDIN SDOUT VSS
Figure 1-1: Pin Out

1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin Number Name Type Description
A1, A6, A14, B2, B3,

B4, B5, C2, C9, C10,
D2, D9, E2, E7, E8,
F1, F2, F8, F9, F10,
G2, G5, G7, G9, H2,
H5, H7, H9, J1, J2, VSS Power Device ground. Connect to GND.
J8, J9, J10, K2, K7,
K8, L2, L7, L8, L9,
M2, M9, M10, N2,
N3, N4, N5, N7, N8,
N9, P1, P9, P14
Selects between Multiplex and Demultiplex mode.

A7 MUX/DEMUX Digital Input This pin has an internal pull-down resistor.
This function can be overridden by the CSR.
When HIGH, BYPASS is active and all inputs pass data directly to
the outputs.
When LOW, multiplexing/demultiplexing occurs as programmed
A8 BYPASS Digital Input by the MODE_SEL and PID_MODE pins.
This pin has an internal pull-down resistor.
Selects the SD data rate per channel when in Bypass mode.

When HIGH, SD_BYPASS is active.
B9, B8, B7, B6 SD_BYPASS[3:0] Digital Input SD_BYPASS is only available when BYPASS is set to 1.
These pins have an internal pull-down resistor.
Multiplex or Demultiplex conversion mode selection. See Table

3-16: MUX Mode Up Conversion and Table 3-19: DeMUX Mode
B11, B10, A9 MODE_SEL[2:0] Digital Input Down Conversion.
These pins have internal pull-up resistors.
C3, D3, D6, D10,

VCC_IO Power Power supply connection for the I/O. Connect to 1.8V.
H10, L6, L10, M3
C4, C5, C6, C7, C8,

C11, D4, D5, D7,
D8, D11, E5, E6, E9,
E10, E11, F3, F11,
RSVD — These pins are reserved, do not connect.
G11, H11, H12, J4,
J11, J12, K9, K10,
K11, K12, L11, L12,
M11, M12, M14, P6

Table 1-1: Pin Descriptions (Continued)
D1, E1 DDO3, DDO3

B1, C1 DDO2, DDO2
Output Differential serial digital outputs.
A3, A2 DDO1, DDO1
A5, A4 DDO0, DDO0
E3, G3, H3, K3 VCC_A_1V8 Power Power supply connection for Analog 1V8. Connect to 1.8V.
E4, G4, H4, K4 VCC_A_1V1 Power Power supply connection for Analog 1V1. Connect to 1.1V.
The extracted parallel clock from the respective DDI/DDI input

E14, D14, C14, B14 RX_CLK_[3:0] Output
data.
F5, F6, J5, J6, K5, K6 NC — No connect. Pins are not connected internally.
Restarts the power-on initialization sequence.

When asserting, the device state goes to reset.
When de-asserted, the power-on initialization will restart.
F4 SYS_RESET Input When asserting this function, the power supplies must be at their
final stable values.
This pin is active LOW and has an internal pull-up resistor.
The minimum reset pulse duration is 1ms.
F7, G6, G8, G10,

VCC_CORE Power Power supply connection for the core. Connect to 1.1V.
H6, H8, J7
Device reference clock connection.

G1 XTAL_IN
Analog Note: Connection of an external clock or crystal is dependent on
H1 XTAL_OUT
the configuration of REFCLK_SEL pins.
G13, G12, F13, F12,

E13, E12, D13, D12, Multi-function status outputs. Please refer to the CSR document,
STAT[15:0] Digital Output
C13, C12, B13, B12, registers STAT_CH0 through STAT_CH3 for selection description.
A13, A12, A11, A10
SMPTE compliant Multiplex/Demultiplex mode.

When LOW, the input signal’s ST 352 payload identifier, in
combination with the setting of MODE_SEL will be used to
determine the output signal’s ST 352 payload identifier values.
J13, H13 PID_MODE[1:0] Digital Input
When HIGH, the input signal’s ST 352 payload identifier is not
used.
These pins are active LOW and have internal pull-down resistors.
REXT_TX Calibration resistors for high-speed inputs and outputs. Connect

J3, L3 Analog
REXT_RX 1.0kΩ±1% resistor to GND.
Extracted horizontal timing – Rx H blanking from the

J14, H14, G14, F14 TIM_OUT[3:0] Output
corresponding input.
K1, L1 DDI3, DDI3 Serial digital differential input.

M1, N1 DDI2, DDI2
Input Unused Inputs should be left unconnected. In order to save
P2, P3 DDI1, DDI1
P4, P5 DDI0, DDI0 power it is recommended to power down unused inputs.

Multi-link input order handling.

When HIGH the input order is independent of the input
connection order (based on ST 352 embedded PID).
K13 LINK_ASGMT Digital Input When LOW, the output is multiplexed based on the physical input
connection order.
Device reset signal.

When asserting, the device state goes to reset.
K14 RESET Input When de-asserted, the device will be set to its default values.
This pin is active LOW and has an internal pull-up resistor.
The minimum reset pulse duration is 400ns.
JTAG interface Test Mode Select input. This signal is decoded by

L4 TMS Digital Input the internal TAP controller to control test operations.
JTAG interface reset. Digital active-low reset input. Used to reset

the JTAG test sequence.
When LOW, the JTAG test sequence is reset.
L5 TRST Digital Input
When HIGH, normal operation of the JTAG test sequence
resumes.
This pin is active LOW and has an internal pull-down resistor.
When HIGH the M1/DM1 paths will be enabled.

L13 SEC_LINK_ENABLE Digital Input This function can be overridden by the CSR.
Select between DDI0 and DDI2 in the single link input DeMUX
modes.
Set LOW (default) to select DDI0 as the input.
DEMUX_ Set HIGH to select DDI2 as the input.
L14 Input
INPUT_SELECT This function can be overridden by the CSR.
The selected input must not be powered down and the M1 path
must be enabled. (See pin L13, SEC_LINK_ENABLE).
Note: This pin should be tied to GND if not used.
JTAG interface Test Data Input. Serial instructions and data are
M4 TDI Digital Input received on this pin.
JTAG interface Test Data Output. TDO is the serial output for test
M5 TDO Digital Output
instructions and data.
JTAG interface Test Clock input. The test clock input provides the
M6 TCK Digital Input clock for the test logic of this device.

Reference Clock Selection input. Configures the reference clock

input type and frequency.
Set to 00 for 27MHz crystal.
M8, M7 REFCLK_SEL[1:0] Input
Set to 01 for 27MHz differential clock input.
These pins have an internal pull-down resistor.
Note: REFCLK_SEL must be set correctly at power-up.
Chip Select input for the Gennum Serial Peripheral Interface

M13 CS Digital Input (GSPI) host control/status port. Active-low input.
This pin has an internal pull-up resistor.
N6 RSVD — This pin has an internal pull-down resistor.
Input Signal Present.

Set LOW when the input signal is valid.
Set HIGH when the input signal is not present or invalid. In this
N13, N12, N11,
ISP[3:0] Digital Input mode the input section is in standby mode in order to minimize
N10
power consumption.
These pins are active LOW and have internal pull-down resistors.
GSPI Data Clock input. Burst-mode clock input for the GSPI host
N14 SCLK Digital Input
control/status port.
P7, REF_IN
Digital Input Do not connect these pins.
P8 REF_OUT
Tx input PCLK. These pins are optional and only accept a clock
synchronized to the extracted Rx clock.
P11, P10 TX_PCLK[1:0] Input
Unused pins should be left unconnected.
Please refer to the CSR document for selection setting.
P12 SDIN Digital Input GSPI Digital Data Input for the GSPI host control/status port.
GSPI Digital Data Output for the GSPI host control/status port.
P13 SDOUT Digital Output
Active-high output.

2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Parameter Value
Supply Voltage (VCC_CORE, VCC_A_1V1) -0.5V to 1.54V
Supply Voltage (VCC_IO, VCC_A_1V8) -0.5V to 1.98V
Input ESD Voltage (HBM) 1kV
Input ESD Voltage (CDM) 250V
Storage Temperature Range (Ts) -50°C to +125°C

Operating Temperature Range (TA) -40°C to +85°C
Input Voltage Range (1.8V logic inputs) -0.5V to VCC_IO + 0.5V
Solder Reflow Temperature 260°C

Note: Absolute Maximum Ratings are those values beyond which damage may occur.
2.2 DC Electrical Characteristics

Table 2-2: DC Electrical Characteristics
TA = -40°C to +85°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Notes
VCC_A_1V8 1.71 1.8 1.89 V —
VCC_A_1V1 1.05 1.1 1.16 V —

Supply Voltage
VCC_CORE 1.05 1.1 1.16 V —
VCC_IO 1.71 1.8 1.89 V —
ICC_A_1V8 1.8V operation — 704 826 mA —
ICC_A_1V1 1.1V operation — 211 316 mA —

Supply Current
ICC_CORE 1.1V operation — 456 608 mA —
ICC_IO 1.8V operation — 32 63 mA —
QL 3G SL 12G
Power PD DDI0, DDI1, DDI2, DDI3 — 1767 1962 mW —
enabled
DDO0 enabled

Table 2-2: DC Electrical Characteristics (Continued)
QL 1.5G  SL 6G
DDI0, DDI1, DDI2, DDI3 — 1492 1641 mW —
enabled
DDO0 enabled
QL 6G DL 12G
DDI0, DDI1, DDI2, DDI3 — 1979 2190 mW —
enabled
DDO0, DDO2 enabled
QL 3G DL 6G
DDI0, DDI1, DDI2, DDI3 — 1774 1972 mW —
enabled
DDO0, DDO2 enabled
DL 6G SL 12G
DDI0, DDI2 enabled — 1318 1793 mW —
DDO0 enabled
DL 3G SL 6G
DDO0 enabled
DL 1.5G SL 3G
Power PD
DDO0 enabled
SL 12G  QL 3G
DDI0 enabled — 1231 1250 mW —
DDO0, DDO1, DDO2, DDO3
enabled
SL 6G  QL 1.5G
enabled
DL 12G  QL 6G
enabled
DL 6G  QL 3G
enabled
SL 12G  DL 6G
DDO0, DDO2 enabled

Table 2-2: DC Electrical Characteristics (Continued)
SL 6G  DL 3G
DDO0, DDO2 enabled
Power PD
SL 3G  DL 1.5G
DDO0, DDO2 enabled
Serial Input Common

VCMIN — — 0 — V —
Mode Voltage
Serial Output Common

VCMOUT — — ΔVDDO/2 — V —
Mode Voltage
Serial Input Termination Differential — 95.5 100 104 Ω —
Serial Output Termination Differential — 85 100 115 Ω —
0.65 x VCC_IO
VIH 1.8V operation — V —
VCC_IO +0.3
Input Voltage - Digital Pins
0.35 x
VIL 1.8V operation -0.3 — V —
VCC_IO
VCC_IO
VOH 1.8V operation — — V —
Output Voltage - Digital Pins -0.45
VOL 1.8V operation — — 0.45 V —

2.3 AC Electrical Characteristics
Table 2-3: AC Electrical Characteristics

Serial Input/
DRDDI /DRDDO — 0.27 — 11.88 Gb/s —
Output Data Rate
Upstream Voltage Swing VSDI — 400 — 1000 mVppd —
Minimum Swing Setting — 400 — mVppd 3
Output Voltage Swing VDDO
Maximum Swing Setting — 1000 — mVppd —
2 video
Lock Time - Video tLOCK — — — — —
lines
20% to 80% rising edge
DDO<n> Rise/Fall Time triseDDO<n> 36 50 64 ps —
into 50Ω load (on-chip)
12G 0.2 — — UIpp —
Intrinsic Input  6G 0.4 — — UIpp —

IIJT
Jitter Tolerance 3G 0.5 — — UIpp —
1.5G 0.6 — — UIpp —
12G — 0.35 0.50 UIpp 1,2
12G (QL6G-DL12G) — 0.45 0.55 UIpp 1
Intrinsic Serial
tOJ 6G — 0.20 0.30 UIpp 1
Output Jitter
3G — 0.10 0.15 UIpp 1
1.5G — 0.04 0.05 UIpp 1
1. Measured with a 100kHz filter.
2. Applies to QL3G-SL12G, DL6G-SL12G, and Bypass modes.
3. This is the default swing setting for the GS12070.

2.4 Latency
Device latency depends on the mode of operation. Table 2-4 lists latencies per mode
measured in PCLK periods.
Table 2-4: Latencies Per Mode
Min Latency Typ Latency Max Latency

Mode PCLK [MHz]
[# PCLK Periods] [# PCLK Periods] [# PCLK Periods]
QL3GSL12G 148.5 36 46 56
QLHDSL6G 74.25 36 46 56
QL6GDL12G 148.5 45 59 73
MUX QL3GDL6G 148.5 41 55 69
DL6GSL12G 148.5 36 46 56
DL3GSL6G 148.5 41 51 61
DLHDSL3G 74.25 36 46 56
SL12GQL3G 148.5 33 43 53
SL6GQLHD 74.25 33 43 53
DL12GQL6G 148.5 39 53 67
DeMUX DL6GQL3G 148.5 38 48 58
SL12GDL6G 148.5 33 43 53
SL6GDL3G 148.5 36 46 56
SL3GDLHD 74.25 33 43 53

3. Detailed Description
3.1 Power Supply Considerations
3.1.1 Power Connections
Table 3-1: Power Connections
Parameter Description
VCC_A_1V8 Power supply connection for Analog 1V8
VCC_A_1V1 Power supply connection for Analog 1V1
VCC_CORE Power supply connection for Digital core 1V1
VCC_IO Power supply connection for Digital I/O 1V8
VSS Device common ground
3.1.2 Power On Sequence

The GS12070 does not require power supply sequencing; however the following power
up conditions must be met:
1. The ramp up time of each supply must be within 10μs and 200ms. 
Note: To prevent a latch-up condition the power supplies must not ramp faster
than 10μs.
2. The time from the first power supply starting point to the last power supply end
point must be less than 200ms. See Figure 3-1: Power Ramp Up Time PRAMP.
3. The ramp of each power supply should not have any plateaus or dips. See Figure
3-2: Acceptable Power Supply Ramp.
V
3.0
2.5
>10μs
2.0
1.5 >10μs
1.0
0.5
0.0
PRAMP (200ms) t
Figure 3-1: Power Ramp Up Time PRAMP

V PRAMP
Operating
Voltage
Ideal Ramp
Acceptable Ramp
Not Acceptable Ramp
Figure 3-2: Acceptable Power Supply Ramp
3.1.3 Device Initialization

After power-up the device requires a 900ms delay before GSPI transactions can begin.
3.2 Power On Reset

The GS12070 has a built-in power on reset. After the point of stable power supply levels
have been achieved (Point A in Figure 3-3), device initialization will start. The Device
Initialization phase calibrates and trims the analog portions of the device.
Completion of Device Initialization will take 900ms and the GS12070 CSRs will be
automatically reset (Point B) internally. After the internal reset (Point C) the device will
enter Normal Operation.
Power-up Device Initialization Device Reset Normal Operation
B 400ns
Power On Reset
A 900ms C
Power Supplies Stable Device Ready
Figure 3-3: Device Power Up and Reset Sequencing
The pin SYS_RESET can be used to restart the GS12070 from point A. This can be helpful
if the devices needs a cold restart as this eliminates the need for a power cycle.
When the pin RESET is asserted and released, the Device Reset phase will initiate and will
be ready for normal operation (Point C) after 400ns.

3.3 Serial Data Inputs
3.3.1 Input Signal Interface Levels

The balanced input circuit is compatible with industry standard LVPECL, PECL, CML, and
LVDS.
Input signals must be AC-coupled. A 4.7μF capacitor is recommended.
3.3.2 Input Trace Equalization

The GS12070 features per-channel adjustable trace equalization to compensate for PCB
trace dielectric losses.
For 12Gb/s data rate, the trace equalizer's initial settings can be tuned to one of three
specific trace loss bands. The trace EQ is adaptive within the specified band. To optimize
the trace EQ settings, first the EQ setting value for required loss compensation needs to
be written to INPUT_EQ<n> register and then the DDI<n>_EQ_UPDATE parameter bit
must be asserted. Table 3-2 contains the parameter values for the supported trace EQ
settings.
Table 3-2: Trace Equalizer Settings (Register INPUT_EQ<n>)
Input Data Rate

Trace Loss
Notes
Compensation
12GB/s Register Valueh SD - 6Gb/s Register Valueh
0-4dB Setting 3468 (F468) 1
4-8dB Setting 2C58 (EC58) Setting 3468 (F468) 1
8-12dB Setting 2448 (E448) 1
1. The value in brackets is the value that includes the two update bits (15:14). It is the value that will be read back when updated bits are set
but the EQ settings have not been updated. The first value is the read-back value after the EQ settings have been updated.
The register location for the equalizer settings associated with each input channel is
described in Table 3-3.
Table 3-3: Trace Equalizer Register Locations
Input Channel Register Name Addressh
DDI0 DDI0_EQ_UPDT 1023

3.3.3 Input Signal Present
Each input has an associated active LOW control input pin called ISP which needs to be
driven LOW when a valid input signal is applied. When a valid input signal is not present,
this signal is to be driven HIGH.
The ISP_REG register can also be used to control this signal as well as change its polarity
and report on the state of the ISP[3:0] input pin.
An example of how to use this pin in the application is to connect it to the lock pin of a
reclocker that drives the respective serial input.
In the DeMUX mode, it is recommended to leave the associated ISP<n> HIGH for inputs
that are not used.
3.3.4 Input Power-Down

Inputs that are not intended to be used can be powered down through the host
interface. The DDI_PWR_DOWN registers provide per-lane control of the power down
options.
3.4 Serial Data Outputs

The GS12070 has four serial digital differential data outputs capable of operating at SDI
nominal rates of:
• 12G (11.88Gb/s, and 11.88/1.001Gb/s)
• 6G (5.94Gb/s and 5.94/1.001Gb/s)
• 3G (2.97Gb/s and 2.97/1.001Gb/s)
• HD (1.485Gb/s and 1.485/1.001Gb/s,)
• SD (270MHz)
Each output has a driver capable of driving a 100Ω differential load.
3.4.1 DDO Output Swing

The output swing is set to 400mVpp differential by default.
The swing can be changed by setting the DDO<n>_AMP parameter in the
DDO_DRV_AMP register, as shown in Table 3-4. Once the value is set to the desired
amplitude value for the selected output, set the DDO<n>_DRV_AMP_UPDATE
parameter HIGH for this value to be loaded into the GS12070.

Table 3-4: Output Swing Settings
DDO<n>_AMP Nominal DDO

Valueh Amplitude (mVpp diff )
0 400
1 500
2 600
3 700
4 800
5 900
6 1000
7 400
3.4.2 Output Idle

Serial outputs can be individually set to Idle. When an output is set to Idle, its voltage will
be set to the common mode voltage. These functions are programmed through
DDO_IDLE register.
3.4.3 Output Power-Down

Outputs that are not intended to be used can be powered down through the host
interface. The OUTPUT_PWR_DOWN register provides per-lane control of the power
down options.
The OUTPUT_PWR_DOWN register contains 16 bits, which can be broken down into
four groups of four bits each. Each bit in the group of four bits is assigned to a DDO<n>
output. Thus there are multiple bits required to power down a particular DDO<n>
output. The power-down bit assigned to a DDO<n> output in each four-bit group must
be the same.
Shown in Table 3-6 is an example of the value that is written to enable DDO0 and DDO2,
but disable DDO1 and DDO3. For convenience, Table 3-5 is showing the HEX register
value for all possible combinations of output power down.

Table 3-5: DDO<n> Power-Down Control
Note: Powered down output lanes denoted as PD.
Register DDO DDO DDO DDO

Value Lane 0 Lane 1 Lane 2 Lane 3
0000 Active Active Active Active
1111 Active Active Active PD
2222 Active Active PD Active
3333 Active Active PD PD
4444 Active PD Active Active
5555 Active PD Active PD
6666 Active PD PD PD
7777 Active PD PD PD
8888 PD Active Active Active
9999 PD Active Active PD
AAAA PD Active PD Active
BBBB PD Active PD PD
CCCC PD PD Active Active
DDDD PD PD Active PD
EEEE PD PD PD Active
FFFF PD PD PD PD
Table 3-6: Example of Register Value Required to Power Down DDO1 and DDO3
OUTPUT_PWR_
DOWN [15:12] [11:8] [7:4] [3:0]
Bit Slice
DDO<n> Power
Down DDO0 DDO1 DDO2 DDO3 DDO0 DDO1 DDO2 DDO3 DDO0 DDO1 DDO2 DDO3 DDO0 DDO1 DDO2 DDO3
Bit Assignment
Register Bit
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Value
Register Hex
5 5 5 5
Value

3.4.4 Output Driver Disable
The serial output driver can be disabled. This feature can be used in combination with
Output Power Down to realize additional power savings as the output driver is shut
down.
This function can be programmed through the DDO_DRIVER_DISABLE Register.
3.5 Reference Clock

The GS12070 operates from a single reference clock. It is recommended to use a crystal
with ±30ppm frequency tolerance and has a -40°C to +85°C temperature rating or
better.
Please see 5.1 Typical Application Circuit for recommended crystal connection.
A differential clock can also be connected in place of the crystal. The quality of this
reference clock must be equivalent or better than the crystal as it will impact output
jitter. The differential clock must be AC coupled using a 10nF capacitor.
Table 3-7: Reference Clock Configuration Selection
Reference Clock
Configuration Reference Clock
XTAL_IN/OUT
Selection Frequency
REFCLK_SEL[1:0]
00 Crystal 27MHz
01 Differential Clock 27MHz
10
Not Supported
11
3.5.1 DDI CDR Reference Clock Configuration

The GS12070 DDI CDR quad has two configuration options for high-speed clock
generation from the reference clock.
The default DDI CDR configuration (on power-up) has slightly lower power
consumption than the alternative CDR configuration, but the alternative CDR
configuration is superior in jitter performance, IJT and power noise immunity to the
default one.
The alternative CDR configuration can be selected in the initialization process after the
power-up by writing a few registers. For more information please see the Application
Note “GS12070 - Reducing jitter with different DDI CDR clocking configurations.”

3.6 Digital I/O
The digital I/O pins must be interfaced at 1.8V LVCMOS logic levels.
3.7 Modes of Operation

The GS12070 operates in three distinctive modes:
• MUX (Multiplex)
• DeMUX (De-Multiplex)
• Bypass (Input to Output)
3.7.1 Operating Mode Selection

The pins, MUX/DEMUX, and BYPASS configure the operating mode of the device.
In BYPASS mode, the device automatically searches for the data-rates, 12G, 6G, 3G, and
HD at the input. Operation at SD (270Mb/s) must be manually set using the SD_BYPASS
pin. This selection is available per lane and only active when the device is in BYPASS
mode. When BYPASS mode is selected, the MUX/DEMUX pin is ignored.
The settings for mode selection are described in Table 3-8. The default pin settings for
the GS12070 mode selection is set to DeMUX mode through a pull-down resistor.
Alternatively, mode selection can be set through the OPEARTING_MODE_SEL_REG
registers in the CSR.
Note: Register control of the MUX_DEMUX, MODE_SEL, PID_MODE and BYPASS
parameters are grouped. All three functions must either be pin controlled or register
controlled through REG_CTRL_OP_MODE_EN.
Table 3-8: Operating Mode Selection
Pin
Mode
MUX/DEMUX BYPASS SD_BYPASS
0 0 0 DeMUX
1 0 0 MUX
X 1 0 Bypass
SD Bypass (only available

X 1 1
when BYPASS = 1)

3.8 Input Serial Receiver and Input Processing Operation
3.8.1 Input Data Rate

The data rate at the input is automatically configured when a specified MUX or DeMUX
mode is selected. The maximum data rate supported for each DDI<n> input is shown in
Table 3-9.
Table 3-9: Serial Data Input Supported Data Rates
MODE
Input
MUX DEMUX BYPASS
— 12Gb/s 12Gb/s
6Gb/s 6Gb/s 6Gb/s
DDI0 3Gb/s 3Gb/s 3Gb/s
1.5Gb/s — 1.5Gb/s
— — 270Mb/s
— — 12Gb/s
6Gb/s — 6Gb/s
DDI1 3Gb/s — 3Gb/s
1.5Gb/s — 1.5Gb/s
— — 270Mb/s
— 12Gb/s 12Gb/s
6Gb/s 6Gb/s 6Gb/s
DDI2 3Gb/s 3Gb/s 3Gb/s
1.5Gb/s — 1.5Gb/s
— — 270Mb/s
— — 12Gb/s
6Gb/s — 6Gb/s
DDI3 3Gb/s — 3Gb/s
1.5Gb/s — 1.5Gb/s
— — 270Mb/s
In the case of the BYPASS mode, the device by default searches for the data-rates, 12G,
6G, 3G, and HD at the input. If a valid SDI signal is found, and lock is achieved, the data
rate will be reported (per input) in the parameters within the DATA_RATE_REPORT
register as a two bit value. Table 3-10 describes the reported data rates and their
parameter values. Note that SD is not reported as it must be set manually.
In BYPASS mode, the SD rate is not automatically detected and must be manually set for
each individual input. This can be achieved by asserting the SD_BYPASS[3:0] pins or
through the host interface using the SD_BYPASS_SEL_REG register.
The automatic data rate detection can be overridden and can be manually set through
the MANUAL_RATE register. A parameter is available for each individual input.
Table 3-10 applies for both reported data rate and the manual setting of the data rate.

Table 3-10: Data Rate Register Values for Setting and Reporting
Nominal Register
Data Rate Valueb
12G 11
6G 10
3G 01
HD 00
3.8.2 Input Loop Bandwidth

The loop bandwidth of the input is individually configured on a per channel basis. The
default loop bandwidth is optimized and it is not recommended that this value be
changed.
There may be specific cases where the input loop bandwidth needs adjustment. This
can be set through the DDI_CDR_LBW.
SeeTable 3-11 for CDR LBW settings.
Table 3-11: CDR Bandwidth Settings
Data Rate CDR Bandwidth Bandwidth (MHz) CDR Lock to Data Time (μs)
Low 3.26 5.2
12Gb/s Recommended 4.88 4.4
High 5.58 4.1
Low 1.22 9.3
High 4.88 4.4
Low 0.61 18.6
High 2.44 8.7
Low 0.31 37.1
1.5Gb/s Recommended 0.41 30.6
High 1.22 17.5

3.8.3 Automatic Skew Tolerance
The GS12070 automatically adjusts for skew between multi-link inputs. Table 3-12 lists
the maximum skew supported for the various MUX/DeMUX modes.
Table 3-12: Input Skew Compensation
Mode Conversion Time of Skew
DL 6Gb/s SL 12Gb/s 800ns

DL 3Gb/s SL 6Gb/s 800ns
DL 1.5Gb/s SL 3Gb/s 1600ns
QL 3Gb/s SL 12Gb/s 800ns

QL 3Gb/s SL 6Gb/s 800ns
QL 1.5Gb/s SL 6Gb/s 1600ns
DL 6Gb/s QL 3Gb/s 800ns
DL 12Gb/s QL 6Gb/s 400ns

QL 6Gb/s DL 12Gb/s 400ns
3.8.4 Status Reporting

The GS12070 has status monitoring of the following parameters
• LOCK
• PID ERROR
• PID DETECTED
• TRS ERROR
• CRC ERROR
• DATA RATE
• INTERLEAVED INPUT STREAM
Table 3-13 describes the parameter and the register that reports that parameter.

Table 3-13: Input Status Reporting Parameters
Reporting Register
Description STAT Output Pin Availability
Parameter Name
Asserts when the input has locked to the input data

INPUT_ rate and detect three TRS sequences within a 2.5 line
LOCK window.
LOCK_REG
LOCK is available for each individual input
Asserts when the PID embedded in the input stream

does not match the expected PID value. STAT[15:12] - DDI 3
PID ERROR PID_ERROR STAT[11:8] - DDI 2
PID ERROR Indication is available for each of the
individual data streams and for each individual input. STAT[7:4] - DDI 1
STAT[3:0] - DDI 0
Asserts when the PID is inserted in the input stream.
PID_ Assignment to STAT pin is set
PID DETECTED PID DETECTED Indication is available for each of the
DETECTED through STAT_CH[3:0] registers
individual data streams and for each individual input.
Asserts when the received TRS's protection bit is

incorrect.
TRS ERROR NA
TRS_PERR indication is available or each of the
individual data streams and for each individual input.
Asserts when a CRC error has been detected at inputs.

CRC ERROR CRC_ERROR This register is a logical OR of each DDI CRC error, if
detected.
DATA_RATE_ Indicates the data rate on the DDI[3:0] inputs, two bits
DATA RATE
REPORT per input. NA
Indicates that the input video stream is interleaved
VID_STREAM_ when HIGH.
INTERLEAVED
INTERLEAVED_
INPUT STREAM One bit per stream, two streams per input.
STAT
Note: See Figure 3-4: Input Data Stream Paths.
Video
Processing
DDI0 DDI0_DS1
Rx
DDI0_DS2
DDI1_DS1
DDI1 Rx
DDI1_DS2
DDI2 DDI2_DS1
Rx
DDI2_DS2
DDI3 DDI3_DS1
Rx
DDI3_DS2
Figure 3-4: Input Data Stream Paths

3.9 Serial Transmitter Operation
3.9.1 Output Assignment
3.9.1.1 Default Output Assignments

Default output assignments are configured per mode as listed in Table 3-14.
Table 3-14: Serial Tx Output Assignment
Mode Tx0 Tx1 Tx2 Tx3 Notes
QL3GSL12G M0 M0 (DDO idle) M0 (DDO idle) M0 (DDO idle) —
QLHDSL6G M0 M0 (DDO idle) M0 (DDO idle) M0 (DDO idle) —
QL6GDL12G M0 M0 (DDO idle) M1 M1 (DDO idle) —
MUX QL3GDL6G M0 M0 (DDO idle) M1 M1 (DDO idle) —
DL6GSL12G M0 M0 (DDO idle) M1 M1 (DDO idle) 1
DL3GSL6G M0 M0 (DDO idle) M1 M1 (DDO idle) 1
DLHDSL3G M0 M0 (DDO idle) N/A N/A —
SL12GQL3G DM0 DM0 DM0 DM0 —
SL6GQLHD DM0 DM0 DM0 DM0 —
DL12GQL6G DM0 DM0 DM1 DM1 —
DeMUX DL6GQL3G DM0 DM0 DM0 DM0 —
SL12GDL6G DM0 DM0 DM1 DM1 2
SL6GDL3G DM0 DM0 DM1 DM1 2
SL3GDLHD DM0 DM0 N/A N/A —
1. Tx2(M1path) is powered down by default. To use Tx2(M1 path) as a secondary link it must be enabled manually via SEC_LINK_ENABLE pin or
through the CSR. See Figure 3-7 and Section 3.10.2 for further details.
2. Tx2(DM1 path) and Tx3(DM1path) are powered down by default. To use Tx2(DM1 path) and Tx3(DM1 path) as a secondary link they must be
enabled manually via SEC_LINK_ENABLE pin or through the CSR. See Figure 3-10 and Section 3.11.2 for further details.
3.9.1.2 Manual Output Assignment

Each output can be assigned to:
• Multiplexed streams in MUX mode (M0 or M1 processed output)
• Demultiplexed streams in DeMUX mode (DM0 or DM1 processed output)
• Any of the four input channels
This feature is available in any mode, regardless of the default assignment of the serial
output. Assignment of the output is configured through the OUTPUT_ASGMT_
DDO<n> and enabled through the REG_CTRL_OUTPUT_ASGMT_EN register.

Note: Custom output assignments will be retained, even if the mode is changed. To
return to the default output assignment, the register REG_CTRL_OUTPUT_ASGMT_EN
should be set back to “0”.
OUTPUT_ASGMT_DDO<n>
M0 Processed Output
000
M1 Processed Output
DM0_DDO<n>
DM1_DDO<n>
DDI0 DDO<n>
DDI1
DDI2
DDI3
111
Figure 3-5: Output Assignment Selection
3.9.2 Output Loop Bandwidth

The loop bandwidth of the output is individually configured on a per output basis. The
default loop bandwidth should be configured based on the requirements of the device
connected to the DDO[3:0] serial outputs.
The loop bandwidth can be set through the DDO_LBW register and will take effect
when the DDO_LBW_UPDT register has been written to. Please refer to Table 3-15.
Table 3-15: DDO Loop Bandwidth Setting
DDO_LBW_ 12G LBW 6G LBW 3G LBW 1.5G LBW

SETTINGSh (MHz) (MHz) (MHz) (MHz)
0 RSVD
1 0.13 0.13 0.13 0.13
2 0.25 0.25 0.25 0.25
3 0.5 0.5 0.5 0.5
4 1.01 1.01 1.01 1.01
5 2.01 2.01 2.01 2.01
6 4.03 4.03 4.03 2.01
7 8.06 8.06 8.06 2.01
8 16.11 16.11 8.06 2.01
9 32.33 16.11 8.06 2.01
A to F RSVD

3.9.3 Transmitter Input Clock Selection
By default, the Tx PLL input clock is selected by the internal control block from the
receiver's extracted clocks.
In the MUX or DeMUX mode of operation, the following receiver's clocks will be
selected:
• RX0_CLK (from DDI0 input) — if M0 or DM0 data are selected as input to the
transmitter (all QLSL, QLDL muxing/demuxing modes and DLSL modes for
M0/DM0 paths)
• RX2_CLK (from DDI2 input) — if M1 or DM1 data are selected as input to the
transmitter (DLSL modes for M1/DM1 paths)
In Bypass Mode, the Tx PLL input clock is taken from the receiver (DDI input) which is
connected to the transmitter.
Tx<n> PLL clock selection can be changed through TX_REF_CLK_SEL register.
Selection is enabled by 
TX_REF_CLK_CTLR[n] parameter and a clock source is selected through
TX<n>_REF_CLK_SEL parameter.
Additionally an external clock from the pins TX_PCLK0 and TX_PCLK01 can be selected
as the Tx<n> PLL clock input through the register TX_EXT_REF_CLK_SEL. The external
clock is selected through TX<n>_EXT_REF_CLK_EN and the parameter
TX0_EXT_REF_CLK_SEL selects between clocks from and TX_PCLK0 and TX_PCLK1.
Note: The external clock has to be frequency locked to the input data.
TX_REF_CLK_CTLR[n]
TX<n>_REF_CLK_INTERNAL_SEL[1:0]
0
TX<n>_REF_CLK_SEL[1:0] 1
TX<n>_EXT_REF_CLK_EN
RX0_CLK
00
RX1_CLK
TX<n>_PCLK_INT
RX2_CLK
RX3_CLK
11
0 TX<n>_PCLK
TX<n>_EXT_REF_CLK_SEL 1
0 TX<n>_PCLK_EXT
1
TC_PCLK0 TC_PCLK1
pin pin
Figure 3-6: Tx PLL Input Clock Selection Block
3.10 Multiplex Mode
3.10.1 Conversion Selection

In MUX mode, conversion modes are illustrated in Figure 3-7.
The conversion mode can be set through the MODE_SEL[2:0] pins.

The OPERATING _MODE_SEL _REG register can also be used to select the conversion
mode and override the pin settings. The MODE_SEL parameter is used to set the mode
and the REG_CTRL_MODE_SEL_EN parameter is used to enable the pin override.
The mode selection settings are listed in Table 3-16.
Table 3-16: MUX Mode Up Conversion
Pins MUX Mode Notes

(Refer to
MUX/DEMUX MODE_SEL2 MODE_SEL1 MODE_SEL0 Input Output Figure 3-7)
1 1 1 1 QL 3Gb/s SL 12Gb/s (a)
1 1 1 0 QL 1.5Gb/s SL 6Gb/s (b)
1 1 0 1 QL 6Gb/s DL 12Gb/s (c)
1 1 0 0 QL 3Gb/s DL 6Gb/s (d)
1 0 1 1 DL 6Gb/s SL 12Gb/s (e)
1 0 1 0 DL 3Gb/s SL 6Gb/s (f )
1 0 0 1 DL 1.5Gb/s SL 3Gb/s (g)
1 0 0 0 RSVD RSVD —
QL3G → SL12G QLHD → SL6G DLHD → SL3G

3Gb/s 12Gb/s 1.5Gb/s 6Gb/s 1.5Gb/s 3Gb/s
3Gb/s 1.5Gb/s 1.5Gb/s
3Gb/s 1.5Gb/s
3Gb/s 1.5Gb/s
The system accepts quad 3Gb/s input signals The system accepts quad 1.5Gb/s input signals
and drives a single link 12Gb/s output signal. and drives a single link 6Gb/s output signal. The system accepts dual link 1.5Gb/s input signals
The 12Gb/s signal is outputted from DDO0 by The 6Gb/s signal is outputted from DDO0 by on DDI0 and DDI1 inputs and drives single link
default but can be set to output from any pin. default but can be set to output from any pin. 3Gb/s output signals. The 3Gb/s signals is outputted
(a) (b) from DDO0 by default , but can be set to output
from any pins.
(g)
QL6G → DL12G QL3G → DL6G
6Gb/s 12Gb/s 3Gb/s 6Gb/s
6Gb/s 3Gb/s
6Gb/s 3Gb/s
The system accepts quad 6Gb/s input signals The system accepts quad 3Gb/s input signals
and drives 12Gb/s dual link output signals. and drives dual link 6Gb/s output signals. The
The 12Gb/s signals are outputted from 6Gb/s signals are outputted from DDO0 and DDO2
DDO0 and DDO2 by default, but can be set to by default, but can be set to output from any pin.
output from any pin.
(c) (d)
2x DL6G → 2x SL12G 2x DL3G → 2x SL6G

6Gb/s 3Gb/s
6Gb/s 12Gb/s 3Gb/s

6Gb/s
6Gb/s 3Gb/s
The system accepts two independent dual link 6Gb/s The system accepts two independent dual link 3Gb/s
input signals and drives two single link 12Gb/s output input signals and drives two single link 6Gb/s output
signals. The 12Gb/s signals are outputted from DDO0 signals. The 6Gb/s signals are outputted from DDO0
and DDO2 by default, but can be set to output from and DDO2 by default, but can be set to output from
any pins. any pins.
(e) (f)
Figure 3-7: Multiplex Conversion Modes

Note:
• In Figure 3-7 e) and f ), solid coloured inputs use path M0 and gradient coloured
inputs use path M1. See Section 3.10.2 for further details.
• In order to enable DL 1.5Gb/s to SL 3Gb/s conversion, it is required to set additional
registers (See Table 3-17).
Table 3-17: DL 1.5Gb/s to SL 3Gb/s conversion
Addressh Datah
16 3
13 1
65 92
64 2D48
3.10.2 Multiplexing Paths

The MUX modes will enable one of two paths based on the selected conversion mode.
For quad link inputs the M0 path is used.
For dual link inputs both M0 and M1can be used based on the application requirement.
By default M1 is powered down. To enable the M1 path, the pin SEC_LINK_ENABLE
should be driven HIGH.
Alternatively, the parameter SEC_LINK_REG within the OPERATING_MODE_SEL_REG
register can be used. The parameter REG_CTRL_SEC_LINK_EN is used to override the
pin control and enable the register selection of this feature.
Mux M0
DDI0
DDI1 Virtual M0
UHD
Interface MUX PROCESSED
DDI2 V0 OUTPUT
DDI3
Mux M1
Virtual UHD M1
Interface MUX PROCESSED
V1 OUTPUT
Figure 3-8: Multiplexing Paths

3.10.3 SMPTE Compatibility
Table 3-18 outlines the conversion mappings that are compatible to the SMPTE UHD
standards.
If PID_MODE pin is set to ‘1’ the input streams will be multiplexed according to the
mappings defined by the SMPTE UHDTV standards. The payload identifiers will be
passed to the output unchanged, as received. The Payload ID can be inserted manually,
if required.
The Payload ID will not be inserted for the DL 1.5Gb/s to SL 3Gb/s conversion regardless
of the PID_MODE pin setting. For the DL 1.5Gb/s to SL 3Gb/s conversion, the user needs
to manually insert PIDs.
Table 3-18: MUX Mode SMPTE Compatibility
MUX Mode Supported SMPTE Mapping
Input Output Input Mapping Output Mapping
QL 1.5Gb/s SL 6Gb/s ST274 – 30/25/24 FR, progressive ST2081-10 2160-line Mode 1
ST425-3 1080-line Level A Mapping ST2081-10 1080-line Mode 2

DL 3Gb/s SL 6Gb/s ST425-3 1080-line Level B DL Mapping —
ST425-3 2160-line Mapping ST2081-10 2160-line Mode 1

QL 3Gb/s DL 6Gb/s
ST425-5 2160-line Level B Mapping See Note below

QL 3Gb/s SL 12Gb/s
ST425-5 2160-line Level B Mapping See Note below
ST2081-11 2160-line Mode 1 ST2082-10 2160-line Mode 1

DL 6Gb/s SL 12Gb/s

QL 6Gb/s DL 12Gb/s
Note: For QL Level B mapping, the device will not convert input from Level B mapping
to a Level A mapping. 
QL Level B streams will be multiplexed as DS8-DS4-DS6-DS2-DS7-DS3-DS5-DS1. The
SL12G output will not be compatible with a SL12G input that has been mapped per
ST2081-11 2160-line Mode 1. A second GS12070 can be used to demultiplex SL12G
mapped data streams in QL3G Level B mapping.
3.10.4 Lost Input

In MUX mode, if the GS12070 fails to detect LOCK on an input, the primary input is
copied to the missing input(s). By default, DDI0 is the primary channel. This function is
enabled on all inputs.
The LOST_INPUT _IGNORE_CTRL register allows for customization of this feature.

The primary input to be re-defined, can be configured through the M0_PRIM_CH
parameter for Quad-Link inputs and Dual-Link inputs appearing on DDI1:0]. For
Dual-Link inputs appearing on DDI[3:2] this feature is not supported.
The feature can be disabled on a per-input basis through the IGNORE_LOST_INPUT
parameter.
3.10.5 Automatic Input Link Ordering

The SMPTE multi-link standards, define the Link numbers within Byte 4 of the SMPTE ST
352M Payload ID.
By default, the GS12070 will associate the Link number with the respective DDI<n>
input:
• Input on DDI0 is treated as Link 1
• Input on DDI3 is treated as Link 4
The GS12070 can use the Payload ID to identify the Link number and disassociate the
Link number with the DDI<n> inputs and multiplex the Input in the correct SMPTE
defined order. To enable this function, the LINK_ASGMT pin must be set to logic HIGH.
Alternatively this can be set through the VI_ASGMT_0 register using the
LNK_ASGMT_SEL parameter. The parameter REG_CTRL_LNK _ASGMT_SEL_EN can
be used to override the pin setting.
3.10.6 MUX Manual Input Channel Assignment

In cases where the PID is not defined, incorrect, or missing, the input can be manually
rearranged into the UHD multiplexer. The virtual interface allows manual reassignment
of an input.
Manual input assignment can be enabled through the parameter
MANUAL_CTRL_LNK_ASGMT parameter in the VI_ASGMT_0 register for M0 and M1
path.
For the M0 path, VI0_CH<n>_SEL parameter can be used to select which input is
assigned to each channel container.
For the M1 path, VI1_CH<n>_SEL parameter can be used to select which input is
assigned to each channel container.

VI0_CH0_SEL Virtual Interface V0
DDI0
Input DDI1
DDI0
Processing DDI2
DDI3
VI0_CH1_SEL CH0_DS1 VI_DS1

DDI0 CH0_DS2 VI_DS2
DDI1
DDI1 Input
DDI2
Processing CH1_DS1 VI_DS3
DDI3
CH1_DS2 VI_DS4
VI0_CH2_SEL To UHD
MUX0
CH2_DS1 VI_DS5
DDI0
Input DDI1 CH2_DS2 VI_DS6
DDI2 DDI2
Processing
DDI3
CH3_DS1 VI_DS7
VI0_CH3_SEL CH3_DS2 VI_DS8
DDI0
Input DDI1
DDI3
Processing DDI2
DDI3
Virtual Interface V1
VI1_CH0_SEL
DDI2
CH2_DS1 VI_DS1
DDI3
CH2_DS2 VI_DS2
To UHD
VI1_CH1_SEL MUX1
CH3_DS1 VI_DS3
DDI2
DDI3 CH3_DS2 VI_DS4
Figure 3-9: Virtual Interface
3.11 Demultiplex Mode
3.11.1 Conversion Selection

In DeMUX mode, conversion modes are illustrated in Figure 3-10.
The conversion mode can be set through the MODE_SEL[2:0] pins. The OPERATING
_MODE_SEL _REG register can also be used to select the conversion mode and override
the pin settings. The MODE_SEL parameter is used to set the mode and the
REG_CTRL_MODE_SEL_EN parameter is used to enable the pin override.
The mode selection settings are listed in Table 3-19.

Table 3-19: DeMUX Mode Down Conversion
Pins DeMUX Mode Notes

(Refer to
MUX/DEMUX MODE_SEL2 MODE_SEL1 MODE_SEL0 Input Output Figure 3-10)
0 1 1 1 SL 12Gb/s QL 3Gb/s (a)
0 1 1 0 SL 6Gb/s QL 1.5Gb/s (b)
0 1 0 1 DL 12Gb/s QL 6Gb/s (c)
0 1 0 0 DL 6Gb/s QL 3Gb/s (d)
0 0 1 1 SL 12Gb/s DL 6Gb/s (e)
0 0 1 0 SL 6Gb/s DL 3Gb/s (f )
0 0 0 1 SL 3Gb/s DL 1.5Gb/s (g)
0 0 0 0 RSVD RSVD —
SL3G → DLHD
SL12G → QL3G SL6G → QLHD
12Gb/s 3Gb/s 6Gb/s 1.5Gb/s 3Gb/s 1.5Gb/s
3Gb/s 1.5Gb/s 1.5Gb/s
12Gb/s 3Gb/s 1.5Gb/s
3Gb/s 1.5Gb/s
The system accepts a single link 12Gb/s input The system accepts a single link 6Gb/s input
signal and drives quad link 3Gb/s output signals. The system accepts a single link 3Gb/s input signal and
signal and drives quad link 1.5Gb/s output signals.
The 12Gb/s signal is input into DDI0 by default. drives two dual link 1.5Gb/s output signals. The 1.5Gb/s
The 6Gb/s signal can only be inputted into DDI0.
This can be changed to DDI2 through the are assigned to DDO0 and DDO1 by default but can be
secondary link assignment feature. (b) assigned to other two outputs as well.
(a) (g)
DL12G → QL6G DL6G → QL3G

6Gb/s 3Gb/s
6Gb/s 3Gb/s
The system accepts dual link 12Gb/s input The system accepts dual link 6Gb/s input
signals and drives quad link 6Gb/s output signals. signals and drives quad link 3Gb/s output signals.
The 12Gb/s signals can only be inputted into The 6Gb/s signals can only be inputted into
DDI0 and DDI2. DDI0 and DDI2.
(c) (d)
2x SL12G → 2x DL6G 2x SL6G → 2x DL3G
6Gb/s 3Gb/s
6Gb/s 3Gb/s
The system accepts two independent single link The system accepts two independent single link
12Gb/s input signals and drives two dual link 6Gb/s 6Gb/s input signals and drives two dual link 3Gb/s
output signals. The 12Gb/s signals can only be inputted output signals. The 6Gb/s signals can only be inputted
into DDI0 and DDI2. into DDI0 and DDI2.
(e) (f)
Figure 3-10: DeMUX Conversion Modes
Note: In Figure 3-10 e) and f), solid coloured inputs use path DM0 and gradient coloured
inputs use path DM1. See Section 3.11.2 for further details.

3.11.2 Demultiplexing Paths
The DeMUX modes will enable one of two paths based on the selected conversion
mode.
For quad link outputs the DM0 path is used.
For dual link outputs both DM0 and DM1can be used based on the application
requirement. By default DM1 is powered down. To enable DM1, the pin
SEC_LINK_ENABLE should be driven HIGH.
Alternatively, the parameter SEC_LINK_REG within the OPERATING_MODE_SEL_REG
register can be used. The parameter REG_CTRL_SEC_LINK_EN is used to override the
pin control and enable the register selection of this feature.
DeMux DM0
DDI0 UHD Prog. Output DM0

DeMUX Delay Link PROCESSED
DDI2 Assignment
OUTPUT
DeMux DM1
UHD Output DM1

DeMUX Link PROCESSED
Assignment
OUTPUT
Figure 3-11: Demultiplexing Paths

SEL_DM0_VIRT0
DM0_Link1
DM0_DDO0
DM0_DS1 DM0_DS1
DM0 DM0_DS3 DM0_DS3 DM0_Link1
DM0_Link2
DM0_DS2 SEL_DM_DL12_VIR[0] DM0_DS2

Input
DDI0 processing, DM0_DS4 DM0_VIR DM0_DS4 SEL_DM0_VIRT1
1
UHD DM0, DM0_DS5 DM0_DS5 DM0_Link1
DM0_DDO1
DM0_DS7 DM0_DS7 DM0_Link2
Output delay 0
DM0_Link2
DM0_DS6 DM0_DS6
DM0_DS8 DM0_DS8
SEL_DM1_VIRT0
DM1 DM1_DS1 SEL_DM_DL12_VIR[1] DM1_DS1
DM1_DS3 DM1_DS3 DM1_Link1 DM1_Link1
DM1_DDO2
Input DM1_DS2 1 DM1_VIR DM1_DS2 DM1_Link2
DDI2 processing, DM1_DS4
0
DM1_DS4
UHD DM1, DM1_DS5 DM1_DS5
Output delay DM1_DS7 DM1_DS7 DM1_Link2 SEL_DM1_VIRT1
DM1_DS6 DM1_DS6 DM1_Link1
DM1_DDO3
DM1_DS8 DM1_DS8
DM1_Link2
Figure 3-12: DL12G-QL6G Output Link Assignment
Note: Default setting for SEL_DM_DL12_VIR is "10" so that output assignment is:
DDO0 - Link3
DDO1 - Link4
DDO2 - Link1
DDO3 - Link2
Setting register 65h (DM_DL12_VIR) to 55h (SEL_DM_DL12_VIR to 01) will remap the
output order to:
DDO0 - Link1
DDO1 - Link2
DDO2 - Link3
DDO3 - Link4

3.11.3 SMPTE Compatibility
Table 3-20 outlines the conversion mappings that are compatible to the SMPTE UHD
standards.
If PID_MODE pin is set to ‘1’ the input streams will be demultiplexed according to the
mappings defined by the SMPTE UHDTV standards. The payload identifiers will be
passed to the output unchanged, as received. The Payload ID can be inserted manually,
if required.
Table 3-20: DeMUX Mode SMPTE Compatibility
DeMUX Mode Supported SMPTE Mapping
Input Output Input Mapping Output Mapping
SL 6Gb/s QL 1.5Gb/s ST2081-10 2160-line Mode 1 ST274 – 30/25/24 FR, progressive
ST2081-10 1080-line Mode 2 ST425-3 1080-line Level A Mapping

SL 6Gb/s DL 3Gb/s ST425-3 1080-line Level B DL Mapping
ST2081-10 2160-line Mode 1 ST425-3 2160-line Mapping

SL 12Gb/s DL 6Gb/s

DL 12Gb/s QL 6Gb/s ST2082-11 2160-line Mode 2 ST2081-12 2160-line Mode 2
ST-2082-11 2160-line Mode 3 ST2081-12 2160-line Mode 3
3.11.4 Lane Delay

In DeMUX mode, the delay between each output channel can be manually adjusted for
up to:
• 6.8μs in 6.7ns increments for 3G and 6G outputs
• 13.8μs in 13.47ns increments for HD Outputs
The output delay can be enabled through the DM0_DELAY_EN register. Each of the
delay increment steps can be set through the DM0_DELAY_LINK[3:0] parameters.
Note: When the delay block has been enabled, the latency is increased by two PCLK.
By default, each of the links appear on the respective DDO outputs:
• LINK0 appears on DDO0
Note: The DM0_delay block is located before the DeMUX Output Link Assignment
block. If the manual output link assignment feature is used together with the lane delay,
the link with the added delay will be remapped to the selected DDO.

3.11.5 DeMUX Output Link Assignment
By default, the SMPTE multilink outputs are mapped as follows:
Table 3-21: Default Output Assignment of Multilink Standards
Output Quad Link Outputs Dual Link Outputs
DDO0 Link 1 DM0 Link 1
The default output assignment can be custom defined. Manual output link assignment
can be enabled through the parameter REG_CTRL_SEL_DM0_VIRT in the
SEL_DM0_VIRT register for DM0 path.
For the DM1 path, the parameter REG_CTRL_SEL_DM1_VIRT in the SEL_DM1_VIRT
register should be used.
For the DM0 path, SEL_DM0_VIRT<n> parameter can be used to select which link is
assigned to each DDO Output.
For the DM1 path, SEL_DM1_VIRT<n> parameter can be used to select which input is
assigned to each DDO Output.

SEL_DM0_VIRT0
LINK1
LINK2
LINK3 DM0_DDO0
LINK4
DM0_DS1 LINK1 SEL_DM0_VIRT1

DM0_DS2 LINK1
LINK2
DM0_DS3 LINK2 LINK3 DM0_DDO1
LINK4
DM0_DS4
UHD_DM0,
Prog. Delay SEL_DM0_VIRT2
DM0_DS5 LINK3
LINK1
DM0_DS6
LINK2
LINK3 DM0_DDO2
DM0_DS7 LINK4 LINK4
DM0_DS8
SEL_DM0_VIRT3
LINK1
LINK2
LINK3 DM0_DDO3
LINK4
SEL_DM1_VIRT[0]
LINK1
LINK2 DM1_DDO0
SEL_DM1_VIRT[1]
DM1_DS1 LINK1
LINK1
DM1_DS2 LINK2 DM1_DDO1
UHD_DM1
DM1_DS3 LINK2 SEL_DM1_VIRT[2]
DM1_DS4 LINK1
LINK2 DM1_DDO2
SEL_DM1_VIRT[3]
LINK1
LINK2 DM1_DDO3
Figure 3-13: Output Link Assignment Selection

3.12 Bypass Mode
In bypass mode the GS12070 automatically bypasses 12Gb/s, 6Gb/s, 3Gb/s, and 1.5Gb/s
video data from the input to the output.
The input to output assignment by default:
• DDI0 is assigned to DDO0
If required, any of the inputs can be assigned to any of the output using Output
Assignment feature, Section 3.9.1.
Note: When the mode of operation is switched from the BYPASS mode to MUX/DeMUX
mode and vice versa, the CORE_RESET (register RESET_1, 79h) bit has to be toggled.
Alternatively, all the ISP pins can be toggled if there is no GSPI access or if preferred by
the user.
3.12.1 Input Stream Data Rate Detection

In bypass mode, when the input is 1.5G, 3G, 6G, or 12G, the GS12070 is able to
automatically determine each input data rate and reported in DATA_RATE_REPORT
register, in the parameters DATA_RATE_RX<n>.
The data rate can be set manually through the parameter REG_CTRL_MANUAL_RATE
in the MANUAL_RATE register.
3.12.2 SD Bypass Mode

The device is capable of passing through signals serialized as per SMPTE 259 at 270Mb/s
rate in SD Bypass mode only. SD Bypass mode is manually selectable on a per-channel
basis and only available when BYPASS is set HIGH.
The SD_ BYPASS pin can be overwritten via the controls found in the
SD_BYPASS_SEL_REG register.
When in the SD bypass mode, input data is oversampled. The default oversampling data
rate is 3Gb/s. The oversampling introduces periodic jitter, with the p-p value
proportional to the oversampling rate. The jitter can be reduced by increasing the
oversampling rate to 6Gb/s. The oversampling rate can be set to 6Gb/s by setting
SD_BYPASS_ RATE_6G_3Gb, parameter, register SD_BYPASS_ SEL_REG to 1.
3.12.3 PRBS Data Bypass

In the data rate detection process, the data rate detection block searches for TRS data
words in the input data stream. Hence, the GS12070 is able to automatically determine
input data rate only if the input is SDI video. If the input is PRBS data, the GS12070 data
rate has to be set manually to pass data.

In order to pass PRBS data, the following GS12070 registers need to be set:
• address = 6h (MANUAL_RATE) data = depends on the data rate (should always be
written first)
 The register MANUAL_RATE should be set as the following for the different data
rates:
 12G - FFFh
 6G - AAFh
 3G - 55Fh
 HD - Fh
• address = 3h (INPUT_ LOCK_REG) data = FF0h - Input lock overwrite
• address = Ah (DDO_IDLE) data = F00h - Tx power down overwrite
• address = 8h (RSVD) data = F0h - Set internal ready signal HIGH (should always be
written last)
3.13 Payload ID Handling

The GS12070 will automatically detect and replace the appropriate PID based on the
selected mode. PID handling can be disabled through the PID_MODE Pin or the
PID_MODE parameter in the OPERATING _MODE_SEL _REG register.
Note: Register control of the MUX_DEMUX, PID_MODE and BYPASS are grouped. All
three functions must either be Register controlled or pin controlled.
Note: PID handling is not available when the device is in the bypass mode.
3.13.1 Detection of Payload ID

If a Payload ID is detected in the incoming video input, it can be read through the CSR.
Based on the input format,Table 3-22 through Table 3-25 describe the registers where
the Payload ID is stored.

Table 3-22: DeMUX Mode DM0 Payload ID Detected Registers
Input Register SL12QL3 SL6QLHD DL12QL6 SL12DL6 DL6QL3 SL6DL3 SL6DLHD
PID_DET_CH0A_DS1_* DDI0_DS1 DDI0_DS1 DDI0_DS1 DDI0_DS1 DDI0_DS1 DDI0_DS1 NA
PID_DET_CH0A_DS2_* DDI0_DS5 DDI0_DS3 DDI0_DS5 DDI0_DS5 DDI0_DS3 DDI0_DS3 NA

DDI0
PID_DET_CH0B_DS1_* DDI0_DS3 DDI0_DS2 DDI0_DS3 DDI0_DS3 DDI0_DS2 DDI0_DS2 DDI0_DS1
PID_DET_CH0B_DS2_* DDI0_DS7 DDI0_DS4 DDI0_DS7 DDI0_DS7 DDI0_DS4 DDI0_DS4 DDI0_DS2
PID_DET_CH1A_DS1_* DDI0_DS2 NA DDI0_DS2 DDI0_DS2 NA NA NA
PID_DET_CH1A_DS2_* DDI0_DS6 NA DDI0_DS6 DDI0_DS6 NA NA NA

DDI1
PID_DET_CH1B_DS1_* DDI0_DS4 NA DDI0_DS4 DDI0_DS4 NA NA NA
PID_DET_CH1B_DS2_* DDI0_DS8 NA DDI0_DS8 DDI0_DS8 NA NA NA
PID_DET_CH2A_DS1_* NA NA DDI2_DS1 NA DDI2_DS1 NA NA
PID_DET_CH2A_DS2_* NA NA DDI2_DS5 NA DDI2_DS3 NA NA

DDI2
PID_DET_CH2B_DS1_* NA NA DDI2_DS3 NA DDI2_DS2 NA NA
PID_DET_CH2B_DS2_* NA NA DDI2_DS7 NA DDI2_DS4 NA NA
PID_DET_CH3A_DS1_* NA NA DDI2_DS2 NA NA NA NA
PID_DET_CH3A_DS2_* NA NA DDI2_DS6 NA NA NA NA
DDI3
PID_DET_CH3B_DS1_* NA NA DDI2_DS4 NA NA NA NA
Table 3-23: DeMUX Mode DM1 Payload ID Detected Registers

Input Register SL12QL3 SL6DL3
PID_DET_CH2A_DS1_* DDI2_DS1 DDI2_DS1

DDI2
PID_DET_CH2B_DS1_* DDI2_DS3 DDI2_DS2
PID_DET_CH2B_DS2_* DDI2_DS7 DDI2_DS4
PID_DET_CH3A_DS1_* DDI2_DS2 NA
PID_DET_CH3A_DS2_* DDI2_DS6 NA
DDI3
PID_DET_CH3B_DS1_* DDI2_DS4 NA

Table 3-24: MUX Mode M0 Payload ID Detected Registers
Input Register QL3SL12 QLHDSL6 QL6DL12 DL6SL12 QL3DL6 DL3SL6 DLHDSL3
PID_DET_CH0A_DS1_* DDI0_DS1 DDI0_DS1 DDI0_DS1 DDI0_DS1 DDI0_DS1 DDI0_DS1 DDI0_DS1
PID_DET_CH0A_DS2_* DDI0_DS2 NA DDI0_DS3 DDI0_DS3 DDI0_DS1 DDI0_DS1 NA

DDI0
PID_DET_CH0B_DS1_* NA NA DDI0_DS2 DDI0_DS2 NA NA NA
PID_DET_CH1A_DS1_* DDI1_DS1 DDI1_DS1 DDI1_DS1 DDI1_DS1 DDI1_DS1 DDI1_DS1 DDI1_DS1
PID_DET_CH1A_DS2_* DDI1_DS2 NA DDI1_DS3 DDI1_DS3 DDI1_DS2 DDI1_DS2 NA

DDI1
PID_DET_CH2A_DS1_* DDI2_DS1 DDI2_DS1 DDI2_DS1 NA DDI2_DS1 NA NA
PID_DET_CH2A_DS2_* DDI2_DS2 NA DDI2_DS3 NA DDI2_DS2 NA NA

DDI2
PID_DET_CH3A_DS1_* DDI3_DS1 DDI3_DS1 DDI3_DS1 NA DDI3_DS1 NA NA
PID_DET_CH3A_DS2_* DDI3_DS2 NA DDI3_DS3 NA DDI3_DS2 NA NA

DDI3
Table 3-25: MUX Mode M1 Payload ID Detected Registers

Input Register DL6SL12 DL3SL6

DDI2

DDI3

3.13.2 Automatic Insertion of Payload ID
Automatic insertion of SMPTE ST 352 Payload ID by the GS12070 involves the
replacement of PID Byte 1 and modification of the Link number bits in PID Byte 4.
The structure of the inserted Payload ID is shown in Table 3-26 for DeMUX mode and
Table 3-27 for MUX mode.
If the detected Payload ID (Byte 1) is valid for the selected conversion mode, the
GS12070 will replace the outgoing Payload ID with the appropriate value.
If the detected Payload ID does not match the expected value for the selected
conversion mode or if it is missing, the GS12070 will insert a default Payload ID value.
The Payload ID will be inserted in every data stream of the Virtual Interface. If the data
stream carries a full 4:2:2 sub image with multiplexed Luma (Y) and Chroma (C) data, the
payload ID will be inserted in the Y channel only. The Payload ID will be inserted once
per frame in the Line 10, immediately following an EAV word sequence as defined in
ST352, ST2082-10(11 and12), ST2081-10 (and 11) and ST425-5.
If there are any other data already in the ancillary space in the Line 10 immediately after
the last EAV word (CRC1), they will be overwritten by the Payload ID words. In such a
case, the user can select one of manual PID insertion modes, e.g. Manual-Fast Mode with
DS Selection or Full Manual Mode, see Section 3.13.3.

Table 3-26: DeMUX Mode PID Auto Replacement Definition
PID inserted
PID Byte 1
Mode Input Output
detected
BYTE1 BYTE2 BYTE3 BYTE4
2160 2160 LINK#&0&

CEh 97h BYTE2_DET BYTE3_DET
Mode 1 Level A BYTE4_DET[4:0]
SL12QL3
All others 97h C0h 80h LINK#&000001
2160 1080 0 & BYTE3_DET[6:7] & 010&BYTE4_

C0h 85h BYTE2_DET
Mode 1 30/29.94 BYTE3_DET[3:0] DET[4:0]
SL6QL1.5
All others 85h C0h 80h 41h
4320 4320 0&LINK#&

D0h C4h BYTE2_DET BYTE3_DET
Mode 1 Mode 1 BYTE4_DET[4:0]
2160 2160 0&LINK#&

DL12QL6 D1h C5h BYTE2_DET BYTE3_DET
C4h(data interleaved)
All others C0h 80h 0&LINK#&00001
or C5h
2160 2160 0&LINK#&

CEh C2h BYTE2_DET BYTE3_DET
SL12DL6 1080 1080 0&LINK#&

CFh C3h BYTE2_DET BYTE3_DET
All others C2h C0h 80h 0&LINK#&00001
2160 2160 LINK#&0&

C2h 97h BYTE2_DET BYTE3_DET
Mode 1 Level A BYTE4_DET[4:0]
DL6QL3
All others 97h C0h 80h LINK#&000001
2160 2160 BYTE3_DET[5:7] & LINK#&0&

C0h 96h BYTE2_DET
Mode 1 on DL 3G BYTE3_DET[4:0] BYTE4_DET[4:0]
1080 1080 BYTE3_DET[7:6] & 00 & LINK#&0&

SL6DL3 C1h 94h BYTE2_DET
Mode 2 Level A BYTE3_DET[3:0] BYTE4_DET[4:0]
96h(data interleaved)
All others C0h 80h LINK#&000001
or 94h
SL3Dl1.5 No PID insertion. User should manually insert PIDs if needed

Table 3-27: MUX Mode PID Auto Replacement Definition
PID inserted
PID Byte 1
Mode Input Output
detected
BYTE1 BYTE2 BYTE3 BYTE4
2160 2160 000 &

97h CEh BYTE2_DET BYTE3_DET
Level A Mode 1 BYTE4_DET[4:0]
QL3SL12
All others CEh C0h B0h 01h
1080 2160 BYTE3_DET[5:6] & 11 & 000 &

85h C0h IN_BYTE2
30/29.94 Mode 1 BYTE3_DET[3:0] BYTE4_DET[4:0]
QL1.5SL6
All others C0h C0h B0h 01h
4320 4320 0&LINK# &

C4h D0h BYTE2_DET BYTE3_DET
2160 2160 0&LINK# &

QL6DL12 C5h D1h BYTE2_DET BYTE3_DET
D0h (data
All others C0h 80h 0&LINK# & 00001
interleaved) or D1h
2160 2160 000 &

C2h CEh BYTE2_DET BYTE3_DET
DL6SL12 1080 1080 000 &

C3h CFh BYTE2_DET BYTE3_DET
All others CEh C0h B0h 01h
2160 2160 0&LINK# &

97h C2h BYTE2_DET BYTE3_DET
QL3DL6
All others C2h C0h B0h 0&LINK# & 00001
2160 2160 BYTE3_DET[5:7] & 000 &

96h C0h BYTE2_DET
on DL 3G Mode 1 BYTE3_DET[4:0] BYTE4_DET[4:0]
1080 1080 000 &

DL3SL6 94h C1h BYTE2_DET BYTE3_DET
C0h (data interleaved)

All others C0h B0h 01h
or C1h
DL1.5SL3 No PID insertion. User should manually insert PIDs if needed

3.13.3 Manual Insertion of Payload ID
Payload ID values can be inserted manually through the PID_INS <n> registers.
In addition, specific bytes of Payload ID can be masked so they are not overwritten. The
bytes to be masked are defined within the PID_BYTE_OVERRIDE parameter in the
PID_PROGRAM_CTRL register.
For convenience, there are three methods in which this can be accomplished.
Table 3-28 shows the register settings for these three modes of operation.
Table 3-28: PID Insertion Mode
PID_PROGRAM_CTRL Register
PID_WR_FAST_ PID_OVERRIDE
MODE bit bit
Automatic PID Insertion 0 0
Manual-Fast Mode 1 0
Manual-Fast Mode with DS Selection 1 1
Full Manual Mode 0 1
In Fast Mode, one Payload ID is defined and inserted in all of the outgoing data streams.
The PID values to be inserted must be written to the PID_INS_CH0A_DS1_BYTE_1_2
and PID_INS_CH0A_DS1_BYTE_3_4.
In Fast Mode with Data Stream Selection, one Payload ID is defined and inserted in all of
the outgoing data streams. The data stream in which the PID is to be inserted is defined
by the PID_PROGRAM_STREAM_MASK register.
In Full Manual Mode Payload ID for each stream must be set, according to stream
mapping defined in Table 3-29 to Table 3-32.
The data stream in which the PID is to be inserted is defined by the
PID_PROGRAM_STREAM_MASK registers.
Table 3-29 to Table 3-32 define the PID insertion registers for all streams and operating
modes.
• Table 3-29: DeMUX Mode DM0 Payload ID Insertion Registers
• Table 3-30: DeMUX Mode DM1 Payload ID Insertion Registers
• Table 3-31: MUX Mode M0 Payload ID Insertion Registers
• Table 3-32: MUX Mode M1 Payload ID Insertion Registers

Table 3-29: DeMUX Mode DM0 Payload ID Insertion Registers
Register SLQL3 SL6QL1.5 DL12QL6 SL12DL6 DL6QL3 SL6DL3 SL3DL1.5
PID_INS_CH0A_DS1_* DDO0_DS1 DDO0_DS1 DDO0_DS1 DDO0_DS1 DDO0_DS1 DDO0_DS1 DDO0_DS1
PID_INS_CH0B_DS1_* DDO1_DS1 DDO1_DS1 DDO0_DS3 DDO0_DS3 DDO0_DS2 DDO0_DS2 DDO0_DS2
PID_INS_CH0B_DS2_* DDO3_DS1 DDO3_DS1 DDO1_DS3 DDO1_DS3 DDO1_DS2 DDO1_DS2 DDO1_DS2
PID_INS_CH1A_DS1_* DDO0_DS2 NA DDO0_DS2 DDO0_DS2 NA NA NA
PID_INS_CH1A_DS2_* DDO2_DS2 NA DDO1_DS2 DDO1_DS2 NA NA NA
PID_INS_CH1B_DS1_* DDO1_DS2 NA DDO0_DS4 DDO0_DS4 NA NA NA
PID_INS_CH1B_DS2_* DDO3_DS2 NA DDO1_DS4 DDO1_DS4 NA NA NA
PID_INS_CH2A_DS1_* NA NA DDO2_DS1 NA DDO2_DS1 NA NA
PID_INS_CH2A_DS2_* NA NA DDO3_DS1 NA DDO3_DS1 NA NA
PID_INS_CH2B_DS1_* NA NA DDO2_DS3 NA DDO2_DS2 NA NA
PID_INS_CH2B_DS2_* NA NA DDO3_DS3 NA DDO3_DS2 NA NA
PID_INS_CH3A_DS1_* NA NA DDO2_DS2 NA NA NA NA
PID_INS_CH3A_DS2_* NA NA DDO3_DS2 NA NA NA NA
PID_INS_CH3B_DS1_* NA NA DDO2_DS4 NA NA NA NA
Table 3-30: DeMUX Mode DM1 Payload ID Insertion Registers

Register SL12DL6 SL6DL3
PID_INS_CH2A_DS1_* DDO2_DS1 DDO2_DS1
PID_INS_CH2B_DS1_* DDO2_DS3 DDO2_DS2
PID_INS_CH2B_DS2_* DDO3_DS3 DDO3_DS2
PID_INS_CH3A_DS1_* DDO2_DS2 NA
PID_INS_CH3A_DS2_* DDO3_DS2 NA
PID_INS_CH3B_DS1_* DDO2_DS4 NA

Table 3-31: MUX Mode M0 Payload ID Insertion Registers
Register QL3SL12 QL1.5SL6 QL6DL12 DL6SL12 QL3DL6 DL3SL6 DL1.5SL3
PID_INS_CH0A_DS2_* DDO0_DS2 NA DDO0_DS3 DDO0_DS3 DDO0_DS2 DDO0_DS2 NA
PID_INS_CH0B_DS1_* NA NA DDO0_DS2 DDO0_DS2 NA NA NA
PID_INS_CH1A_DS2_* DDO0_DS4 NA DDO0_DS7 DDO0_DS7 DDO0_DS4 DDO0_DS4 NA
PID_INS_CH2A_DS1_* DDO0_DS5 DDO0_DS3 DDO2_DS1 NA DDO2_DS1 NA NA
PID_INS_CH2A_DS2_* DDO0_DS6 NA DDO2_DS3 NA DDO2_DS2 NA NA
PID_INS_CH3A_DS1_* DDO0_DS7 DDO0_DS4 DDO2_DS5 NA DDO2_DS3 NA NA
PID_INS_CH3A_DS2_* DDO0_DS8 NA DDO2_DS7 NA DDO2_DS4 NA NA
Table 3-32: MUX Mode M1 Payload ID Insertion Registers

Register DL6SL12 DL3SL6

3.14 Embedded Video Pattern Generator
GS12070 contains a video pattern generator (PG) capable of generating various 4K
video patterns on DL6G and 12GUHD interfaces for video system debug, design bring
up, and optimization. The PG does not utilize any shaping (rise and fall times) for
individual bars or for custom patterns.
PG can be enabled via OPERATING_MODE_SEL_REG register, address 0001h, by
setting bits 13 to 12 to "01" (parameters PG_REF_INT_EXTB and SEL_PG). The device
must then be set to MUX operating mode, and the gearbox mode should be set to
desired output standard (ie. QL3GSL12G, QL3GDL6G or QL1.5SL6G).
Timing signals used to generate patterns are extracted from a video stream via DDI0. A
valid SDI signal must be connected to the DDI0 input and its data rate must match the
input data rate of the selected gearbox mode (ie. 3G input for QL3GSL12G mode).
The default pattern after reset or power up is Colour Bars 75%, but there are additional
patterns that can be selected through register 3000h: Colour Bars 100%, several flat field
patterns, Luma/Chroma ramp, and custom pattern mode. Predefined patterns are listed
in Table 3-33: Predefined Pattern Selection.
For more information on Pattern Generator, please refer to the “Generating Video
Patterns with GS12070 UHD-SDI Gearbox Application Note” (PDS-061505).
Table 3-33: Predefined Pattern Selection
PG_PATTERN_SEL Pattern Visual Representation
0000 Colour bars 70%
0001 Colour bars 100%
0010 Checkfield
0011 Luma/Chroma (Y/C) ramp

Table 3-33: Predefined Pattern Selection (Continued)
0100 EQ test signal
0101 PLL test signal
0110 Custom
0111 Reserved
1000 White
1001 Yellow
1010 Cyan
1011 Green
1100 Magenta
1101 Red

Table 3-33: Predefined Pattern Selection (Continued)
1110 Blue
1111 Black
3.15 GSPI Host Interface

The GS12070 is configured via the Gennum Serial Peripheral Interface (GSPI).
The GSPI host interface is comprised of a serial data input signal (SDIN pin), serial data
output signal (SDOUT pin), an active-LOW chip select (CS pin) and a burst clock (SCLK
pin).
The GS12070 is a slave device, so the SCLK, SDIN and CS signals must be sourced by the
application host processor.
All read and write access to the device is initiated and terminated by the application
host processor.
3.15.1 CS Pin
The Chip Select pin (CS) is an active-LOW signal provided by the host processor to the
GS12070.
The HIGH-to-LOW transition of this pin marks the start of serial communication to the
GS12070.
The LOW-to-HIGH transition of this pin marks the end of serial communication to the
GS12070.
Each device may use its own separate Chip Select signal from the host processor or up
to 32 devices may be connected to a single Chip Select when making use of the Unit
Address feature.
Only those devices whose Unit Address matches the UNIT ADDRESS in GSPI Command
Word 1 will respond to communication from the host processor (unless the B’CAST ALL
bit in GSPI Command Word 1 is set to 1).

3.15.2 SDIN Pin
The SDIN pin is the GSPI serial data input pin of the GS12070.
The 32-bit Command and 16-bit Data Words from the host processor or from the SDOUT
pin of other devices are shifted into the device on the rising edge of SCLK when the CS
pin is LOW.
3.15.3 SDOUT Pin

The SDOUT pin is the GSPI serial data output of the GS12070.
All data transfers out of the GS12070 to the host processor or to the SDIN pin of other
connected devices occur from this pin.
By default at power up or after system reset, the SDOUT pin provides a non-clocked path
directly from the SDIN pin, regardless of the CS pin state, except during the GSPI Data
Word portion for read operations from the device. This allows multiple devices to be
connected in Loop-Through configuration.
For read operations, the SDOUT pin is used to output data read from an internal
Configuration and Status Register (CSR) when CS is LOW. Data is shifted out of the
device on the falling edge of SCLK, so that it can be read by the host processor or other
downstream connected device on the subsequent SCLK rising edge.
3.15.3.1 GSPI Link Disable Operation

It is possible to disable the direct SDIN to SDOUT (Loop-Through) connection by writing
a value of 1 to the GSPI_LINK_DISABLE bit in HOST_CONFIG. When disabled, any data
appearing at the SDIN pin will not appear at the SDOUT pin and the SDOUT pin is HIGH.
Note: Disabling the Loop-Through operation is temporarily required when initializing
the Unit Address for up to 32 connected devices.
The time required to enable/disable the Loop-Through operation from assertion of the
register bit is less than the GSPI configuration command delay as defined by the
parameter tcmd_GSPI_config (4 SCLK cycles).
Table 3-34: GSPI_LINK_DISABLE Bit Operation
Bit State Description
0 SDIN pin is looped through to the SDOUT pin
1 Data appearing at SDIN does not appear at SDOUT, and SDOUT pin is HIGH.

SDIN pin
Configuration and
Status Register SDOUT pin
GSPI_LINK
_DISABLE
High-Z
BUS_THROUGH
CS pin
Figure 3-14: GSPI_LINK_DISABLE Operation
3.15.3.2 GSPI Bus-Through Operation

Using GSPI Bus-Through operation, the GS12070 can share a common PCB trace with
other GSPI devices for SDOUT output.
When configured for Bus-Through operation, by setting
GSPI_BUS_THROUGH_ENABLE bit to 1, the SDOUT pin will be high-impedance when
the CS pin is HIGH.
When the CS pin is LOW, the SDOUT pin will be driven and will follow regular read and
write operation as described in Section 3.15.3.
Multiple chains of GS12070 devices can share a single SDOUT bus connection to host by
configuring the devices for Bus-Through operation. In such configuration, each chain
requires a separate Chip Select (CS).
SDIN pin
Configuration and
Status Register SDOUT pin
GSPI_LINK
_DISABLE
High-Z
BUS_THROUGH
CS pin
Figure 3-15: GSPI_BUS_THROUGH_ENABLE Operation
3.15.4 SCLK Pin

The SCLK pin is the GSPI serial data shift clock input to the device, and must be provided
by the host processor.
Serial data is clocked into the GS12070 SDIN pin on the rising edge of SCLK. Serial data
is clocked out of the device from the SDOUT pin on the falling edge of SCLK (read
operation). SCLK is ignored when CS is HIGH.
The maximum interface clock rate is 27MHz.

3.15.5 Command Word 1 Description
All GSPI accesses are a minimum of 48 bits in length (two 16-bit Command Words
followed by a 16-bit Data Word) and the start of each access is indicated by the
HIGH-to-LOW transition of the chip select (CS) pin of the GS12070.
The format of the Command Words and Data Word are shown in Figure 3-16.
Data received immediately following this HIGH-to-LOW transition will be interpreted as
a new Command Word.
3.15.5.1 R/W bit—B15 Command Word 1

This bit indicates a read or write operation.
When R/W is set to 1, a read operation is indicated, and data is read from the register
specified by the ADDRESS field of the Command Word.
When R/W is set to 0, a write operation is indicated, and data is written to the register
specified by the ADDRESS field of the Command Word.
3.15.5.2 B'CAST ALL—B14 Command Word 1

This bit is used in write operations to configure all devices connected in Loop-Through
and Bus-Through configuration with a single command.
When B’CAST ALL is set to 1, the following Data Word is written to the register specified
by the ADDRESS field of the Command Words, regardless of the setting of the UNIT
ADDRESS(es).
When B’CAST ALL is set to 0, a normal write operation is indicated. Only those devices
that have a Unit Address matching the UNIT ADDRESS field of Command Word 1 write
the Data Word to the register specified by the ADDRESS field of the Command Words.
3.15.5.3 EMEM—B13 Command Word 1

The EMEM bit must be set to 1 in Command Word 1. When EMEM is set to 1, a 23-bit
address split between Command Word 1 and Command Word 2 is used to access the
registers in this device.
3.15.5.4 AUTOINC—B12 Command Word 1

Auto Increment is not supported. The AUTOINC must be set to 0.

3.15.5.5 UNIT ADDRESS—B11:B7 Command Word 1
The 5 bits of the UNIT ADDRESS field of the Command Word are used to select one of 32
devices connected on a single chip select in Loop-Through or Bus-Through
configurations.
Read and write accesses are only accepted if the UNIT ADDRESS field matches the
programmed DEVICE_UNIT_ADDRESS in HOST_CONFIG.
By default at power-up or after a device reset, the DEVICE_UNIT_ADDRESS is set to 00h.
3.15.5.6 ADDRESS—B6:B0 Command Word 1 and B15:B0 Command Word 2

The Command and Data Word formats are shown in Figure 3-16 and Figure 3-17 below.
Command Word
MSB LSB
UNIT ADDRESS ADDRESS[22:16]
B’CAST
R/W ALL EMEM AUTOINC UA4 UA3 UA2 UA1 UA0 A22 A21 A20 A19 A18 A17 A16
ADDRESS[15:0]
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Data Word
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 3-16: Command and Data Word Format
Command Word 1
MSB LSB
UNIT ADDRESS ADDRESS[22:16]
B’CAST
R/W ALL EMEM AUTOINC UA4 UA3 UA2 UA1 UA0 A22 A21 A20 A19 A18 A17 A16
23-bit CSR address field.
5-bit UNIT ADDRESS field providing up to

32 devices to be connected on a single CS.
Auto increment read/write access when set.

Single read write access when reset.
Extended memory mode. When set, the extended memory mode is

enabled. When reset, normal GSPI addressing is enabled.
When set, the UNIT ADDRESS field is ignored and

all data accesses are actioned by the device.
When reset, the Unit Address is used to
manage data accesses in the device.
Read access when this bit is set.

Write access when this bit is reset.
Command Word 2
ADDRESS[15:0]
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Figure 3-17: Command Word 1 and Command Word 2 Details

3.15.6 GSPI Transaction Timing
t
tcmd
t9
SCLK
CS
SDIN X
SDOUT X
t0 t1 t2 t4 t7
SCLK
t3 t8
CSb
SDIN R/W BCST EMEM Auto_Inc UA4 UA3 UA2 UA1 UA0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT R/W BCST EMEM Auto_Inc UA4 UA3 UA2 UA1 UA0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D 12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDI signal is looped out on SDO
Write Mode
t5
t9
SCLK
t6
CSb
SDIN R/W RSV EMEM Auto_Inc UA4 UA3 UA2 UA1 UA0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDOUT R/W RSV EMEM Auto_Inc UA4 UA3 UA2 UA1 UA0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDI signal is looped out on SDO Read Data is output on SDO
Read Mode
Figure 3-18: GSPI External Interface Timing

Table 3-35: GSPI Timing Parameters
Equivalent
Parameter Symbol SCLK Min Typ Max Units
Cycles
CS LOW Before SCLK Rising Edge t0 — 1.8 — — ns
SCLK Frequency — — — 20 MHz
SCLK Period t1 — 50 — — ns
SCLK Duty Cycle t2 — 40 50 60 %
Input Data Setup Time t3 — 2 — — ns
SCLK Idle Time – Write t4 1 50 — — ns
SCLK Idle Time – Read t5 4 162 — — ns
Inter–Command Delay Time tcmd 3 120 — — ns
Inter–Command Delay Time (after

tcmd_GSPI_conf2 4 162 — — ns
GSPI configuration write)
SDOUT After SCLK Falling Edge t6 — 2 — 8 ns
CS HIGH After Final SCLK Falling

t7 — 0 — — ns
Edge
Input Data Hold Time t8 — 1 — — ns
CS HIGH Time t9 — 75 — — ns
SDIN to SDOUT Combinatorial

— — — — 7.5 ns
Delay
# of
Max chips daisy-chained at max compatible
— — 1
SCLK frequency (20 MHz) When host clocks in SDOUT Semtech
data on rising edge of SCLK devices
Max frequency for 16 

— — 2 MHz
daisy-chained devices
# of
Max chips daisy-chained at max compatible
— — 4
SCLK frequency (20 MHz) When host clocks in SDOUT Semtech
data on falling edge of SCLK devices
Max frequency for 16 

— — 2 MHz
daisy-chained devices
Note:
1. Parameter is exactly multiple of SCLK periods and scales proportionally.
2. tcmd_GSPI_conf inter-command delay must be used whenever modifying HOST_CONFIG register at address 0x00.

3.15.7 Single Read/Write Access
Single read/write access timing for the GSPI interface is shown in Figure 3-19 to
Figure 3-23.
When performing a single read or write access, one Data Word is read from/written to
the device per access. Each access is a minimum of 48-bits long, consisting of two
Command Words and a single Data Word. The read or write cycle begins with a
HIGH-to-LOW transition of the CS pin. The read or write access is terminated by a
LOW-to-HIGH transition of the CS pin.
The maximum interface clock rate is 20MHz and the inter-command delay time
indicated in the figures as tcmd, is a minimum of 3 SCLK clock cycles. After modifying
values in HOST_CONFIG, the inter-command delay time, tcmd_GSPI_config, is a minimum
of 4 SCLK clock cycles.
For read access, the time from the last bit of Command Word 2 to the start of the data
output, as defined by t5, corresponds to no less than 4 SCLK clock cycles at 20MHz.
t cmd
SCLK
CS
SDIN COMMAND WORD 1 COMMAND WORD 2 DATA WORD X COMMAND WORD 1
SDOUT COMMAND WORD 1 COMMAND WORD 2 DATA WORD X COMMAND WORD 1
Figure 3-19: GSPI Write Timing—Single Write Access with Loop-Through Operation (default)
t cmd
SCLK
CS
SDOUT
Figure 3-20: GSPI Write Timing—Single Write Access with GSPI Link-Disable Operation
t cmd
SCLK
CS

High-Z High-z
SDOUT COMMAND WORD 1 COMMAND WORD 2 DATA WORD COMMAND WORD 1
Figure 3-21: GSPI Write Timing—Single Write Access with Bus-Through Operation
SCLK
t5
CS
SDIN COMMAND WORD 1 COMMAND WORD 2
SDOUT COMMAND WORD 1 COMMAND WORD 2 DATA WORD
Figure 3-22: GSPI Read Timing—Single Read Access with Loop-Through Operation (default)

SCLK
t5
CS
SDIN COMMAND WORD 1 COMMAND WORD 2

High-z
SDOUT COMMAND WORD 1 COMMAND WORD 2 X DATA WORD
Figure 3-23: GSPI Read Timing—Single Read Access with Bus-Through Operation
3.15.8 Auto-increment Read/Write Access

This feature is not supported in the GS12070.
3.15.9 Setting a Device Unit Address

Multiple (up to 32) GS12070 devices can be connected to a common Chip Select (CS) in
Loop-Through or Bus-Through operation.
To ensure that each device selected by a common CS can be separately addressed, a
unique Unit Address must be programmed by the host processor at start-up as part of
system initialization or following a device reset.
Note: By default at power up or after a device reset, the DEVICE_UNIT_ADDRESS of
each device is set to 0h and the SDINSDOUT non-clocked loop-through for each
device is enabled.
These are the steps required to set the DEVICE_UNIT_ADDRESS of devices in a chain to
values other than 0:
1. Write to Unit Address 0 selecting HOST_CONFIG (ADDRESS = 0), with the
GSPI_LINK_DISABLE bit set to 1 and the DEVICE_UNIT_ADDRESS field set to 0.
This disables the direct SDINSDOUT non-clocked path for all devices on chip
select.
2. Write to Unit Address 0 selecting HOST_CONFIG (ADDRESS = 0), with the
GSPI_LINK_DISABLE bit set to 0 and the DEVICE_UNIT_ADDRESS field set to a
unique Unit Address. This configures DEVICE_UNIT_ADDRESS for the first device
in the chain. Each subsequent such write to Unit Address 0 will configure the next
device in the chain. If there are 32 devices in a chain, the last (32nd) device in the
chain must use DEVICE_UNIT_ADDRESS value 0.
3. Repeat step 2 using new, unique values for the DEVICE_UNIT_ADDRESS field in
HOST_CONFIG until all devices in the chain have been configured with their own
unique Unit Address value.
Note: tcmd_GSPI_conf delay must be observed after every write that modifies
HOST_CONFIG.
All connected devices receive this command (by default the Unit Address of all devices
is 0), and the Loop-Through operation will be re-established for all connected devices.
Once configured, each device will only respond to Command Words with a 
UNIT ADDRESS field matching the DEVICE_UNIT_ADDRESS in HOST_CONFIG.

Note: Although the Loop-Through and Bus-Through configurations are compatible
with previous generation GSPI enabled devices (backward compatibility), only devices
supporting Unit Addressing can share a chip select. All devices on any single chip select
must be connected in a contiguous chain with only the last device's SDOUT connected
to the application host processor. Multiple chains configured in Bus-Through mode can
have their final SDOUT outputs connected to a single application host processor input.
3.15.10 Default GSPI Operation

By default at power up or after a device reset, the GS12070 is set for Loop-Through
Operation and the internal DEVICE_UNIT_ADDRESS field of the device is set to 0.
Figure 3-24 shows a functional block diagram of the Configuration and Status Register
(CSR) map in the GS12070.
At power-up or after a device reset, DEV_UNIT_ADDRESS = 00h
bits [15] [14] [13] [12] [11:7] [6:0]
BCAST Auto Unit Address Register Address

R/W EMEM
COMMAND 1 ALL Inc 32 devices Upper 7 bits
bits [15:0]
COMMAND 2 Lower 16 bits of Register Address
bits [15:0]
DATA Data to be written / Read Data Compare
bits [15] [14] [13] [12:5] [4:0]

Read/Write
GSPI_BUS_
Reg 0 GSPI_LINK
RESERVED THROUGH RESERVED DEV_UNIT_ADDRESS
_DISABLE
_ENABLE
Configuration and Status Registers
Figure 3-24: Internal Register Map Functional Block Diagram
The steps required for the application host processor to write to the Configuration and
Status Registers via the GSPI, are as follows:
1. Set Command Word 1 for write access (R/W = 0); set Auto Increment to 0; set EMEM
to 1. The Unit Address field in the Command Word 1 to match the configured
DEVICE_UNIT_ADDRESS which will be zero after power-up. Set the Register
Address bits in Command Word 1 to match the upper 7 bits of the register address
to be accessed. Set the bits in Command Word 2 to match the lower 16 bits of the
register address to be accessed. Write Command Word 1 and Command Word 2.
2. Write the Data Word to be written to the register.
Read access is the same as the above with the exception of step 1, where the Command
Word 1 is set for read access (R/W = 1).
Note: The UNIT ADDRESS field of Command Word 1 must always match
DEVICE_UNIT_ADDRESS for an access to be accepted by the device. Changing
DEVICE_UNIT_ADDRESS to a value other than 0 is only required if multiple devices are
connected to a single chip select (in Loop-Through or Bus-Through configuration).

4. Host Interface Register Map
4.1 Control Registers

The GS12070 only supports extended mode addressing (EMEM). The register addresses
in the register descriptions include the EM register offset address. Table 4-1 is only
provided as reference.
Table 4-1: Address Offset

Table Address Offset Valueh
GS12070 Control and Status Register

0
Table 4-5
Rx Control and Status Register
1000
Table 4-6
Tx Control and Status Register
2000
Table 4-7
Pattern Generator and Control Register
3000
Table 4-8
Table 4-2: Control Registers

GSPI
Function
Addressh
Register Name
GSPI 0 HOST_CONFIG
1 OPERATING_ MODE_SEL_REG
2 SD_BYPASS_ SEL_REG
13 SYNC_W _DISABLE
19 VID_STREAM_ INTERLEAVE
1C DISABLE_ CRC_INS
6A TX_ EXTERNAL_REF_ CLK_SEL

Operating Mode Control
6D TIM_ OUTPUT_ ENABLE
STAT_CH0,
6E, 6F, STAT_CH1,
70, 71 STAT_CH2,
STAT_CH3
72 STAT_ OUTPUT_ ENABLE
78, 79 RESET_0, RESET_1

Table 4-2: Control Registers (Continued)
GSPI
Function
Addressh Register Name
3 INPUT_ LOCK_REG
5 ISP_REG
Input Control
6 MANUAL_RATE
9 DDI_PWR_ DOWN
7 DATA_RATE _REPORT
1B CRC_ERROR
PID_DET_CH0A_ DS1_BYTE_1_2 to
Status 1D to 3C
PID_DET_CH3B _DS2_BYTE_3_4
42 PID_ERROR
43 PID_DETECTED
A DDO_IDLE
3D OVERRIDE_ STREAM_ NUMBER

Output Control
LINK_N_TO _INSERT_STR _0_7,
3E, 3F
LINK_N_TO _INSERT_STR _8_15
69 TX_REF_CLK_SEL
B REG_CTRL_ OUTPUT_ ASGMT_EN

Output Channel Assignment
C CHAN_ASGMT _DDO<n>
E, F SEL_DM0_VIRT, SEL_DM1_VIRT
11 DEMUX_IN_SEL
73 DM0_DELAY_EN
Demultiplex Configuration
DM0_ DELAY_LINK1,
74, 75, DM0_ DELAY_LINK2,
76, 77 DM0_ DELAY_LINK3,
DM0_ DELAY_LINK4
40 PID_ PROGRAM_CTRL
41 PID_PROGRAM _STREAM_MASK
PID Insertion
PID_INS_CH0A _DS1_BYTE_1_2 to
44 to 63
PID_INS_CH3B _DS2_BYTE_3_4

Table 4-2: Control Registers (Continued)
GSPI
Function
Addressh Register Name
64 VI_ASGMT_0
Multiplex Configuration
66 LOST_INPUT_ IGNORE_CTRL
4, 8, D, 10,
12, 14, 15,
16, 17, 18,
Reserved 1A, 65, 67, RSVD
68, 6A, 6B,
6C, 7A to
8B
Table 4-3: Rx Control Registers

Function GSPI Addressh Register Name
101B DDI_CDR_LBW
1023, DDI0_EQ_UPDT,
Rx Control 1024, DDI1_EQ_UPDT,
1025, DDI2_EQ_UPDT,
1026 DDI3_EQ_UPDT
1010 to 101A,
RSVD 101C to 1022, RSVD
1027 to 10F9
Table 4-4: Tx Control Registers

Function GSPI Addressh Register Name
2014 DDO_DRV_AMP
201A DDO_LBW
201B DDO_LBW_UPDT
Tx Control
201C DDO_DRV_UPDT
2037 OUTPUT_ PWR_DOWN
2038 DDO_DRIVER_ DISABLE
2000 to 2013,
2015 to 2019,
Reserved 201D to 2036, RSVD
2039 to 20C7

4.2 Register Descriptions
4.2.1 GS12070 Control and Status Register

F
Table 4-5: GS12070 Control and Status Register 

Note: Where unspecified, parameter bits MSB to LSB are mapped to DDIO/Channel/Stream [MSB:LSB]
Bit Reset
Addressh Register Name Parameter Name R/W Description
Slice Valueh
RSVD 15:15 RO 0 Reserved.
GSPI_LINK_DISABLE 14:14 RW 0 GSPI loop-through disable.
GSPI_BUS_
13:13 RW 0 Enables bus-through operation.
0 HOST_CONFIG THROUGH_ENABLE
DEVICE_UNIT_
4:0 RW 0 Sets the unit address for the device.
ADDRESS

Table 4-5: GS12070 Control and Status Register (Continued)
Bit Reset
Slice Valueh
1 = Reserved.
PG_REF_INT_EXTB 13:13 RW 0 0 = Selects timing from the video stream on
the input DDIO.
1 = PG enabled.
SEL_PG 12:12 RW 0
0 = PG disabled.
REG_CTRL_ When HIGH, the SEC_LINK_REG value is

10:10 RW 0
SEC_LINK_EN used.
When HIGH, the second link of the dual link

connection is multiplexed or
SEC_LINK_REG 9:9 RW 0 demultiplexed.
Only active when REG_CTRL_SEC_LINK_EN
is set HIGH.
REG_CTRL_ Overrides MODE_SEL pins with values in

8:8 RW 0
MODE_SEL_EN the MODE_SEL register.
Selects operating mode, if

REG_CTRL_MODE_SEL is set HIGH.
OPERATING_
1 111 = QL 3Gb/s to SL 12Gb/s
MODE_SEL_REG
110 = QL 1.5Gb/s to SL 6Gb/s
MODE_SEL 7:5 RW 7 101 = QL 6Gb/s to DL 12Gb/s
100 = QL 3Gb/s to DL 6Gb/s
011 = DL 6Gb/s to SL 12Gb/s
010 = DL 3Gb/s to SL 6Gb/s
001 = DL 1.5Gb/s to SL 3Gb/s
000 = RSVD
When HIGH, MUX_DEMUX_REG,

REG_CTRL_ PID_MODE_REG and BYPASS_REG will set
4:4 RW 0
OP_MODE_EN operating mode instead of the associated
pins.
Enabled by REG_CTRL_OP_MODE_EN.
PID_MODE_REG 3:2 RW 0 00 = Automatic PID insertion
11 = No PID insertion
When HIGH, sets the part in the BYPASS.

BYPASS_REG 1:1 RW 0
When HIGH, sets MUX operation mode.

MUX_DEMUX_REG 0:0 RW 0 When LOW, sets DeMUX operation mode.

Bit Reset
Slice Valueh
When HIGH, oversampling rate in

SD_BYPASS_ SD_BYPASS mode is set to 6G data rate.
9:9 RW 0
RATE_6G_3Gb
When LOW, it is set to 3G data rate.
REG_CTRL_ When HIGH, SD_BYPASS control from

8:8 RW 0
SD_BYPASS_ SD_BYPASS registers.
2 SEL_REG
SD_BYPASS_PIN 7:4 RO 0 SD_BYPASS pin status.
When HIGH, input Rx will be set to

SD_BYPASS mode.
SD_BYPASS_SEL 3:0 RW 0 Only active when REG_CTRL_SD_BYPASS is
set HIGH.
One bit per input.
REG_CTRL_ When HIGH, control of lock signal is taken

11:8 RW 0
INPUT_LOCK from INPUT_LOCK_REG.
INPUT_ Overrides video lock signal if REG_CTRL_
3 LOCK_REG
INPUT_LOCK_REG 7:4 RW 0 INPUT_LOCK register is set HIGH.
One bit per input.
Indicates video lock of the input 0 to 3.

INPUT_LOCK 3:0 RO 0
One bit per input.
4 RSVD RSVD 15:0 RW 0 Reserved.

Bit Reset
Slice Valueh
When HIGH, inverts ISP pin signal.

One bit per input.
ISP_POLARITY(n)
ISP_POLARITY 15:12 RW 0 ISP(n) 0
ISP_REG_SEL(n)
1
REG_CTRL_ISP_SEL_EN(n)
ISP_REG When HIGH, overrides ISP pin with the

5 REG_CTRL_
11:8 RW 0 value from the ISP_REG_SEL parameter.
ISP_SEL_EN
One bit per input.
Sets value of ISP signal, if

ISP_REG_SEL 7:4 RW 0 REG_CTRL_ISP_SEL_EN is set HIGH.
One bit per input.
Reports signal level (HIGH or LOW) applied

ISP_PIN 3:0 RO 0 to the ISP pin.
One bit per input.
Manual rate control of Rx3.

00 = HD
01 = 3G
MANUAL_RATE_RX3 11:10 RW 0 10 = 6G
11 = 12G
Only active when REG_CTRL_MANUAL
_RATE[3] is set HIGH.
Manual rate control of Rx2.

MANUAL_RATE_RX2 9:8 RW 0 See MANUAL_RATE_RX3 for selection
6 MANUAL_RATE
values.

values.

values.
REG_CTRL_ Manual rate control override.

3:0 RW 0
MANUAL_RATE One bit per input.

Bit Reset
Slice Valueh
Indicates data rate of Rx3 in BYPASS mode.

11 = 12G
10 = 6G
01 = 3G
00 = HD
DATA_RATE_RX3 7:6 RO 3 Note: If the input is not locked, the value
reported by this parameter is not valid. 
If the device is in the DeMUX or MUX mode,
DATA_RATE the value reported is always the same as
7 _REPORT
the input data rate given by the selected
gearbox mode.
Indicates data rate of Rx2.

DATA_RATE_RX2 5:4 RO 3
See DATA_RATE_RX3 for selection values.


8 RSVD RSVD 15:0 RW F Reserved.
Manual receiver power-down override

DDI_PWR_DOWN enable.
11:8 RW 0
_REG_SEL
One bit per input.
DDI3_PWR_ Power-down for DDI3, if DDI_PWR_DOWN

7:7 RW 0
DOWN_REG _REG_SEL is set HIGH.
RSVD 6:6 RW 0 Reserved.
DDI_PWR_ DDI2_PWR_ Power-down for DDI2, if DDI_PWR_DOWN

9 5:5 RW 0
DOWN DOWN_REG _REG_SEL is set HIGH.

3:3 RW 0

1:1 RW 0

Bit Reset
Slice Valueh
Manual transmitter idle override enable.

0 = DDO idle controlled by the GS12070
operation mode
DDO_IDLE_OW_EN 11:8 RW 0
1 = DDO Idle controlled by the
DDO[3:0]_IDLE_REG setting
One bit per output.
Idle for DDO3, if DDO_IDLE_OW_EN is set

DDO3_IDLE_REG 6:6 RW 0
DDO_IDLE HIGH.
A

HIGH.

HIGH.

HIGH.
When the corresponding bit <n> is

asserted, the assignment of the
DDO<n>serial output is controlled by the
REG_CTRL_
OUTPUT_ settings of the OUTPUT_ASGMT_DDO<n>
B REG_CTRL_OUTPUT_
ASGMT_EN 3:0 RW 0 parameter
ASGMT_EN
DDO0 = Bit 0
DDO1 = Bit 1
DDO2 = Bit 2
DDO3 = Bit 3

Bit Reset
Slice Valueh
Selects the source of the DDO3 output if

REG_CTRL_OUTPUT_ASGMT_EN is set
HIGH.
000 = M0 Processed Output
OUTPUT_ 001 = M1 Processed Output
ASGMT_DDO3
14:12 RW 2 010 = DM0 Processed Output 
011 = DM1 Processed Output
100 = DDI0 
101 = DDI1 
110 = DDI2 
111 = DDI3

CHAN_ASGMT OUTPUT_
C _DDO<n> 10:8 RW 2 HIGH.
ASGMT_DDO2
See OUTPUT_ASGMT_DDO3 for selection
values.

OUTPUT_ HIGH.
6:4 RW 2
ASGMT_DDO1
values.

OUTPUT_ HIGH.
2:0 RW 2
ASGMT_DDO0
values.
D RSVD RSVD 15:0 RW 0 Reserved.

Bit Reset
Slice Valueh
Manual assignment of the data stream on

the Tx3, if REG_CTRL_SEL_DM0_VIRT[3] is
set HIGH.
SEL_DM0_VIRT3 11:10 RW 0 00 = Data stream 8/7
01 = Data stream 6/5
10 = Data stream 4/3
11 = Data stream 2/1

SEL_DM0_VIRT2 9:8 RW 1 set HIGH.
See SEL_DM0_VIRT3 for selection values.
E SEL_DM0_VIRT

When HIGH, the control of the DM0 virtual

REG_CTRL_SEL interface output is from register
3:0 RW 0 SEL_DM0_VIRT[3:0].
_DM0_VIRT
One bit per output channel.
REG_CTRL_SEL When HIGH, enables SEL_DM1_VIRT

4:4 RW 0
F SEL_DM1_VIRT _DM1_VIRT control.
When HIGH, swaps data stream on DM1.

SEL_DM1_VIRT 3:0 RW 5

Bit Reset
Slice Valueh
When HIGH, enables selection of the active

REG_CTRL_DEMUX
1:1 RW 0 input in the single link to quad link case
_IN_0_2
through the register DEMUX_IN_0_2_SEL.
11 DEMUX_IN_SEL
Select the active input in the single link to
quad link case, if REG_CTRL_DEMUX_IN_0
DEMUX_IN_0_2_SEL 0:0 RW 0 _2 is set HIGH. 
0 = DDI0
1 = DDI2
12 RSVD RSVD 15:0 RO 7654 Reserved.
When HIGH, disables sync word insertion

DEMUX1_SYNC_W for DEMUX1.
3:3 RW 0
_DISABLE
Only applies to dual 6G output mode.
When HIGH, disables the sync word

SYNC_W DEMUX0_SYNC_W insertion for DEMUX0.
13 _DISABLE 2:2 RW 0
_DISABLE Only applies to dual and quad 6G output
mode.
MUX1_SYNC_W When HIGH, disables sync word insertion

1:1 RW 0
_DISABLE for MUX1.
MUX0_SYNC_W When HIGH, disables sync word insertion

0:0 RW 0
_DISABLE for MUX0.
14 RSVD RSVD 15:0 RW FF Reserved.
When HIGH, data in the video stream is

interleaved.
VID_STREAM_
19 VID_STREAM_ One bit per Input data stream. See
INTERLEAVE
7:0 RO 0 CH<n>_DS<m> in Figure 3-9 for data
INTERLEAVE_STAT
stream definition. It maps as:
bit0 - DDI0_DS1
bit7 - DDI3_DS2
1A RSVD RSVD 15:0 RW 0 Reserved.

Bit Reset
Slice Valueh
When this register reads ‘01’, a CRC error is

detected in DataStream 2 of any of the
CRC_DS2_ERROR 15:8 ROCW 0 inputs.
Write ’80’ to clear this register.
1B CRC_ERROR
When this register reads ‘01’, a CRC error is
detected in DataStream 1 of any of the
CRC_DS1_ERROR 7:0 ROCW 0 inputs.
Write ’80’ to clear this register.
When HIGH, disables insertion of

recalculated CRC words.
DISABLE_
1C One bit per Input data stream. See
CRC_INS
DISABLE_CRC_INS 7:0 RW 0 CH<n>_DS<m> in Figure 3-9 for data
stream definition. It maps as:
bit0 - DDI0_DS1
bit7 - DDI3_DS2
PID_DET_CH0A Detected PID byte2 for video stream CH0A

15:8 RO 0
PID_DET_CH0A_ _DS1_BYTE_2 DS1.
1D DS1_BYTE_1_2
7:0 RO 0
_DS1_BYTE_1 DS1.

15:8 RO 0
PID_DET_CH0A _DS1_BYTE_4 DS1.
1E _DS1_BYTE_3_4
7:0 RO 0
_DS1_BYTE_3 DS1.

15:8 RO 0
1F _DS2_BYTE_1_2
7:0 RO 0
_DS2_BYTE_1 DS2.

15:8 RO 0
20 _DS2_BYTE_3_4
7:0 RO 0
_DS2_BYTE_3 DS2.
PID_DET_CH0B Detected PID byte2 for video stream CH0B

15:8 RO 0
PID_DET_CH0B _DS1_BYTE_2 DS1.
21 _DS1_BYTE_1_2
7:0 RO 0
_DS1_BYTE_1 DS1.

Bit Reset
Slice Valueh

15:8 RO 0
22 _DS1_BYTE_3_4
7:0 RO 0
_DS1_BYTE_3 DS1.

15:8 RO 0
23 _DS2_BYTE_1_2
7:0 RO 0
_DS2_BYTE_1 DS2.

15:8 RO 0
24 _DS2_BYTE_3_4
7:0 RO 0
_DS2_BYTE_3 DS2.

15:8 RO 0
25 _DS1_BYTE_1_2
7:0 RO 0
_DS1_BYTE_1 DS1.

15:8 RO 0
26 _DS1_BYTE_3_4
7:0 RO 0
_DS1_BYTE_3 DS1.

15:8 RO 0
27 _DS2_BYTE_1_2
7:0 RO 0
_DS2_BYTE_1 DS2.

15:8 RO 0
28 _DS2_BYTE_3_4
7:0 RO 0
_DS2_BYTE_3 DS2.

15:8 RO 0
29 _DS1_BYTE_1_2
7:0 RO 0
_DS1_BYTE_1 DS1.

15:8 RO 0
2A _DS1_BYTE_3_4
7:0 RO 0
_DS1_BYTE_3 DS1.

Bit Reset
Slice Valueh

15:8 RO 0
2B _DS2_BYTE_1_2
7:0 RO 0
_DS2_BYTE_1 DS2.

15:8 RO 0
2C _DS2_BYTE_3_4
7:0 RO 0
_DS2_BYTE_3 DS2.

15:8 RO 0
2D _DS1_BYTE_1_2
7:0 RO 0
_DS1_BYTE_1 DS1.

15:8 RO 0
2E _DS1_BYTE_3_4
7:0 RO 0
_DS1_BYTE_3 DS1.

15:8 RO 0
2F _DS2_BYTE_1_2
7:0 RO 0
_DS2_BYTE_1 DS2.

15:8 RO 0
30 _DS2_BYTE_3_4
7:0 RO 0
_DS2_BYTE_3 DS2.

15:8 RO 0
31 _DS1_BYTE_1_2
7:0 RO 0
_DS1_BYTE_1 DS1.

15:8 RO 0
32 _DS1_BYTE_3_4
7:0 RO 0
_DS1_BYTE_3 DS1.

15:8 RO 0
33 _DS2_BYTE_1_2
7:0 RO 0
_DS2_BYTE_1 DS2.

Bit Reset
Slice Valueh

15:8 RO 0
34 _DS2_BYTE_3_4
7:0 RO 0
_DS2_BYTE_3 DS2.

15:8 RO 0
35 _DS1_BYTE_1_2
7:0 RO 0
_DS1_BYTE_1 DS1.

15:8 RO 0
36 _DS1_BYTE_3_4
7:0 RO 0
_DS1_BYTE_3 DS1.

15:8 RO 0
37 _DS2_BYTE_1_2
7:0 RO 0
_DS2_BYTE_1 DS2.

15:8 RO 0
38 _DS2_BYTE_3_4
7:0 RO 0
_DS2_BYTE_3 DS2.

15:8 RO 0
39 _DS1_BYTE_1_2
7:0 RO 0
_DS1_BYTE_1 DS1.

15:8 RO 0
3A _DS1_BYTE_3_4
7:0 RO 0
_DS1_BYTE_3 DS1.

15:8 RO 0
3B _DS2_BYTE_1_2
7:0 RO 0
_DS2_BYTE_1 DS2.

15:8 RO 0
3C _DS2_BYTE_3_4
7:0 RO 0
_DS2_BYTE_3 DS2.

Bit Reset
Slice Valueh
When HIGH, selects the stream to override

OVERRIDE_ the link number.
OVERRIDE_STREAM
3D STREAM_ 15:0 RW 0
NUMBER _NUMBER_SEL When LOW, link numbers are not
modifiable.
PID word link number for streams 0-7 to be

embedded, if the corresponding stream is
selected through OVERRIDE_STREAM
LINK_N_TO
_INSERT_STR _NUMBER_SEL register.
3E LINK_N_0_7 15:0 RW 0
_0_7 Two bits per data stream.
Refer to Table 3-29 to Table 3-32 in data
sheet for definition of the streams.
PID word link number for streams 8-15 to

be embedded, if the corresponding stream
is selected through OVERRIDE_STREAM
LINK_N_TO
_INSERT_STR _NUMBER_SEL register.
3F LINK_N_8_15 15:0 RW 0
_8_15 Two bits per data stream.
When in manual PID replacement mode,

set bit HIGH to select PID byte override.
Bit 7 of PID_BYTE_OVERRIDE corresponds
PID_BYTE_OVERRIDE 7:4 RW 00F to PID byte 4. Bit 4 of PID_BYTE_OVERRIDE
corresponds to PID byte 1.
Note: Byte selection applies to all 16
streams.
PID_
40 RSVD 3:2 RO 0 Reserved.
PROGRAM_CTRL
When HIGH, enables fast mode PID
replacement. In fast mode, PID’s from the
PID_INS_CH0A_DS1_BYTE_1_2 and
PID_WR_FAST_MODE 1:1 RW 0
PID_INS_CH0A_DS1_BYTE_3_4 registers
are written to all streams selected by
PID_PROGRAM_STREAM_MASK.
When HIGH, enables manual PID insertion

PID_OVERRIDE 0:0 RW 0 in streams selected by
PID_PROGRAM_STREAM_MASK.

Bit Reset
Slice Valueh
When HIGH, the PID will be overridden for

the corresponding video stream.
PID_PROGRAM PID_PROGRAM_VID
41 _STREAM_MASK 15:0 RW 0 One bit per data stream.
_STREAM_MASK
When HIGH, PID error is detected.

One bit per data stream.
42 PID_ERROR PID_ERROR 15:0 RO 0
When HIGH, reports that PID is detected.

One bit per data stream.
43 PID_DETECTED PID_DETECTED 15:0 RO 0
PID_INS_CH0A PID byte 2 to be inserted in the video

15:8 RW 0
PID_INS_CH0A _DS1_BYTE_2 stream CH0A DS1.
44 _DS1_BYTE_1_2
7:0 RW 0
_DS1_BYTE_1 stream CH0A DS1.

15:8 RW 0
45 _DS1_BYTE_3_4
7:0 RW 0

15:8 RW 0
46 _DS2_BYTE_1_2
7:0 RW 0

15:8 RW 0
47 _DS2_BYTE_3_4
7:0 RW 0
PID_INS_CH0B PID byte 2 to be inserted in the video

15:8 RW 0
PID_INS_CH0B _DS1_BYTE_2 stream CH0B DS1.
48 _DS1_BYTE_1_2
7:0 RW 0
_DS1_BYTE_1 stream CH0B DS1.

Bit Reset
Slice Valueh

15:8 RW 0
49 _DS1_BYTE_3_4
7:0 RW 0

15:8 RW 0
4A _DS2_BYTE_1_2
7:0 RW 0

15:8 RW 0
4B _DS2_BYTE_3_4
7:0 RW 0
_DS2_BYTE_3 streamCH0B DS2.

15:8 RW 0
4C _DS1_BYTE_1_2
7:0 RW 0

15:8 RW 0
4D _DS1_BYTE_3_4
7:0 RW 0

15:8 RW 0
4E _DS2_BYTE_1_2
7:0 RW 0

15:8 RW 0
4F _DS2_BYTE_3_4
7:0 RW 0

15:8 RW 0
50 _DS1_BYTE_1_2
7:0 RW 0

15:8 RW 0
51 _DS1_BYTE_3_4
7:0 RW 0

Bit Reset
Slice Valueh

15:8 RW 0
52 _DS2_BYTE_1_2
7:0 RW 0

15:8 RW 0
53 _DS2_BYTE_3_4
7:0 RW 0

15:8 RW 0
54 _DS1_BYTE_1_2
7:0 RW 0

15:8 RW 0
55 _DS1_BYTE_3_4
7:0 RW 0

15:8 RW 0
56 _DS2_BYTE_1_2
7:0 RW 0

15:8 RW 0
57 _DS2_BYTE_3_4
7:0 RW 0

15:8 RW 0
58 _DS1_BYTE_1_2
7:0 RW 0

15:8 RW 0
59 _DS1_BYTE_3_4
7:0 RW 0

15:8 RW 0
5A _DS2_BYTE_1_2
7:0 RW 0

Bit Reset
Slice Valueh

15:8 RW 0
5B _DS2_BYTE_3_4
7:0 RW 0

15:8 RW 0
5C _DS1_BYTE_1_2
7:0 RW 0

15:8 RW 0
5D _DS1_BYTE_3_4
7:0 RW 0

15:8 RW 0
5E _DS2_BYTE_1_2
7:0 RW 0

15:8 RW 0
5F _DS2_BYTE_3_4
7:0 RW 0

15:8 RW 0
60 _DS1_BYTE_1_2
7:0 RW 0

15:8 RW 0
61 _DS1_BYTE_3_4
7:0 RW 0

15:8 RW 0
62 _DS2_BYTE_1_2
7:0 RW 0

15:8 RW 0
63 _DS2_BYTE_3_4
7:0 RW 0

Bit Reset
Slice Valueh
Select the input channel for the virtual

output stream 1, VI1.
VI1_CH1_SEL 13:13 RW 1
Refer to output link assignment Figure 3-8
in data sheet.

in data sheet.

in data sheet.

in data sheet.
64 VI_ASGMT_0
in data sheet.

in data sheet.
When HIGH, the virtual link assignment is

MANUAL_CTRL
3:3 RW 0 manually selected based on the registers
_LNK_ASGMT
VIx_CHx_SEL.
When HIGH, the value in register

REG_CTRL_LNK
1:1 RW 0 LNK_ASGMT_SEL_REG is used instead of
_ASGMT_SEL
the LNK_ASGMT pin setting.
LNK_ASGMT_SEL Overrides LNK_ASGMT pin setting, if

0:0 RW 0
_REG REG_CTRL_LNK_ASGMT_SEL is set HIGH.

Bit Reset
Slice Valueh
RSVD 15:3 RO A Reserved.
When HIGH, the DL12G stream assignment

MAN_CTRL_SEL_
2:2 RW 0 is manually selected based on the
DM_DL12_VIR
parameter SEL_DM_DL12_VIR
Selects between DL12G streams:

SEL_DM_DL12_VIR[0] controls DDO0 and
DDO1 selection.
65 DM_DL12_VIR
When ‘1’, DDI0 stream demuxed to DDO0 &
DDO1. When ‘0’, DDI2 stream demuxed to
SEL_DM_DL12_
1:0 RW 2 DDO0 & DDO1
VIR
SEL_DM_DL12_VIR[1] controls DDO2 &
DDO3 selection.
When ‘1’, DDI0 stream demuxed to DDO2&
DDO3. When ‘0’, DDI2 stream demuxed to
DDO2 & DDO3
Selects the primary input for MUX M0.

00 = DDI0
M0_PRIM_CH 5:4 RW 0 01 = DDI1
10 = DDI2
11 = DDI3
When the appropriate bit is asserted, the

LOST_INPUT_
66 IGNORE_CTRL selected input is replaced with the selected
primary input. By Default, all non-primary
inputs are selected to be replaced. To
disable this feature, write ‘0’ all bits.
IGNORE_LOST_INPUT 3:0 RW E
One bit per channel.
Bit 3 controls input 3
Bit 0 controls input 0
68 RSVD RSVD 15:0 RW FF Reserved.

Bit Reset
Slice Valueh
When HIGH, the reference clock is selected

TX_REF_CLK_CTLR 11:8 RW 0 from TX<n>_REF_CLK_SEL.
One bit per output.
Selects the reference clock for Tx3 if bit

TX_REF_CLK_CTLR[3] set HIGH.
TX3_REF_CLK_SEL 7:6 RW 0 00 = DDI0 extracted clock

01 = DDI1 extracted clock
10 = DDI2 extracted clock
TX_REF_CLK_SEL 11 = DDI3 extracted clock
69
TX2_REF_CLK_SEL 5:4 RW 0 TX_REF_CLK_CTLR[2] set HIGH.
See TX3_REF_CLK_SEL for selection values.



Bit Reset
Slice Valueh
When HIGH, the Tx3 reference clock is

TX3_ EXT_REF_
7:7 RW 0 sourced from TX_PCLK0 or TX_PCLK1 pins
CLK_EN
instead of DDI<n> extracted clock.
Selects between the external clocks for the

Tx3 reference clock if
TX3_ EXT_REF_ TX3_EXT_REF_CLK_EN is set HIGH.
6:6 RW 0
CLK_SEL
0 = clock from TX_PCLK0 pin
1 = clock from TX_PCLK1 pin

TX2_ EXT_REF_
CLK_EN
6A TX_ Selects between the external clocks for the

EXTERNAL_REF_ TX2_ EXT_REF_
4:4 RW 0 Tx2 reference clock if
CLK_SEL CLK_SEL
TX2_EXT_REF_CLK_EN is set HIGH.

TX1_ EXT_REF_
CLK_EN

TX1_ EXT_REF_
CLK_SEL

TX0_ EXT_REF_
CLK_EN

TX0_ EXT_REF_
CLK_SEL
6B to 6C RSVD RSVD 15:0 RW 0 Reserved.

Bit Reset
Slice Valueh
Enables extracted H-blanking on the

output on pins F14, G14, H14, and J14.
0 Bit 3 enables J14 (TIM_OUT3)

TIM_OUT_OEN 7:4 RW Bit 2 enables H14 (TIM_OUT2)
Bit 1 enables G14 (TIM_OUT1)
TIM_ Bit 0 enables F14 (TIM_OUT0)
6D
OUTPUT_ One bit per pin.
ENABLE
Enables extracted clock on the output on
pins B14, C14, D14, and E14.
Bit 3 enables E14 (RX_CLK_3)
RX_CLK_OEN 3:0 RW 0 Bit 2 enables D14 (RX_CLK_2)
Bit 1 enables C14 (RX_CLK_1)
Bit 0 enables B14 (RX_CLK_0)
One bit per pin.
Indicates status for DDI0 input.

000 = LOCK
001 = TRS_PERR
010 = PID_DETECTED
011 = PID_ERROR
STAT_3_SEL 11:9 RW 3
100 = DATA_RATE[0]
101 = DATA_RATE[1]
Combined error from all inputs.
6E STAT_CH0
110 = TRS_PERR_COMB
111 = PID_ERROR_COMB

STAT_2_SEL 8:6 RW 2
See STAT_3_SEL for selection values.

STAT_1_SEL 5:3 RW 1

STAT_0_SEL 2:0 RW 0

Bit Reset
Slice Valueh

000 = LOCK
001 = TRS_PERR
011 = PID_ERROR
101 = DATA_RATE[1]
6F STAT_CH1

STAT_6_SEL 8:6 RW 2

STAT_5_SEL 5:3 RW 1

STAT_4_SEL 2:0 RW 0

000 = LOCK
001 = TRS_PERR
011 = PID_ERROR
101 = DATA_RATE[1]
70 STAT_CH2


STAT_9_SEL 5:3 RW 1

STAT_8_SEL 2:0 RW 0

Bit Reset
Slice Valueh

000 = LOCK
001 = TRS_PERR
011 = PID_ERROR
101 = DATA_RATE[1]
71 STAT_CH3



STAT_ When bit<n> HIGH, enables STAT<n>

72 OUTPUT_ STAT_EN 15:0 RW FFFF output buffer.
ENABLE
One bit per pin.
73 DM0_DELAY_EN When HIGH, enables programmable

DELAY_EN 0:0 RW 0 inter-channel output delay in DeMUX
mode only.
Programmable delay for data stream 1.

DM0_
74 DELAY_LINK1
DELAY_LINK1 9:0 RW 0 Maximum delay of 1024 increment steps.
See Section 3.11.4 of data sheet for
explanation of delay values.

DM0_
75 DELAY_LINK2

Bit Reset
Slice Valueh

DM0_
76 DELAY_LINK3

DM0_
77 DELAY_LINK4
Resets interlink delay adjustment block.

RESET_DEL_ADJ 8:8 RW 0 Note: For all reset parameters, toggle the
parameter HIGH to LOW to perform reset.
78 RESET_0
Resets video processing block.
RESET_CH_BLOCK 7:4 RW 0
One bit per channel.
Resets input block.

RESET_IN_BLOCK 3:0 RW 0
One bit per input block.
Resets entire GS12070 digital core, except

CORE_RESET 6:6 RW 0
the CSRs.
RESET_M1 5:5 RW 0 Resets MUX M1 and DEMUX DM1 blocks.

79 RESET_1
Resets MUX M0, DEMUX DM0, and
RESET_M0 4:4 RW 0
programmable delay blocks.
Resets crosspoint.
RESET_CHAN_ASGMT 3:0 RW 0
7A to 8B RSVD RSVD 15:0 RO — Reserved.

4.2.2 Rx Control and Status Register
Table 4-6: Rx Control and Status Register
Bit Reset
Slice Valueh
1000 to
RSVD RSVD 15:0 RW — Reserved.
101A
Write 1 to upload bandwidth settings from

DDI3_CDR_LBW. The register will be
automatically set back to 0 when the CDR
DDI3_UPDATE_ bandwidth is updated.
15:15 ROSW 0
CDR_LBW Note: The DDI3_UPDATE_CDR_LBW bit is
not updated until DDI3 is enabled
(powered up in the selected mode and ISP
is LOW).
Loop bandwidth settings:

00 = LOW
01 = Default
DDI3_CDR_LBW 14:13 RW 1 10 = HIGH
11 = Default
See CDR Bandwidth Settings for bandwidth
101B DDI_CDR_LBW
values.
DDI2_UPDATE_
12:12 ROSW 0 See DDI3_UPDATE_CDR_LBW.
CDR_LBW
DDI2_CDR_LBW 11:10 RW 1 See DDI3_CDR_LBW for settings.
DDI1_UPDATE_
CDR_LBW
DDI0_UPDATE_
CDR_LBW
RSVD 3:0 RW F Reserved.
101C to
1022
Write 3 to update DDI0_EQ settings. The

DDI0_EQ_UPDATE 15:14 ROSW 0 register will automatically revert back to 0
1023 DDI0_EQ_UPDT when the settings are updated
DDI0_EQ 13:0 ROSW 908 For EQ values, see Table 3-2 in data sheet.

Table 4-6: Rx Control and Status Register (Continued)
Bit Reset
Slice Valueh



1027 to
10F9

4.2.3 Tx Control and Status Registers
Table 4-7: Tx Control and Status Registers
Bit Reset
Slice Valueh
2000 to
2013
DDO0 output Driver Amplitude settings.
Differential
DDO0_AMP
Amplitude (mVppd)
0 400
DDO0_AMP 11:9 RW 0 1 500
2 600
3 700
4 800
5 900
2014 DDO_DRV_AMP 6 1000
7 400
Note: This value will be loaded into the

GS12070 once the DDO0_DRV_AMP_
UPDATE parameter is set HIGH.
See DDO0_AMP for DDO1 Driver

DDO1_AMP 8:6 RW 0
Amplitude settings.

DDO2_AMP 5:3 RW 0
Amplitude settings.

DDO3_AMP 2:0 RW 0
Amplitude settings.
2018 to
RSVD RSVD 15:0 RW 0 Reserved.
2019

Table 4-7: Tx Control and Status Registers (Continued)
Bit Reset
Slice Valueh
See Table 3-15: DDO Loop Bandwidth

Setting.
DDO0_LBW 15:12 RW 0 Note: This value will be loaded into the
GS12070 once the DDO0_UPDATE_LBW
parameter is set HIGH.
201A DDO_LBW See Table 3-15: DDO Loop Bandwidth

DDO1_LBW 11:8 RW 0
Setting.

DDO2_LBW 7:4 RW 0
Setting.

DDO3_LBW 3:0 RW 0
Setting.
Write 1 to upload DDO loop bandwidth

settings from DDO0_LBW. The register will
be automatically set back to 0 when the
DDO0_UPDATE_LBW 3:3 ROSW 0
DDO loop bandwidth is updated.
201B DDO_LBW_UPDT Note: Bits are not updated if DDO0 is idle
(Table 3-14) or manually powered down.
DDO1_UPDATE_LBW 2:2 ROSW 0 See DDO0_UPDATE_LBW.
Write 1 to update DDO driver amplitude

DDO0_DRV_ settings from DDO0_AMP parameter. The
3:3 ROSW 0
AMP_UPDATE register will be automatically set back to 0
when the amplitude is updated.
201C DDO_DRV_UPDT DDO1_DRV_

2:2 ROSW 0 See DDO0_DRV_AMP_UPDATE.
AMP_UPDATE
DDO2_DRV_
AMP_UPDATE
DDO3_DRV_
AMP_UPDATE
201D to
2036

Bit Reset
Slice Valueh
This register provides power down control

of the DDO<n> outputs.
0 = enables DDO<n> output

1 = disables DDO<n> output
DDO<n> Power
bit group bit
Down Assignment
15 DDO0
14 DDO1
[15:12]
13 DDO2
12 DDO3
11 DDO0
10 DDO1
[11:8]
9 DDO2
OUTPUT_ OUTPUT_
2037 PWR_DOWN 15:0 RW 0 8 DDO3
PWR_DOWN
7 DDO0
6 DDO1
[7:4]
5 DDO2
4 DDO3
3 DDO0
2 DDO1
[3:0]
1 DDO2
0 DDO3
Note: The power-down bit assigned to

a DDO<n> output across four-bit
groups must be the same.
See Section 3.4.3 for more information.

Bit Reset
Slice Valueh
Enables the DDO_DISABLE register setting

– one bit per DDO output.
Bit 7 – DDO0
DDO_DISABLE_ Bit 6 – DDO1
7:4 RW 0
OW_EN Bit 5 – DDO2
Bit 4 – DDO3
DDO_DRIVER_
2038 Note: Only select bits that are related to the
DISABLE
desired output to be manually disabled.
‘1’ Disables the DDO output – one bit per

DDO output.
DDO_DISABLE 3:0 RW 0 Bit 3 – DDO0

Bit 2 – DDO1
Bit 1 – DDO2
Bit 0 – DDO3
2039 to
20C7

4.2.4 Video Pattern Generator Control Registers
Table 4-8: Video Pattern Generator Control Registers

See “Generating Video Patterns with GS12070 UHD-SDI Gearbox Application Note” (PDS-061505) for a more detailed
description of register control functions.
Bit Reset
Addressh Register Name Parameter Name R/W
Slice Valueh
Selects Luma (Y)/Chroma (C)

limits:
YC_RAMP_LIMIT_SEL 12:11 RW 0 00 = SMPTE

10 = Full
X1 = Custom limit and step for
Y ramp
Selects Luma (Y)/Chroma (C)

ramp type. See “Generating
3000 PG_MODE YC_RAMP_SEL 10:7 RW 0 Video Patterns with GS12070
UHD-SDI Gearbox Application
Note” (PDS-061505).
Set:
PG_LINE_SEL 6:6 RW 0 1 = for 2048 line standards
0 = for 1920 line standards
Selects a pattern. See

PG_PATTERN_SEL 3:0 RW 0
Table 3-33.
3001 RSVD_REG RSVD 15:0 RW 0 Reserved.

3002 H_REGION_0 Selects horizontal region for
H_REGION_0 10:0 RW 0
custom pattern.

custom pattern.

custom pattern.

custom pattern.

custom pattern.

Table 4-8: Video Pattern Generator Control Registers (Continued)
Bit Reset
Slice Valueh

custom pattern.

custom pattern.

custom pattern.

300A H_REGION_8 Selects horizontal region for
custom pattern.

300B H_REGION_9 Selects horizontal region for
custom pattern.

300C H_REGION_10 Selects horizontal region for
custom pattern.

300D H_REGION_11 Selects horizontal region for
custom pattern.

300E H_REGION_12 Selects horizontal region for
custom pattern.

300F H_REGION_13 Selects horizontal region for
custom pattern.

custom pattern.

3011 V_REGION_0 Selects vertical region for
V_REGION_0 10:0 RW 0
custom pattern.

Bit Reset
Slice Valueh

custom pattern.

custom pattern.

custom pattern.

custom pattern.

custom pattern.

custom pattern.

custom pattern.

custom pattern.

301A V_REGION_9 Selects vertical region for
custom pattern.

301B V_REGION_10 Selects vertical region for
custom pattern.

301C V_REGION_11 Selects vertical region for
custom pattern.

Bit Reset
Slice Valueh

301D V_REGION_12 Selects vertical region for
custom pattern.

301E V_REGION_13 Selects vertical region for
custom pattern.

301F V_REGION_14 Selects vertical region for
custom pattern.
3020 to
3024

3025 YRAMP_H_START
YRAMP_H_START 10:0 RW 0 Start Y/C value of the ramp.

3026 YRAMP_H_STEP
YRAMP_H_STEP 10:0 RW 0 Horizontal ramp increment.

3027 YRAMP_V_STEP
YRAMP_V_STEP 10:0 RW 0 Vertical ramp increment.
3028 Y_BLANKING Y_BLANKING 15:0 RW 40 Y value in the blanking region.
3029 C_BLANKING C_BLANKING 15:0 RW 200 C value in the blanking region.
302A to
30FF

3100 to Y_VALUE_1 to Y value for pixels on position
31FF Y_VALUE_256 Y_VALUE_1 to
9:0 RW 0 defined by H_REGION_N and
Y_VALUE_256
V_REGION_N.

3200 to C_B_VALUE_1 to
C_B_VALUE_1 to Cb value for pixels on position
32FF C_B_VALUE_256 9:0 RW 0
C_B_VALUE_256 defined by H_REGION_N and
V_REGION_N.

3300 to C_R_VALUE_1 to
C_R_VALUE_1 to Cr value for pixels on position
33FF C_R_VALUE_256 9:0 RW 0
C_R_VALUE_256 defined by H_REGION_N and
V_REGION_N.

5. Application Information
5.1 Typical Application Circuit

1 OF 4
P4 A5
IN 4.7μF
DDI0 DDO0 4.7μF
OUT
P5 A4
IN 4.7μF
DDI0 DDO0
4.7μF
OUT
P2 A3
IN 4.7μF
DDI1 DDO1 4.7μF
OUT
P3 A2
IN 4.7μF
DDI1 DDO1 4.7μF
OUT
M1 B1
IN 4.7μF DDI2 100Ω differential 100Ω differential DDO2 4.7μF
OUT
N1 controlled impedance controlled impedance C1
IN 4.7μF
DDI2 DDO2
4.7μF
OUT
K1 D1
IN 4.7μF
DDI3 DDO3 4.7μF
OUT
L1 E1
IN 4.7μF
DDI3 DDO3
4.7μF
OUT
B6 P12
IN SD_BYPASS0 SDIN IN
B7 P13
IN SD_BYPASS1 SDOUT OUT
B8 GSPI Control N14
IN SD_BYPASS2 SCLK IN
B9 M13
IN SD_BYPASS3 CS IN
IN
A7
MUX/DEMUX GS12070
A8 1kΩ ±1%
J3
IN BYPASS REXT_TX
REXT_RX L3
A9
IN MODE_SEL0 1kΩ ±1%
B10
IN MODE_SEL1
C
B11 33pF
IN MODE_SEL2
REF_IN P7
N10 REF_OUT P8
IN ISP0
N11
IN ISP1
N12
IN ISP2 C 27pF
N13 G1
IN ISP3 XTAL_IN
ABM8G
27MHz
M7 Crystal Selection
IN REFCLK_SEL0 H1 R
M8 XTAL_OUT
IN REFCLK_SEL1
100Ω
F4
IN SYS_RESET
K14
IN RESET
C 27pF
2 OF 4
TIM_OUT0 F14
OUT
G14
TIM_OUT1 OUT
H14
IN
P10
TX_PCLK0 TIM_OUT2 OUT
J14
IN
P11
TX_PCLK1 TIM_OUT3 OUT
A10
STAT0 OUT
A11
STAT1 OUT
A12
M5 STAT2 OUT
OUT TDO A13
M4 STAT3 OUT
IN TDI B12
M6 STAT4 OUT
IN TCK JTAG Control B13
L4 STAT5 OUT
IN TMS C12
L5 GS12070 STAT6 OUT
IN TRST C13
STAT7 OUT
D12
STAT8 OUT
D13
STAT9 OUT
E12
K13 STAT10 OUT
IN LINK_ASGMT
STAT11
E13
OUT
L13
IN SEC_LINK_ENABLE
STAT12
F12
OUT
L14
IN DEMUX_INPUT_SELECT
STAT13
F13
OUT
G12
H13
STAT14 OUT
IN PID_MODE0 STAT15
G13
OUT
J13
IN PID_MODE1
B14
RX_CLK_0 OUT
C14
RX_CLK_1 OUT
D14
RX_CLK_2 OUT
E14
RX_CLK_3 OUT
Figure 5-1: GS12070 Typical Application Circuit 1
Note: The capacitor on REXT_RX is recommended to filter any noise on the

sensitive analog pin.

A1
VSS
A6
VSS
A14
VSS
GS12070
Notes:
B2
VCC_IO
VSS
VCC_CORE
10nF
10nF
PDS-061012
B3
VSS
B4
C4 VSS
Final Data Sheet

RSVD B5 C3
VSS VCC_IO
10nF
10nF
C5
VCC_IO
D3
±
RSVD C2
VSS VCC_IO
C6
RSVD C9 D6
VSS VCC_IO
C7
RSVD C10 D10
10nF
10nF
VSS VCC_IO
C8
Rev.6
RSVD D2 H10
VSS VCC_IO
C11
RSVD D9 L6
VSS VCC_IO
D4
10nF
10nF
RSVD E2 L10
VSS VCC_IO
D5
RSVD E7 M3
VSS VCC_IO
February 2018
D7
RSVD E8
VSS
10nF
Local Decoupling Capacitors
10nF

D8
RSVD F1
D11 VSS
RSVD F2
E5 VSS
RSVD F8
10nF
10nF
E6 VSS
RSVD F9
E9 VSS
RSVD F10 E3
2. Bulk decoupling capacitors vary with board design.

VSS VCC_A_1V8
E10
10nF
10nF
RSVD G2 G3
VCC_A_1V8
VSS VCC_A_1V8
E11
RSVD G5 H3
VSS VCC_A_1V8
F3
RSVD G7 K3
VSS VCC_A_1V8
10nF
470nF
G9
F11 VSS
RSVD H2
1. Place local decoupling capacitors close to GS12070 power supply.

VSS
Figure 5-2: GS12070 Typical Application Circuit 2

G11
RSVD H5
4.7μF
470nF
H11 VSS
Capacitors
RSVD H7
VSS
Bulk Decoupling
H12
RSVD H9
VSS
J4
Bulk Decoupling Capacitors
4.7μF
100μF
RSVD J1
VSS
J11
RSVD J2
VSS
J12 E4
RSVD VCC_A_1V1
Power Decoupling
J8
VSS
100μF
K9 G4
VCC_A_1V1
RSVD J9 VCC_A_1V1
VSS
K10 H4
RSVD J10 VCC_A_1V1
VSS
K11 K4
RSVD K2 VCC_A_1V1
www.semtech.com
VSS
K12
RSVD K7 VSS
L11
RSVD K8
VSS
L12
RSVD L2
VSS
L7
VSS
M11
RSVD L8 VSS
VCC_A_1V1
VCC_A_1V8
M12 F7
10nF
10nF
RSVD L9 VCC_CORE
VSS
M14 G6
RSVD M2 VCC_CORE
VCC_CORE
VSS
N6 G8
RSVD M9 VCC_CORE
VSS
10nF
10nF
P6 G10
RSVD M10 VCC_CORE
VSS
H6
N2 VCC_CORE
F5 VSS
NC H8
VCC_CORE
10nF
10nF
N3
F6 VSS
NC J7
N4 VCC_CORE
J5 VSS
NC
N5 VSS
J6
10nF
10nF
NC
N7 VSS
K5
NC
N8 VSS
K6
NC
N9
4 OF 4
VSS
470nF
470nF
P1 VSS
Capacitors
Capacitors
Bulk Decoupling
Bulk Decoupling
P9 VSS
4.7μF
4.7μF
P14
VSS
3 OF 4
Proprietary & Confidential

Semtech
104 of 109
6. Package & Ordering Information
6.1 Package Dimensions
䢢 Top View
12.00±0.1 A
B
Tapered underfill area

6.77±0.1
6.97±0.1 12.00±0.1
1.5 MAX
1.5 MAX
0.15
0.20 S
1.755 MAX
0.37 1.5 MAX 1.5 MAX
0.20 S
5
Bottom View (0.800)

0.80
(0.800)
P
N
M
L
K
NOTE: All dimensions
J are in millimeters.
H
G 196 x Φ0.46±0.05
F Ø0.15Ⓜ S A B
E Ø0.08Ⓜ S
D
C 0.80
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A1 BALL PAD CORNER
Figure 6-1: Package Dimensions

6.2 Recommended PCB Footprint
0.8
0.45
12.00
10.4
10.4
Package 12.00
NOTE: All dimensions are in millimeters.
Figure 6-2: Recommended PCB Footprint
6.3 Packaging Data

Table 6-1: Packaging Data
Parameter Value
196 ball BGA / 12mm x 12mm /
Package Type
0.8mm pad pitch
Moisture Sensitivity Level MSL3
Junction to Air Thermal Resistance, j-a (at zero airflow) 23.0 °C/W
Junction to Board Thermal Resistance, j-b 11.3 °C/W
Junction to Case Thermal Resistance, j-c 0.15 °C/W
Psi, Junction-to-Top Characterization Parameter 4e-2

Pb-free and RoHS compliant Yes

6.4 Solder Reflow Profile
260
255
217
Temperature (°C)
200
150
within 30s
60 - 120s 60 - 150s
Time (s)
Figure 6-3: Maximum Pb-free Solder Reflow Profile
6.5 Marking Diagram
Figure 6-4: GS12070 Marking Diagram

6.6 Ordering Information
Table 6-2: Ordering Information
Part Number Package Temperature Range
GS12070 - IBE3 12mm x 12mm 196-Ball BGA -40ºC to +85ºC

IMPORTANT NOTICE
Information relating to this product and the application or design described herein is believed to be reliable, however such information is
provided as a guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein.
Semtech reserves the right to make changes to the product or this document at any time without notice. Buyers should obtain the latest relevant
information before placing orders and should verify that such information is current and complete. Semtech warrants performance of its
products to the specifications applicable at the time of sale, and all sales are made in accordance with Semtech’s standard terms and conditions
of sale.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS,
DEVICES OR SYSTEMS, OR IN NUCLEAR APPLICATIONS IN WHICH THE FAILURE COULD BE REASONABLY EXPECTED TO RESULT IN PERSONAL
INJURY, LOSS OF LIFE OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS
UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such
unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs damages and attorney fees which could arise.
The Semtech name and logo are registered trademarks of the Semtech Corporation. All other trademarks and trade names mentioned may be
marks and names of Semtech or their respective companies. Semtech reserves the right to make changes to, or discontinue any products
described in this document without further notice. Semtech makes no warranty, representation or guarantee, express or implied, regarding the
suitability of its products for any particular purpose. All rights reserved.
© Semtech 2018
Contact Information
Semtech Corporation
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
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GS12070

Key Features Description

GS12070 www.semtech.com 1 of 109

VCC_IO VCC_A_1V8 VCC_A_1V1 VCC_CORE VSS

DDI0 Input Video DDO0

ST 352 & Channel

GS12070 Block Diagram

GS12070 www.semtech.com 2 of 109

Version ECO Date Changes and/or Modifications

Added Section 3.12.3, PRBS Data Bypass.

Added Section 2.4, Latency.

Added Section 3.3.4 on output power down.

3 034034 October 2016 Updates to add information to Section 3.

Updated pin names in Figure 1-1, Table 1-1,

1 026325 June 2015 Minor correction on Page 1.

0 025710 June 2015 New document.

GS12070 www.semtech.com 3 of 109

GS12070 www.semtech.com 4 of 109

GS12070 www.semtech.com 5 of 109

1.1 Pin Assignment

MUX/ MODE_ High-speed differential inputs

Clock and Timing — Output

XTAL_ PID_ I/O supply

Figure 1-1: Pin Out

GS12070 www.semtech.com 6 of 109

Table 1-1: Pin Descriptions

Pin Number Name Type Description

A1, A6, A14, B2, B3,

Selects between Multiplex and Demultiplex mode.

Selects the SD data rate per channel when in Bypass mode.

Multiplex or Demultiplex conversion mode selection. See Table

C3, D3, D6, D10,

C4, C5, C6, C7, C8,

GS12070 www.semtech.com 7 of 109

Pin Number Name Type Description

D1, E1 DDO3, DDO3

The extracted parallel clock from the respective DDI/DDI input

Restarts the power-on initialization sequence.

F7, G6, G8, G10,

Device reference clock connection.

G13, G12, F13, F12,

SMPTE compliant Multiplex/Demultiplex mode.

REXT_TX Calibration resistors for high-speed inputs and outputs. Connect

Extracted horizontal timing – Rx H blanking from the

K1, L1 DDI3, DDI3 Serial digital differential input.

GS12070 www.semtech.com 8 of 109

Pin Number Name Type Description

Multi-link input order handling.

Device reset signal.

JTAG interface Test Mode Select input. This signal is decoded by

JTAG interface reset. Digital active-low reset input. Used to reset

When HIGH the M1/DM1 paths will be enabled.

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Pin Number Name Type Description

Reference Clock Selection input. Configures the reference clock

Chip Select input for the Gennum Serial Peripheral Interface

N6 RSVD — This pin has an internal pull-down resistor.

Input Signal Present.