ACS759 Datasheet

ACS759xCB
Thermally Enhanced, Fully Integrated, Hall-Effect-Based Linear Current Sensor IC

with 100 µΩ Current Conductor and Optimized Performance at 3.3 V
FEATURES AND BENEFITS DESCRIPTION

• Industry-leading noise performance through proprietary The Allegro™ ACS759 family of current sensor ICs provides
amplifier and filter design techniques economical and precise solutions for AC or DC current sensing.
• Integrated shield greatly reduces capacitive coupling Typical applications include motor control, load detection and
from current conductor to die due to high dV/dt signals, management, power supply and DC-to-DC converter control,
and prevents offset drift in high-side, high-voltage inverter control, and overcurrent fault detection.
applications
The device consists of a precision, low-offset linear Hall
• Total output error improvement through gain and offset
circuit with a copper conduction path located near the die.
trim over temperature
Applied current flowing through this copper conduction path
• Small package size, with easy mounting capability
generates a magnetic field which the Hall IC converts into a
• Monolithic Hall IC for high reliability
proportional voltage. Device accuracy is optimized through the
• Ultralow power loss: 100 µΩ internal conductor
close proximity of the magnetic signal to the Hall transducer.
resistance
A precise, proportional output voltage is provided by the
• Galvanic isolation allows use in economical, high-side
low-offset, chopper-stabilized BiCMOS Hall IC, which is
current sensing in high-voltage systems
programmed for accuracy at the factory.
Continued on the next page…
High-level immunity to current conductor dV/dt and stray
TÜV America
electric fields, offered by Allegro proprietary integrated shield
Certificate Number: UL Certified File
No.: US-29755-UL
technology, for low output voltage ripple and low offset drift
U8V 15 05 54214 037
in high-side, high-voltage applications.
PACKAGE: 5-Pin CB Package The output of the device has a positive slope (>VCC / 2) when an
increasing current flows through the primary copper conduction
path (from terminal 4 to terminal 5), which is the path used
for current sampling. The internal resistance of this conductive
path is 100 µΩ typical, providing low power loss.
The thickness of the copper conductor allows survival of the
device at high overcurrent conditions. The terminals of the
conductive path are electrically isolated from the signal leads
PSS PFF
Leadform Leadform
Continued on the next page…
Additional leadforms available for qualifying volumes
+3.3 V
1
4 VCC
IP+ CBYP
ACS759 0.1 µF
2
IP GND
CF
5
IP– 3
VIOUT VOUT
RF
Application 1: The ACS759 outputs an analog signal, VOUT , that varies linearly with the bidirectional AC or DC primary current, IP ,
within the range specified. CF is for optimal noise management, with values that depend on the application.
Typical Application
ACS759-DS, Rev. 8 February 3, 2020
MCO-0000204
ACS759xCB Thermally Enhanced, Fully Integrated, Hall-Effect-Based Linear Current Sensor IC
FEATURES AND BENEFITS (continued) DESCRIPTION (continued)

• 3.0 to 3.6 V, single supply operation (pins 1 through 3). This allows the ACS759 family of sensor ICs
• 120 kHz typical bandwidth to be used in applications requiring electrical isolation without the
• 3 µs output rise time in response to step input current use of opto-isolators or other costly isolation techniques.
• Output voltage proportional to AC or DC currents
The device is fully calibrated prior to shipment from the factory.
• Factory-trimmed for accuracy
The ACS759 family is lead (Pb) free. All leads are plated with 100%
• Extremely stable output offset voltage
matte tin, and there is no Pb inside the package. The heavy gauge
• Nearly zero magnetic hysteresis
leadframe is made of oxygen-free copper.
SELECTION GUIDE
Package Primary Sampled Sensitivity
Sens (Typ.) Current TOP
Part Number [1] Current, IP Packing [3]
Terminals Signal Pins Directionality (°C)
(A) (mV/A) [2]
ACS759LCB-050B-PFF-T Formed Formed ±50 26.4 Bidirectional
–40 to 150
ACS759LCB-100B-PFF-T Formed Formed ±100 13.2 Bidirectional
ACS759KCB-150B-PFF-T Formed Formed ±150 8.8 Bidirectional 34 pieces
–40 to 125
ACS759KCB-150B-PSS-T Straight Straight ±150 8.8 Bidirectional per tube
ACS759ECB-200B-PFF-T Formed Formed ±200 6.6 Bidirectional
–40 to 85
ACS759ECB-200B-PSS-T Straight Straight ±200 6.6 Bidirectional
[1] Additionalleadform options available for qualified volumes.

[2] WithVCC = 3.3 V.
[3] Contact Allegro for additional packing options.
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Unit
Forward Supply Voltage VCC 8 V
Reverse Supply Voltage VRCC –0.5 V
Forward Output Voltage VIOUT 28 V
Reverse Output Voltage VRIOUT –0.5 V
Output Source Current IOUT(Source) VIOUT to GND 3 mA
Output Sink Current IOUT(Sink) VCC to VIOUT 1 mA
Range E –40 to 85 °C
Nominal Operating Ambient Temperature TOP Range K –40 to 125 °C
Range L –40 to 150 °C
Maximum Junction TJ(max) 165 °C
Storage Temperature Tstg –65 to 165 °C
ISOLATION CHARACTERISTICS
Agency type-tested for 60 seconds per
Dielectric Strength Test Voltage* VISO 4800 VAC
UL standard 60950-1, 2nd Edition
For basic (single) isolation per UL standard 60950-1, 2nd 990 VDC or Vpk
Working Voltage for Basic Isolation VWFSI
Edition 700 Vrms
For reinforced (double) isolation per UL standard 60950- 636 VDC or Vpk
Working Voltage for Reinforced Isolation VWFRI
1, 2nd Edition 450 Vrms
* Allegro does not conduct 60-second testing. It is done only during the UL certification process.
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THERMAL CHARACTERISTICS: May require derating at maximum conditions

Characteristic Symbol Test Conditions [1] Value Unit
Mounted on the Allegro evaluation board with
2800 mm2 (1400 mm2 on component side and
1400 mm2 on opposite side) of 4 oz. copper
connected to the primary leadframe and with
Package Thermal Resistance RθJA 7 °C/W
thermal vias connecting the copper layers.
Performance is based on current flowing
through the primary leadframe and includes the
power consumed by the PCB.
[1] Additional thermal information available on the Allegro website.
TYPICAL OVERCURRENT CAPABILITIES [2][3]

TA = 25°C, 1 second duration, 1% duty cycle 1200 A
Overcurrent IPOC TA = 85°C, 1 second duration, 1% duty cycle 900 A
TA = 150°C, 1 second duration, 1% duty cycle 600 A
[2] Test was done with Allegro evaluation board. The maximum allowed current is limited by TJ(max) only.
[3] For more overcurrent profiles, please see FAQ on the Allegro website, www.allegromicro.com.
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+3 to 3.6 V
IP+ VCC
To all subcircuits
Dynamic Offset
Cancellation
VIOUT
Filter
Amp Out
0.1 µF
Gain Offset
Gain Temperature Offset Temperature
Coefficient Coefficient
Trim Control
IP– GND
Functional Block Diagram
Terminal List
IP+ 4 Number Name Description
3 VIOUT
1 VCC Device power supply terminal
2 GND
2 GND Signal ground terminal
1 VCC 3 VIOUT Analog output signal
IP– 5
4 IP+ Terminal for current being sampled
5 IP– Terminal for current being sampled
Pinout Diagram
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COMMON OPERATING CHARACTERISTICS [1]: Valid at TOP = –40°C to 150°C and VCC = 3.3 V, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Supply Voltage VCC 3 3.3 3.6 V
Supply Current ICC Output open – 10 13.5 mA
Power-On Delay tPOD TA = 25°C – 10 – µs
IP step = 60% of IP+, 10% to 90% rise time, TA = 25°C,
Rise Time [2] tr – 3 – µs
COUT = 0.47 nF
Propagation Delay Time [2] tPROP TA = 25°C, COUT = 0.47 nF – 1 – µs
Response Time tRESPONSE Measured as sum of tPROP and tr – 4 – µs
Internal Bandwidth [3] BWi –3 dB; TA = 25°C, COUT = 0.47 nF – 120 – kHz
Output Load Resistance RLOAD(MIN) VIOUT to GND 4.7 – – kΩ
Output Load Capacitance CLOAD(MAX) VIOUT to GND – – 10 nF
Primary Conductor Resistance RPRIMARY TA = 25°C – 100 – µΩ
Symmetry [2] ESYM Over half-scale of IP – 100 – %
Quiescent Output Voltage [4] VIOUT(Q) IP = 0 A, TA = 25°C – VCC/2 – V
Ratiometry [2] VRAT VCC = 3 to 3.6 V – 100 – %
[1] Device is factory-trimmed at 3.3 V, for optimal accuracy.

[2] See Characteristic Definitions section of this datasheet.
[3] Calculated using the formula BW = 0.35 / t .
i r
[4] V
IOUT(Q) may drift over the lifetime of the device by as much as ±20 mV.
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X050B PERFORMANCE CHARACTERISTICS [1]: TOP = –40°C to 150°C, VCC = 3.3 V, unless otherwise specified
Primary Sampled Current IP –50 – 50 A
SensTA Full scale of IP applied for 5 ms, TA = 25°C – 26.4 – mV/A
Sensitivity Sens(TOP)HT Full scale of IP applied for 5 ms, TOP = 25°C to 150°C – 26.5 – mV/A
Sens(TOP)LT Full scale of IP applied for 5 ms,TOP = –40°C to 25°C – 26 – mV/A
Noise [2] VNOISE TA= 25°C, 10 nF on VIOUT pin to GND – 6.6 – mV
Nonlinearity ELIN Up to full scale of IP , IP applied for 5 ms – <±1 – %
VOE(TA) IP = 0 A, TA = 25°C – ±5 – mV
Electrical Offset Voltage [3] VOE(TOP)HT IP = 0 A, TOP = 25°C to 150°C – ±10 – mV
VOE(TOP)LT IP = 0 A, TOP = –40°C to 25°C – ±25 – mV
Magnetic Offset Error IERROM IP = 0 A, TA = 25°C, after excursion of 50 A – 125 – mA
ETOT(HT) Over full scale of IP , IP applied for 5 ms, TOP = 25°C to 150°C – ±1.5 – %
Total Output Error [4]
ETOT(LT) Over full scale of IP , IP applied for 5 ms, TOP = –40°C to 25°C – ±3.5 – %
[1] See Characteristic Performance Data page for parameter distributions over temperature range.
[2] ±3 sigma noise voltage.
[3] V
OE(TOP) drift is referred to ideal VIOUT(Q)
= 1/2 VCC.
[4] Percentage of I . Output filtered.
P
Sens(TOP)LT Full scale of IP applied for 5 ms, TOP = –40°C to 25°C – 13 – mV/A
Noise [2] VNOISE TA= 25°C, 10 nF on VIOUT pin to GND – 4 – mV
VOE(TA) IP = 0 A, TA = 25°C – ±5 – mV
ETOT(HT) Over full scale of IP , IP applied for 5 ms, TOP = 25°C to 150°C – ±1.8 – %
ETOT(LT) Over full scale of IP , IP applied for 5 ms, TOP = –40°C to 25°C – ±4 – %
[2] ±3 sigma noise voltage.
[3] V
OE(TOP) drift is referred to ideal VIOUT(Q)
= 1/2 VCC.
P
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Sens(TOP)LT Full scale of IP applied for 5 ms, TOP = –40°C to 25°C – 8.6 – mV/A
VOE(TA) IP = 0 A, TA = 25°C – ±5 – mV
ETOT(HT) Over full scale of IP , IP applied for 5 ms, TOP = 25°C to 125°C – ±2 – %
[2] ±3sigma noise voltage.
[3] V
OE(TOP) drift is referred to ideal VIOUT(Q) = /2 VCC.
1
P
X200B PERFORMANCE CHARACTERISTICS1: TOP = –40°C to 85°C, VCC = 3.3 V, unless otherwise specified
Sens(TOP)LT Full scale of IP applied for 5 ms, TOP = –40°C to 25°C – 6.5 – mV/A
VOE(TA) IP = 0 A, TA = 25°C – ±5 – mV
ETOT(HT) Over full scale of IP , IP applied for 5 ms, TOP = 25°C to 85°C – ±2 – %
[2] ±3sigma noise voltage.
[3] V
OE(TOP) drift is referred to ideal VIOUT(Q) = /2 VCC .
1
P
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CHARACTERISTIC PERFORMANCE DATA

Data taken using the ACS759LCB-050B
Accuracy Data
Electrical Offset Voltage versus Ambient Temperature Sensitivity versus Ambient Temperature
40 27.5
30 27.0
Sens (mV/A)
20 26.5
VOE (mV)
10 26.0
0 25.5
-10 25.0
-20 24.5
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
Nonlinearity versus Ambient Temperature Symmetry versus Ambient Temperature

1.20 100.40
100.20
1.00
100.00
0.80 99.80
ESYM (%)
ELIN (%)
99.60
0.60 99.40
99.20
0.40 99.00
98.80
0.20
98.60
0 98.40
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
Magnetic Offset Error versus Ambient Temperature Total Output Error versus Ambient Temperature
160 4
140
2
120
0
100
IERROM (mA)
ETOT (%)
80 -2
60
-4
40
-6
20
0 -8
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
Typical Maximum Limit Mean Typical Minimum Limit
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Accuracy Data
30 13.8
25
13.6
20
Sens (mV/A)
15 13.4
VOE (mV)
10
13.2
5
0 13.0
-5 12.8
-10
12.6
-15
-20 12.4
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)

0.70 100.40
100.20
0.60
100.00
0.50
99.80
ESYM (%)
ELIN (%)
0.40 99.60
0.30 99.40
99.20
0.20
99.00
0.10
98.80
0 98.60
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
250 4
200 2
0
150
IERROM (mA)
ETOT (%)
-2
100
-4
50
-6
0 -8
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
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Accuracy Data
30 9.2
25
9.0
20
Sens (mV/A)
15 8.8
VOE (mV)
10
8.6
5
0 8.4
-5
8.2
-10
-15 8.0
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)

0.60 100.40
100.20
0.50
100.00
0.40
99.80
ESYM (%)
ELIN (%)
0.30 99.60
99.40
0.20
99.20
0.10
99.00
0 98.80
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
300 6
250 4
2
200
IERROM (mA)
0
ETOT (%)
150
-2
100
-4
50 -6
0 -8
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
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Accuracy Data
25 6.9
20 6.8
15 6.7
Sens (mV/A)
10 6.6
VOE (mV)
5 6.5
0 6.4
-5 6.3
-10 6.2
-15 6.1
–60 -40 -20 0 20 40 60 80 100 –60 -40 -20 0 20 40 60 80 100
TA (°C) TA (°C)

0.50 100.40
0.45 100.30
0.40
100.20
0.35
ESYM (%)
100.10
ELIN (%)
0.30
0.25 100.00
0.20 99.90
0.15
99.80
0.10
0.05 99.70
0 99.60
–60 -40 -20 0 20 40 60 80 100 –60 -40 -20 0 20 40 60 80 100
TA (°C) TA (°C)
350 4
300 2
250
0
IERROM (mA)
200
ETOT (%)
-2
150
-4
100
50 -6
0 -8
–60 -40 -20 0 20 40 60 80 100 –60 -45 -20 0 20 40 60 80 100
TA (°C) TA (°C)
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Data taken using the ACS759LCB-100
Timing Data
Rise Time Propagation Delay Time
IP (20 A/div.) IP (20 A/div.)
VIOUT (0.5 V/div.) VIOUT (0.5 V/div.)
2.988 µs 997 ns
t (2 µs/div.) t (2 µs/div.)
Response Time Power-on Delay
VCC
IP (20 A/div.)
VIOUT (0.5 V/div.)

9.034 µs
VIOUT (1 V/div.)
(IP = 60 A DC)
3.960 µs
t (2 µs/div.) t (2 µs/div.)
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CHARACTERISTIC DEFINITIONS
Definitions of Accuracy Characteristics
Sensitivity (Sens). The change in device output in response to a The ratiometric change (%) in the quiescent voltage output is
1 A change through the primary conductor. The sensitivity is the defined as:
product of the magnetic circuit sensitivity (G / A) and the linear VIOUTQ(VCC) VIOUTQ(3.3V)
∆VIOUTQ(∆V) = × 100 (%)
IC amplifier gain (mV/G). The linear IC amplifier gain is pro- VCC 3.3 (V)
grammed at the factory to optimize the sensitivity (mV/A) for the
and the ratiometric change (%) in sensitivity is defined as:
half-scale current of the device.
Sens(VCC) Sens(3.3V)
Noise (VNOISE). The noise floor is derived from the thermal and ∆Sens(∆V) = × 100 (%)
shot noise observed in Hall elements. Dividing the noise (mV) VCC 3.3 (V)
by the sensitivity (mV/A) provides the smallest current that the Quiescent output voltage (VIOUT(Q)). The output of the device
device is able to resolve. when the primary current is zero. For bidirectional devices,
it nominally remains at VCC ⁄ 2. Thus, VCC = 3.3 V translates
Nonlinearity (ELIN). The degree to which the voltage output into VIOUT(QBI) = 1.65 V. For unidirectional devices, it nomi-
from the IC varies in direct proportion to the primary current nally remains at 0.1 × VCC. Thus, VCC = 3.3 V translates into
through its half-scale amplitude. Nonlinearity in the output can be VIOUT(QUNI) = 0.33 V. Variation in VIOUT(Q) can be attributed
attributed to the saturation of the flux concentrator approaching to the resolution of the Allegro linear IC quiescent voltage trim,
magnetic hysteresis, and thermal drift.
the half-scale current. The following equation is used to derive
the linearity: Electrical offset voltage (VOE). The deviation of the device out-
put from its ideal quiescent value of VCC ⁄ 2 for bidirectional and
{ [
100 1–
∆ gain × % sat ( VIOUT_half-scale amperes –VIOUT(Q) )
2 (VIOUT_quarter-scale amperes – VIOUT(Q) ) [{ 0.1 × VCC for unidirectional devices, due to nonmagnetic causes.
Magnetic offset error (IERROM). The magnetic offset is due to
where the residual magnetism (remnant field) of the core material. The
magnetic offset error is highest when the magnetic circuit has
∆ gain = the gain variation as a function of temperature changes been saturated, usually when the device has been subjected to a
from 25°C, full-scale or high-current overload condition. The magnetic offset
% sat = the percentage of saturation of the flux concentra- is largely dependent on the material used as a flux concentrator.
tor, which becomes significant as the current being sampled The larger magnetic offsets are observed at the lower operating
temperatures.
approaches half-scale ±IP , and
VIOUT_half-scale amperes = the output voltage (V) when the sampled Total Output Error (ETOT). The maximum deviation of the
current approximates half-scale ±IP . actual output from its ideal value, also referred to as accuracy,
illustrated graphically in the output voltage versus current chart
Symmetry (ESYM). The degree to which the absolute voltage on the following page.
output from the IC varies in proportion to either a positive or ETOT is divided into four areas:
negative half-scale primary current. The following equation is
• 0 A at 25°C. Accuracy at the zero current flow at 25°C,
used to derive symmetry: without the effects of temperature.
VIOUT_+ half-scale amperes – VIOUT(Q) • 0 A over Δ temperature. Accuracy at the zero current flow
 VIOUT(Q) – VIOUT_–half-scale amperes 
100 including temperature effects.
• Half-scale current at 25°C. Accuracy at the the half-scale
Ratiometry. The device features a ratiometric output. This current at 25°C, without the effects of temperature.
means that the quiescent voltage output, VIOUTQ, and the mag- • Half-scale current over Δ temperature. Accuracy at the half-
netic sensitivity, Sens, are proportional to the supply voltage, VCC. scale current flow including temperature effects.
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Definitions of Dynamic Response Characteristics
Power-On Time (tPO). When the supply is ramped to its operat-

ing voltage, the device requires a finite time to power its internal
components before responding to an input magnetic field.
Power-On Time, tPO , is defined as the time it takes for the output
voltage to settle within ±10% of its steady-state value under an
applied magnetic field, after the power supply has reached its
minimum specified operating voltage, VCC(min), as shown in the
chart at right.
Rise time (tr). The time interval between a) when the device
reaches 10% of its full-scale value, and b) when it reaches 90%
of its full scale value. The rise time to a step response is used to
derive the bandwidth of the device, in which ƒ(–3 dB) = 0.35 / tr.
Both tr and tRESPONSE are detrimentally affected by eddy current Output Voltage versus Sampled Current
losses observed in the conductive IC ground plane. Total Output Error at 0 A and at Half-Scale Current
Accuracy
Increasing VIOUT(V) Over ∆Temp erature
I (%) Primary Current
Accuracy
90 25°C Only
Bidirectional
Average
Transducer Output VIOUT
10
Accuracy
0 Over ∆Temp erature
t
Rise Time, tr
Accuracy
25°C Only
Propagation delay (tPROP). The time required for the device IP(min)
output to reflect a change in the primary current signal. Propaga- –IP (A) +IP (A)
tion delay is attributed to inductive loading within the linear IC Half Scale
IP(max)
package, as well as in the inductive loop formed by the primary
conductor geometry. Propagation delay can be considered as a 0A
fixed time offset and may be compensated. Decreasing VIOUT(V)
Primary Current Accuracy

I (%) 25°C Only
90 Accuracy
Over ∆Temp erature
Accuracy
Transducer Output Increasing VIOUT(V) Over ∆Temp erature
0
Accuracy
t 25°C Only
Propagation Time, tPROP
Unidirectional
Average
VIOUT
Accuracy
Over ∆Temp erature
Accuracy
25°C Only
–IP (A) +IP (A)
Full Scale
0A IP(max)
Decreasing VIOUT(V)
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Chopper Stabilization Technique

Chopper Stabilization is an innovative circuit technique that is ponents which are beyond the user’s frequency range of interest.
used to minimize the offset voltage of a Hall element and an asso-
As a result of this chopper stabilization approach, the output
ciated on-chip amplifier. The technique nearly eliminates Hall IC voltage from the Hall IC is desensitized to the effects of tempera-
output drift induced by temperature or package stress effects. ture and mechanical stress. This technique produces devices that
This offset reduction technique is based on a signal modulation- have an extremely stable Electrical Offset Voltage, are immune to
demodulation process. Modulation is used to separate the unde- thermal stress, and have precise recoverability after temperature
sired DC offset signal from the magnetically induced signal in the cycling.
frequency domain. Then, using a low-pass filter, the modulated This technique is made possible through the use of a BiCMOS
DC offset is suppressed while the magnetically induced signal process that allows the use of low-offset and low-noise amplifiers
passes through the filter. The anti-aliasing filter prevents aliasing in combination with high-density logic integration and sample
from happening in applications with high frequency signal com- and hold circuits.
Regulator
Clock/Logic
Low-Pass
Hall Element
Filter
Sample and
Anti-aliasing
Hold
Filter
Amp
Concept of Chopper Stabilization Technique
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PACKAGE OUTLINE DRAWINGS
For Reference Only – Not for Tooling Use

(Reference DWG-9111 & DWG-9110)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
14.0 ±0.2 0.5

4.0 ±0.2 3.5 ±0.2 R 1.0
R 2.05
3.0 ±0.2 R 3.0
1.50 ±0.10 1º±2°
5 4
Ø 0.5 B
3 4
17.5 ±0.2
21.4
13.00 ±0.10
Branded
Face
4.40 ±0.10
Ø 0.8
1.9 ±0.2 Ø 1.5

2.9 ±0.2
0.51 ±0.10
1 2 3
+0.060 1.91
0.381
–0.030 5º±5°
10.00 ±0.10 B PCB Layout Reference View
3.5 ±0.2
NNNNNNN
7.00 ±0.10 TTT-AAA
LLLLLLL
A Dambar removal intrusion
B Perimeter through-holes recommended YYWW
C Branding scale and appearance at supplier discretion 1

C Standard Branding Reference View
N = Device part number
T = Temperature code
A = Amperage range
L = Lot number
Y = Last two digits of year of
manufacture
W = Week of manufacture
= Supplier emblem
Creepage distance, current terminals to signal pins: 7.25 mm

Clearance distance, current terminals to signal pins: 7.25 mm
Package mass: 4.63 g typical
Package CB, 5-pin Package, Leadform PFF
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For Reference Only – Not for Tooling Use

(Reference DWG-9111, DWG-9110)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
14.0 ±0.2
4.0 ±0.2
3.0 ±0.2
5 4
1.50 ±0.10
2.75 ±0.10
A NNNNNNN
TTT-AAA
23.50 ±0.5
LLLLLLL
13.00 ±0.10
YYWW
4.40 ±0.10 Branded 1

Face
B Standard Branding Reference View
1 2 3 N = Device part number
3.18 ±0.10 T = Temperature code
11.0 ±0.05 1.9 ±0.2 A = Amperage range
L = Lot number
+0.060
0.51 ±0.10 0.381 Y = Last two digits of year of
–0.030
manufacture
W = Week of manufacture
= Supplier emblem
10.00 ±0.10
7.00 ±0.10
A Dambar removal intrusion
B Branding scale and appearance at supplier discretion
Creepage distance, current terminals to signal pins: 7.25 mm

Clearance distance, current terminals to signal pins: 7.25 mm
Package mass: 4.63 g typical
Package CB, 5-pin Package, Leadform PSS
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REVISION HISTORY
Number Date Description
1 January, 2013 Update Isolation certifications and specifications; update to current terminology
2 April 8, 2015 Updated TUV certification and reformatted document
3 November 2, 2016 Updated PCB Layout Reference View in Package Outline Drawing on page 17
4 June 5, 2017 Updated product status
5 June 1, 2018 Updated recommended substitution
6 December 5, 2018 Updated TUV/UL Certification
7 May 31, 2019 Updated TUV certificate mark
8 February 3, 2020 Updated product status
Copyright 2020, Allegro MicroSystems.

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improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
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Allegro’s product can reasonably be expected to cause bodily harm.
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ACS759 Datasheet

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ACS759 Datasheet

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ACS759xCB

Thermally Enhanced, Fully Integrated, Hall-Effect-Based Linear Current Sensor IC

FEATURES AND BENEFITS DESCRIPTION

FEATURES AND BENEFITS (continued) DESCRIPTION (continued)

[1] Additionalleadform options available for qualified volumes.

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS: May require derating at maximum conditions

[1] Additional thermal information available on the Allegro website.

TYPICAL OVERCURRENT CAPABILITIES [2][3]

Functional Block Diagram

[1] Device is factory-trimmed at 3.3 V, for optimal accuracy.

CHARACTERISTIC PERFORMANCE DATA

Nonlinearity versus Ambient Temperature Symmetry versus Ambient Temperature

Typical Maximum Limit Mean Typical Minimum Limit

CHARACTERISTIC PERFORMANCE DATA

Nonlinearity versus Ambient Temperature Symmetry versus Ambient Temperature

Typical Maximum Limit Mean Typical Minimum Limit

CHARACTERISTIC PERFORMANCE DATA

Nonlinearity versus Ambient Temperature Symmetry versus Ambient Temperature

Typical Maximum Limit Mean Typical Minimum Limit

CHARACTERISTIC PERFORMANCE DATA

Nonlinearity versus Ambient Temperature Symmetry versus Ambient Temperature

Typical Maximum Limit Mean Typical Minimum Limit

CHARACTERISTIC PERFORMANCE DATA

Rise Time Propagation Delay Time

IP (20 A/div.) IP (20 A/div.)

VIOUT (0.5 V/div.) VIOUT (0.5 V/div.)

Response Time Power-on Delay

VIOUT (0.5 V/div.)

Definitions of Dynamic Response Characteristics

Power-On Time (tPO). When the supply is ramped to its operat-

fixed time offset and may be compensated. Decreasing VIOUT(V)

Primary Current Accuracy

–IP (A) +IP (A)

Chopper Stabilization Technique

Concept of Chopper Stabilization Technique

PACKAGE OUTLINE DRAWINGS

For Reference Only – Not for Tooling Use

14.0 ±0.2 0.5

1.9 ±0.2 Ø 1.5

C Branding scale and appearance at supplier discretion 1

Creepage distance, current terminals to signal pins: 7.25 mm

Package CB, 5-pin Package, Leadform PFF

For Reference Only – Not for Tooling Use

4.40 ±0.10 Branded 1

Creepage distance, current terminals to signal pins: 7.25 mm

Package CB, 5-pin Package, Leadform PSS

Copyright 2020, Allegro MicroSystems.

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