Introduction MicroController

Chapter 1

ARM Embedded Systems
The ARM processor core is a key component of many successful 32-
bit embedded systems.
 ARM cores are widely used in mobile phones, handheld organizers,
and a multitude of other everyday portable consumer devices.
 ARM’s designers have come a long way from the first ARM1 prototype
in 1985.
 The ARM company bases their success on a simple and powerful
original design,
 Which continues to improve today through constant technical
innovation.
 In fact, the ARM core is not a single core, but a whole family of
designs sharing similar design principles and a common instruction
set.
 In this first chapter we discuss how the RISC (reduced instruction set
computer) design philosophy was adapted by ARM to create a flexible
embedded processor.
 We then introduce an example embedded device and discuss the
typical hardware and software technologies that surround an ARM
processor.
The RISC design philosophy
 The ARM core uses a RISC architecture.
 RISC is a design philosophy aimed at delivering simple but
powerful instructions that execute within a single cycle at a
high clock speed.
 The RISC philosophy concentrates on reducing the
complexity of instructions performed by the hardware
because it is easier to provide greater flexibility and
intelligence in software rather than hardware.
 As a result, a RISC design places greater demands on the
compiler.
 In contrast, the traditional complex instruction set computer
(CISC) relies more on the hardware for instruction
functionality, and consequently the CISC instructions are
more complicated.
RISC and CISC Major Differences
The RISC philosophy is implemented with four major design
rules:
1. Instructions—RISC processors have a reduced number of
instruction classes. These classes provide simple operations
that can each execute in a single cycle. The compiler or
programmer synthesizes complicated operations (for
example, a divide operation) by combining several simple
instructions. Each instruction is a fixed length to allow the
pipeline to fetch future instructions before decoding the
current instruction. In contrast, in CISC processors the
instructions are often of variable size and take many cycles
to execute.
2. Pipelines—The processing of instructions is broken down
into smaller units that can be executed in parallel by
pipelines. Ideally the pipeline advances by one step on each
cycle for maximum throughput. Instructions can be decoded
in one pipeline stage. There is no need for an instruction to
be executed by a mini-program called microcode as on CISC
processors.
3. Registers—RISC machines have a large general-purpose

register set. Any register can contain either data or an
address. Registers act as the fast local memory store for all
data processing operations. In contrast, CISC processors have
dedicated registers for specific purposes.
4. Load-store architecture—The processor operates on data held in
registers. Separate load and store instructions transfer data
between the register bank and external memory. Memory accesses
are costly, so separating memory accesses from data processing
provides an advantage because you can use data items held in the
register bank multiple times without needing multiple memory
accesses. In contrast, with a CISC design the data processing
operations can act on memory directly.
 These design rules allow a RISC processor to be simpler, and thus

the core can operate at higher clock frequencies. In contrast,
traditional CISC processors are more complex and operate at
lower clock frequencies. Over the course of two decades, however,
the distinction between RISC and CISC has blurred as CISC
processors have implemented more RISC concepts.
The ARM Design Philosophy
 There are a number of physical features that have driven the
ARM (Advanced RISC Machines) processor design.
 First, portable embedded systems require some form of
battery power.
 The ARM processor has been specifically designed to be
small to reduce power consumption and extend battery
 operation—essential for applications such as mobile phones
and personal digital assistants (PDAs).
 High code density is another major requirement since
embedded systems have limited memory due to cost and/or
physical size restrictions.
 High code density is useful for applications that have limited
on-board memory, such as mobile phones and mass storage
devices.
 ARM has incorporated hardware debug technology within
the processor so that software engineers can view what is
happening while the processor is executing code.
 With greater visibility, software engineers can resolve issues
faster, which has a direct effect on the time to market and
reduces overall development costs.
 The ARM core is not a pure RISC architecture because of the
constraints of its primary application—the embedded
system.
 The strength of the ARM core is that it does not take the
RISC concept too far.
 In today’s systems the key is not raw processor speed but
total effective system performance and power consumption.
Instruction Set for Embedded Systems
 The ARM instruction set differs from the pure RISC
definition in several ways that make the ARM instruction set
suitable for embedded applications:
 Variable cycle execution for certain instructions—Not every
ARM instruction executes in a single cycle. For example,
load-store-multiple instructions vary in the number of
execution cycles depending upon the number of registers
being transferred. The transfer can occur on sequential
memory addresses, which increases performance since
sequential memory accesses are often faster than random
accesses. Code density is also improved since multiple
register transfers are common operations at the start and end
of functions.
 Inline barrel shifter leading to more complex instructions—
The inline barrel shifter is a hardware component that pre-
processes one of the input registers before it is used by an
instruction. This expands the capability of many instructions
to improve core performance and code density.
 Thumb 16-bit instruction set—ARM enhanced the processor

core by adding a second 16-bit instruction set called Thumb
that permits the ARM core to execute either 16- or 32-bit
instructions. The 16-bit instructions improve code density by
about 30% over 32-bit fixed-length instructions.
 Conditional execution—An instruction is only executed when
a specific condition has been satisfied. This feature improves
performance and code density by reducing branch
instructions.
 Enhanced instructions—The enhanced digital signal

processor (DSP) instructions were added to the standard
ARM instruction set to support fast 16×16-bit multiplier
operations and saturation. These instructions allow a faster-
performing ARM processor in some cases to replace the
traditional combinations of a processor plus a DSP.
 These additional features have made the ARM processor one

of the most commonly used 32-bit embedded processor
cores.

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Chapter 1

3. Registers—RISC machines have a large general-purpose

 These design rules allow a RISC processor to be simpler, and thus

 Thumb 16-bit instruction set—ARM enhanced the processor

 Enhanced instructions—The enhanced digital signal

 These additional features have made the ARM processor one

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