Data Sheet: Single-Channel, Software Configurable Input and Output With HART Modem
Data Sheet: Single-Channel, Software Configurable Input and Output With HART Modem
Data Sheet: Single-Channel, Software Configurable Input and Output With HART Modem
AD74115H
Single-Channel, Software Configurable Input and Output with HART Modem
Rev. 0
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Data Sheet AD74115H
TABLE OF CONTENTS
REVISION HISTORY
VOLTAGE OUTPUT
AVDD = +6 V to +28.8 V, AVSS = −2.5 V to −18 V, AGND = DGND = 0 V, REFIN = +2.5 V (ideal), DVCC = +2.7 V to +5.5 V, AVCC = +4.5 V
to +5.5 V, and all specifications are at TA = −40°C to +105°C, unless otherwise noted. The sense resistor (RSENSE) = 100 Ω (ideal), the load
resistor (RLOAD) = 100 kΩ, and the load capacitor (CLOAD) = 4.7 nF per the recommended configuration. Note that the headroom specification
for AVDD and AVSS must be considered when setting supply voltages.
VOLTAGE INPUT
AVDD = +6 V to +28.8 V, AVSS = −2.5 V to −18 V, AGND = DGND = 0 V, REFIN = +2.5 V (ideal), DVCC = +2.7 V to +5.5 V, AVCC = +4.5
V to +5.5 V, and all specifications are at TA = −40°C to +105°C, unless otherwise noted. RSENSE = 100 Ω (ideal), and CLOAD = 4.7 nF per the
recommended configuration. Note that the required input range for AVDD and AVSS must be considered when setting the supply voltages.
CURRENT INPUT EXTERNALLY POWERED AND CURRENT INPUT EXTERNALLY POWERED WITH
HART
AVDD = +6 V to +28.8 V, AVSS = −2.5 V to −18 V, AGND = DGND = 0 V, REFIN = +2.5 V (ideal), DVCC = +2.7 V to +5.5 V, AVCC = +4.5
V to +5.5 V, and all specifications are at TA = −40°C to +105°C, unless otherwise noted. RSENSE = 100 Ω (Ideal), and CLOAD = 4.7 nF per the
recommended configuration.
Table 4. Current Input Externally Powered and Current Input Externally Powered with HART
Parameter Min Typ Max Unit Test Conditions/Comments
CURRENT INPUT
Input Resolution 16 Bits
Input Range 0 25 mA Sensed across the external 100 Ω resistor
Screw Terminal Voltage 0 V
Short-Circuit Current Limit 25 35 mA Nonprogrammable
ACCURACY
TUE1 −0.1 +0.1 % FSR
TUE at 25°C1 −0.05 +0.05 % FSR
INL −4 ±2 +4 LSB Linearity specified from 0.1 mA to 25 mA
Offset Error −4 +4 LSB
Offset Error at 25°C −1.5 +1.5 LSB
Gain Error1 −250 +250 ppm FSR
Gain Error at 25°C1 −150 +150 ppm FSR
OTHER INPUT SPECIFICATIONS
In order
DC PSRR2 of noise
Input Impedance (Without HART Termination) 165 Ω Current input, externally powered selected, including 100 Ω RSENSE
Input Impedance (with HART Resistive 230 330 Ω Current input, externally powered with HART selected, including
Termination) 100 Ω RSENSE
Compliance (Without HART Termination)2 4.2 V Current input, externally powered selected, and minimum voltage
required at the I/OP screw terminal to sink 25 mA
Compliance (with HART Resistive Termination)2 6.6 V Current input, externally powered with HART selected, and
minimum voltage required at the I/OP screw terminal to sink 20
mA
CURRENT INPUT LOOP POWERED AND CURRENT INPUT LOOP POWERED WITH HART
AVDD = +6 V to +28.8 V, AVSS = −2.5 V to −18 V, AGND = DGND = 0 V, REFIN = +2.5 V (ideal), DVCC = +2.7 V to +5.5 V, AVCC = +4.5
V to +5.5 V, and all specifications are at TA = −40°C to +105°C, unless otherwise noted. RSENSE = 100 Ω (iIdeal), and CLOAD = 4.7 nF per the
recommended configuration. Note that the headroom specification for AVDD must be considered when setting supply voltages.
Table 5. Current Input Loop Powered and Current Input Loop Powered with HART
Parameter Min Typ Max Unit Test Conditions/Comments
CURRENT INPUTS
Input Resolution 16 Bits
Input Range 0 25 mA Sensed across external 100 Ω resistor
Screw Terminal Voltage AVDD V
NonHART Current Limit 0 25 mA Programmable current limit, 14-bit resolution
HART Mode Current Limit 23 30 mA Current input, loop powered with HART enabled, nonprogrammable
Table 5. Current Input Loop Powered and Current Input Loop Powered with HART
Parameter Min Typ Max Unit Test Conditions/Comments
ACCURACY
TUE1 −0.1 +0.1 % FSR
TUE at 25°C1 −0.05 +0.05 % FSR
INL −4 +4 LSB Linearity specified from 0.1 mA to 25 mA range
Offset Error −4 +4 LSB
Offset Error at 25°C −1.5 +1.5 LSB
Gain Error1 −250 +250 ppm FSR
Gain Error at 25°C1 −150 +150 ppm FSR
OTHER INPUT SPECIFICATIONS
DC PSRR2 In order
of noise
Input Impedance (Without HART 165 Ω With current input, loop powered selected, includes 100 Ω RSENSE
Termination)
Input Impedance (with HART Resistive 230 330 Ω With current input, loop powered with HART selected, includes 100 Ω RSENSE
Termination)
Headroom (Without HART Termination)2 3.8 V Minimum required difference between AVDD and the I/OP screw terminal
voltage to source 25 mA, and current input, loop powered selected
Headroom (with HART Resistive 6.0 V Minimum required difference between AVDD and the I/OP screw terminal
Termination)2 voltage to source 20 mA, and current input, loop powered with HART selected
ADC SPECIFICATIONS
AVDD = +6 V to +28.8 V, AVSS = −2.5 V to −18 V, AGND = DGND = 0 V, REFIN = +2.5 V (ideal), DVCC = +2.7 V to +5.5 V, AVCC = +4.5
V to +5.5 V, and all specifications are at TA = −40°C to +105°C, unless otherwise noted. RSENSE = 100 Ω (ideal) and CLOAD = 4.7 nF per the
recommended configuration. Note that the required input range for AVDD and AVSS must be considered when setting the supply voltages.
GENERAL SPECIFICATIONS
AVDD = +6 V to +28.8 V, AVSS = −2.5 V to −18 V, AGND = DGND = 0 V, REFIN = +2.5 V (ideal), DVCC = +2.7 V to +5.5 V, AVCC = +4.5
V to +5.5 V, and all specifications are at TA = −40°C to +105°C, unless otherwise noted. RSENSE = 100 Ω (ideal) and CLOAD = 4.7 nF per the
recommended configuration.
TIMING CHARACTERISTICS
1 All input signals are specified with tR= tF= 5 ns (10% to 90% of the voltage on the DVCC pin (VDVCC)) and timed from a voltage level of VDVDD/2.
2 Guaranteed by design and characterization; not production tested.
3 Charge pump voltage decays while in reset.
4 See Figure 53.
1 All input signals are specified with tR= fall time tF = 5 ns (10% to 90% of the voltage on the DVDD pin (VDVDD)) and timed from a voltage level of VDVDD/2.
2 Guaranteed by design and characterization; not production tested.
VOLTAGE OUTPUT
Figure 5. Screw Terminal Voltage (VSCREW) and SYNC Pin Voltage (VSYNC) vs.
Time on Voltage Output Enabled Figure 8. Output Voltage Change (VOUT, DELTA) vs. Source and Sink Current
Figure 9. Screw Terminal Voltage (VSCREW) and SYNC Pin Voltage (VSYNC) vs.
Time on Current Output Enable Figure 12. AVDD Voltage Headroom vs. IOUT
Figure 10. Current Output (IOUT) and SYNC Pin Voltage (VSYNC) vs. Time
Figure 11. IOUT Settling Time with Inductive Load and with and Without Slew
Rate Enabled
RESISTANCE MEASUREMENT
Figure 13. 2-Wire Resistance Measurement Accuracy Figure 16. 4-Wire RTD Measurement Error
REFERENCE
ADC
Figure 20. ADC Noise Histogram with Output Data Rate (ODR) = 10 SPS Figure 23. ADC Noise Histogram with ODR = 4.8 kSPS
Figure 21. ADC Noise Histogram with ODR = 20 SPS Figure 24. ADC Noise Histogram with ODR = 9.6 kSPS
DIGITAL OUTPUT
HART—IOUT MODE
Figure 27. Carrier Start Time Figure 30. Carrier Detect Off Time (Till ALERT Pin Change to High)
OTHERS
The AD74115H is a single-channel, software configurable input On-chip line protectors ensure that the I/OP screw terminal does
and output that is designed to meet the requirements of isolated not provide power to the IC when brought to a higher potential than
process control and factory automation applications. The device the AVDD pin.
provides a fully integrated single chip solution for input and output
operation. The AD74115H features a 16-bit, Σ-Δ ADC and a 14-bit The recommended external components shown in Figure 32 and
DAC, and the device is packaged in a 7 mm × 7 mm, 48-lead Table 36, including the TVS, are selected to withstand surges on
LFCSP. The AD74115H also includes an integrated HART modem. the input and output terminals.
The channel is configured by writing to the configuration registers. With the recommended components, the I/OP and I/ON screw
Users can refine the default configurations of each operation mode terminals tolerate overvoltages up to dc ± 36 V (limited by the
via the AD74115H register map. See Figure 32 for a detailed external TVS).
functional block diagram of the AD74115H. A cyclic redundancy check (CRC) function is built into the SPI to
ensure error free communications in noisy environments.
ROBUST ARCHITECTURE
POWER SUPPLIES AND REFERENCE
The AD74115H system is robust in noisy environments and can
withstand overvoltage scenarios such as miswire and surge events. Four external voltage supply rails are required to power up the
AD74115H: VAVDD, which is the positive analog supply, VAVSS,
which is the negative analog supply, VAVCC, which is the low voltage
analog supply, and VDVCC, which is the digital supply. See Table High Impedance
14 for the voltage range of the three external supplies and the
associated conditions. High impedance is the default function upon power-up or after a
device reset.
Powering on the AD74115H If a channel is held in high impedance for an extended time, such
When powering up the AD74115H, apply ground connections first. as when the analog input and output functions are not in use,
After power-up, the user must wait for the device power-up time it is recommended to enable a sinking burnout current of 1 μA.
(see Table 14) before any transaction to the device can take place. Enable the burnout current by programming the following bits in the
I_BURNOUT_CONFIG register:
Upon initial power-up or a device reset of the AD74115H, the
output channel is disabled and placed in a high impedance state by ► BRN_VIOUT_EN to 1
default. ► BRN_VIOUT_POL to 0
► BRN_VIOUT_CURR to 100 binary
Charge Pump
Interpreting ADC Data
The AD74115H has an internal charge pump that can be enabled to
provide AVSS, the negative voltage supply. When only unipolar ca- In high impedance mode, the ADC, by default, measures the
pability is required, the charge pump can eliminate the requirement voltage across the screw terminals (I/OP to I/ON) in a 0 V to 12
for the external AVSS supply voltage. Enable the charge pump V range. Use the following equation to calculate the ADC measure-
using the CPUMP_EN bit. For correct operation, the charge pump ment result:
requires an external capacitor (CPUMP fly capacitor) between the VADC = (ADC_CODE/65,536) × Voltage Range
CPUMP_N pin and CPUMP_P pin. Externally connect the CP_OUT
pin to AVSS. where:
VADC is the measured voltage in volts.
If using the charge pump, take care not to apply an external supply ADC_CODE is the value of the ADC_RESULT1 register.
to the AVSS pin. Voltage Range is the measurement range of the ADC and is 12 V.
When the charge pump is enabled, the ±12V bipolar output range is
disabled. Voltage Output
The voltage output amplifier can generate unipolar or bipolar voltag-
Reference es in the 0 V to +12 V and ±12 V, ranges respectively. Each range
The AD74115H can operate with either an external or an internal has 14 bits of resolution. The voltage on the low-side of the RSENSE
reference. The reference input requires 2.5 V for the AD74115H is sensed on the SENSEL pin via a 2 kΩ resistor, which closes the
to function correctly. The reference voltage is internally buffered feedback loop and maintains stability.
before being applied to the DAC and the ADC. If using the internal In voltage output mode, the output range is set to 0 V to 12 V by
reference, the REFIN pin must be tied to the REFOUT pin. default. To select bipolar mode, use the following sequence:
DEVICE FUNCTIONS ► Write 0x2000 to the DAC_CODE register to ensure 0 V output.
The following sections describe the various programmable device ► Set the VOUT_RANGE bit in the OUTPUT_CONFIG register to 1
functions of the AD74115H with block diagrams and guidelines on for bipolar outputs.
how to interpret the ADC results if converting with the default set- ► Select the voltage output use case in the CH_FUNC bits,
tings. These functions are programmed within the CH_FUNC_SET- CH_FUNC_SETUP register.
UP register.
Figure 33 shows the current, voltage, and measurement paths of
Each device function is configured with default measurement set- the voltage output mode.
tings. However, users can adjust these settings as required within
the register map.
Short-Circuit Detection
There are two available short-circuit limits that can be selected
by setting the I_LIMIT bit in the OUTPUT_CONFIG registers. See
Table 1 for the specified short-circuit current values. If the selected
short-circuit limit is reached on a channel, a voltage output short-cir-
cuit error is flagged for that channel, and the ALERT pin asserts.
where:
IRSENSE is the measured current in amps. A negative current
indicates that the current is sourced from the AD74115H. A positive
current indicates that the AD74115H is sinking the current.
VMIN is the minimum voltage of the selected ADC range, which is
−2.5 V by default.
ADC_CODE is the value of the ADC_RESULT1 register.
Voltage Range is the full span of the ADC range, which is 5 V.
RSENSE is the RSENSE resistor, which is 100 Ω.
Current Output Figure 34 shows the current, voltage, and measurement paths of
the current output mode.
In current output mode, the DAC provides a current output on
the VIOUT pin that is regulated by sensing the differential voltage
across RSENSE by using the SENSEL and SENSEH pins.
Short-Circuit Protection and Detection source of typically 30 mA is enabled when the current input, loop
powered with HART mode is selected.
The current from the AD74115H is limited by the programmable
DAC code. The mode can provide resistive termination in current input, loop
powered mode. Input impedance is set to a minimum of 230 Ω to be
In current input loop powered mode, the digital input comparator is compliant with the HART receive impedance.
enabled by default to detect a short circuit.
The digital input comparator is enabled with a threshold voltage Resistance Measurement (2-Wire RTD)
of AVDD/2 and with the output inverted. During normal operation, The resistance measurement configuration biases an external 2-
the voltage on I/OP is typically within 5 V of the VAVDD. If the wire RTD with a voltage derived from a 2.5 V bias. The resultant
load is short circuited to ground, the voltage on the I/OP is pulled excitation current flows through the 2 kΩ and 100 Ω resistors
to ground. When the voltage on the I/OP screw terminal falls to (shown as RPULLUP in Figure 38). This configuration ensures an
less than the programmed threshold level, the comparator trips low, accurate ratiometric measurement. The 16-bit, Σ-∆ ADC automat-
setting the ANALOG_IO_SC bit in the ALERT_STATUS register. ically digitizes the voltage across the RTD. The low excitation
Interpreting ADC Data current ensures that the power dissipated by the RTD is minimized,
reducing self heating. See Figure 38 for an example of the RTD
In current input loop, powered mode, the ADC, by default, meas- bias circuit.
ures the current flowing from the AD74115H into the I/OP screw
terminal through the RSENSE in a 25 mA range. Use the ADC meas-
urement result to calculate the current with the following equation:
ADC_CODE
× Voltage Range
65, 536
IRSENSE = RSENSE
where:
IRSENSE is the measured current in amps.
ADC_CODE is the value of the ADC_RESULT1 register. Figure 38. RTD Bias Circuit
Voltage Range is the full ADC span of the ADC range and is 2.5 V.
RSENSE is the sense resistor, which has a value of 100 Ω. It is essential that the AGND_SENSE pin connects to the low-side
of the measured RTD. Figure 39 shows the current, voltage, and
Current Input, Loop Powered with HART measurement paths of the resistance measurement configuration.
Compatibility Mode
The resistance measurement mode can be used for 2-wire RTD
This mode is a HART-compatible version of the current input, loop measurements, but also as a diagnostic of the attached load. Load
powered mode. However, the current source is not programmable; impedance can be used for load detection techniques or to help to
therefore, configuring of the DACs is not needed. A current-limit determine the health of the load over time.
Interpreting ADC Data range of the ADC is determined by the voltage across the reference
resistor, RREF, guaranteeing a fully ratiometric measurement.
In resistance measurement mode, the 16-bit, Σ-∆ ADC automatical-
ly digitizes the voltage across the RTD in a 2.5 V range. The excitation currents applied to the RTD terminals can be pro-
gramed to one of four values between 250 µA to 1 mA in the
When a conversion is carried out, the ADC code reflects the ratio RTD3W4W_CONFIG register. See Table 7 for the full list of excita-
between the RTD and the RPULL-UP. Use the ADC code to calculate tion currents. Select the excitation current according to the RTD in
the RTD resistance with the following equation: use.
ADC_CODE × RPULL − UP
RRTD = 65, 536 − ADC_CODE
Take care that the voltage generated on the SENSEHF pin (I1 ×
(RREF + RRTD)) is less than VAVCC. The SENSEHF pin voltage
where: provides the positive reference to the ADC and must not exceed the
RRTD is the calculated RTD resistance in ohms. value of VAVCC.
ADC_CODE is the code of the ADC_RESULT1 registers.
RPULL-UP has a value of 2100 Ω. Three measurement ranges are available in 3-wire RTD mode.
These ranges are listed in Table 7. The measurement range can be
Do not change the CONV1_MUX bits in the settings of the configured in the ADC_CONFIG register using the CONV1_RANGE
ADC_CONFIG register if in RTD mode. Changing from the default bits. Select the best range to suit the RTD in use.
ADC mux configuration results in a void ADC result.
When the 3-wire or 4-wire RTD mode is selected, the AD74115H
3-Wire RTD Measurements is automatically configured to measure a 3-wire RTD in a Pt100
range. In this case, an excitation current of 1 mA is used, and the
3-wire RTD measurements are supported with the AD74115H. Use ADC measurement range is set to 0 V to 0.625 V.
the CH_FUNC bits in the CH_FUNC_SETUP register to configure
If a Pt1000 measurement is required, it is recommended to use a
the channel in 3-wire or 4-wire RTD mode.
500 μA excitation current with the ADC range set to 0 V to 12 V.
Figure 40 shows a simplified configuration of the 3-wire RTD
For a lower resistance RTD, for example Cu10, it is recommended
method. Matched excitation currents, I1 and I2 are sourced to two of
to use 1 mA excitation current, and the ADC range set to ±104 mV.
the RTD leads. The third lead is connected to ground. One of the
excitation currents, I1, generates a voltage across the RTD and lead The ADC measurement range can be changed by writing to the
resistance RL1. The second excitation current, I2, generates a drop CONV1_RANGE bits in the ADC_CONFIG register. The excitation
across RL2. The resultant voltage across terminals T1 and T2 is currents can be changed by writing to the RTD_CURRENT bits in
equivalent to the voltage drop across the RTD. (It is assumed that the RTD3W4W_CONFIG register.
the lead resistances are matched, that is, RL1 = RL2 = RL3).
The voltage between the T1 and T2 terminals is measured by the
ADC using the SENSELF and SENSE_EXT1 pins. The full-scale
How to Configure a 3-Wire RTD Measurement When using bipolar ADC ranges, use the ADC code to calculate the
for Pt1000 RTD RTD resistance with the following equation:
ADC_CODE ‐ 32,763
The following is an example of how to configure a 3-wire RTD RRTD = 32,768 × ADC_GAIN × RREF + 0.2
measurement for the Pt1000 RTD:
where:
► Select 3-wire or 4-wire resistance measurement in the RRTD is the calculated RTD resistance in ohms.
CH_FUNC_SETUP register. ADC_CODE is the code of the ADC_RESULT1 register.
► Set CONV1_MUX to SENSELF to SENSE_EXT1 and RREF has a value of 2100 Ω (the combined value of the SENSEH
CONV1_RANGE to 0 V to 12 V in the ADC_CONFIG register. and RSENSE resistors).
► Set RTD_CURRENT to 500 μA and RTD_MODE_SEL to 3-wire ADC_GAIN is the gain of the ADC in the selected ADC range.
RTD mode in the RTD3W4W_CONFIG register. When using the ±104 mV range (Cu10), the ADC_GAIN is 24.
► Set CONV1_EN and CONV_SEQ to start continuous conver-
sions in the ADC_CONV_CTRL register. 4-Wire RTD Measurements
Open-Circuit Detection 4-wire RTD measurements are supported with the AD74115H. Use
the CH_FUNC_SETUP register to configure the channel in 3-wire
An open-circuit detect feature is available on the leads of the 3-wire or 4-wire RTD mode. Configure the RTD_MODE_SEL bit for 4-wire
RTD. The combination of excitation current and RTD and lead RTD measurements in the RTD3W4W_CONFIG register.
resistances generates voltages on the SENSEH and SENSE_EXT1
pins. If the voltage on either of these pins exceeds the short-circuit Figure 41 shows a simplified configuration of 4-wire RTD method.
detect voltage (shown in Table 7), an open-circuit signal is asserted An excitation current, I1 is sourced to a single lead of the RTD via
in the ALERT_STATUS register. SENSEH. The fourth lead is connected to ground.
There is no current flow in second and third leads of the RTD that
Interpreting ADC Data are connected to SENSE_EXT2 and SENSE_EXT1, respectively;
In 3-wire RTD mode, configure the 16-bit, Σ-Δ ADC to measure therefore, these pins are used to sense the voltage directly across
the voltage from SENSELF to SENSE_EXT1. When a conversion the RTD.
is carried out, the ADC code reflects the ratio between RRTD and The full-scale range of the ADC is determined by the voltage across
RREF. RREF, guaranteeing a fully ratiometric measurement.
When using unipolar ADC ranges, use the ADC code to calculate The excitation current applied to the RTD terminal can be pro-
the RTD resistance with the following equation: gramed to one of four values between 250 µA to 1 mA using
ADC_CODE+5 the RTD_CURRENT bits in the RTD3W4W_CONFIG register. See
RRTD = × RREF + 0.2
65,536 × ADC_GAIN Table 7 for the full list of excitation currents. Select the excitation
where: current according to the RTD in use. Take care that the voltage
RRTD is the calculated RTD resistance in ohms. generated on the SENSEHF pin (I1 × (RREF + RRTD)) is less than
ADC_CODE is the code of the ADC_RESULT1 register. VAVCC. The SENSEHF pin voltage provides the positive reference
RREF has a value of 2100 Ω (the combined value of the SENSEH to the ADC and must not exceed the value of VAVCC.
and RSENSE resistors). The measurement range can be configured in the ADC_CONFIG
ADC_GAIN is the gain of the ADC in the selected ADC range. register using the CONV1_RANGE bits. Select the best range to
When using the 0 V to 0.625 V range (Pt100), the ADC_GAIN is 4. suit the RTD in use.
When using the 0 V to 12 V range (Pt1000), the ADC_GAIN is
1/4.8.
How to Configure a 4-Wire RTD Measurement ADC_CODE is the code of the ADC_RESULT1 register.
for Pt100 RTD RREF has a value of 2100 Ω (the combined value of the SENSEH
and RSENSE resistors).
The following is an example of how to configure a 4-wire RTD ADC_GAIN is the gain of the ADC in the selected ADC range.
measurement for the Pt100 RTD: When using the 0 V to 0.625 V range (Pt100), the ADC_GAIN is 4.
► Select 3-wire or 4-wire resistance measurement in the When using the 0 V to 12 V range (Pt1000), the ADC_GAIN is
CH_FUNC_SETUP register. 1/4.8.
► Set CONV1_MUX to SENSE_EXT2 to SENSE_EXT1 and
CONV1_RANGE to 0 V to 0.625 V in the ADC_CONFIG register. When using bipolar ADC ranges, use the ADC code to calculate the
► Set RTD_CURRENT to 1 mA and RTD_MODE_SEL to 4-wire
RTD resistance with the following equation:
RTD mode in the RTD3W4W_CONFIG register. ADC_CODE ‐ 32,763
RRTD = 32,768 × ADC_GAIN × RREF
► Set CONV1_EN and CONV_SEQ to start continuous conver-
sions in the ADC_CONV_CTRL register. where:
RRTD is the calculated RTD resistance in ohms.
Open-Circuit Detection ADC_CODE is the code of the ADC_RESULT1 register.
RREF has a value of 2100 Ω (the combined value of the SENSEH
The combination of excitation current and load resistance gener-
and RSENSE resistors).
ates a voltage on the SENSEH pin. If the voltage generated on
ADC_GAIN is the gain of the ADC in the selected ADC range.
the SENSEH pin is greater than the open-circuit detect voltage
When using the ±104 mV range (Cu10), the ADC_GAIN is 24.
specified in Table 8, an open-circuit signal is asserted in the
ALERT_STATUS register. This signal indicates an open-circuit con-
dition on either T1 or Tl 4 (see Figure 41). Digital Input Logic
The burnout currents can determine if the SENSE_EXT1 or The digital input circuit can convert high voltage digital inputs from
SENSE_EXT2 pins are open circuit (see the Burnout Currents the I/OP screw terminal to low voltage logic signals on the GPIO_B
section). pin or on the SPI.
An externally powered sensor provides a high voltage digital input
Interpreting ADC Data on the I/OP screw terminal. The unfiltered screw terminal voltage
In 4-wire RTD mode, configure the 16-bit, Σ-Δ ADC to measure the on the SENSEL pin can be routed to the on-chip comparator. Use
voltage from SENSE_EXT2 to SENSE_EXT1. When a conversion the DIN_UNBUF_EN bit in the DIN_CONFIG2 register to bypass
is carried out, the ADC code reflects the ratio between RRTD and the input buffer if high speed digital input data rates are required.
RREF. See Table 9 for buffered and unbuffered data rates.
When using unipolar ADC ranges, use the ADC code to calculate The digital input comparator compares the voltage of the input
the RTD resistance with the following equation: signal to a programmable threshold (see the Digital Input Threshold
Setting section for additional information). To debounce the compa-
ADC_CODE+5 rator output, see the Debounce Function section.
RRTD = 65,536 × ADC_GAIN × RREF
where: Monitor the comparator output by reading from the
RRTD is the calculated RTD resistance in ohms. DIN_COMP_OUT register or on the GPIO_A pin. The GPIO_A
pin is configured via the GPIO_CONFIGx register to drive out the Figure 42 shows the current, voltage, and output paths of the digital
debounced digital input signal. input logic mode.
The ADC is not required for digital input operation. However, the
ADC is available for voltage and current measurements while the
digital input logic mode is enabled.
counter can be programmed to count the positive edges or the Table 21. Digital Input Programmable Debounce Times
negative edges, which depend on whether the digital input inverter DEBOUNCE_TIME Code (Hex) Debounce Time (ms)
is used. Enable the digital input counter and configure the inverter 07 0.0756
in the DIN_CONFIG1 register. The count value is accessed in the 08 0.1008
DIN_COUNTER register. 09 0.1301
The counter is reset to 0 when the device is reset. When the 0A 0.1805
counter reaches full scale, it rolls over to 0. The counter freezes if 0B 0.2406
the COUNT_EN bit is set to 0. 0C 0.3203
0D 0.4203
Digital Input Data Rates 0E 0.5602
When the AD74115H is configured in digital input mode, the voltage 0F 0.7504
on the SENSEL pin is buffered and monitored by the digital input 10 1.0008
comparator. Table 9 shows the specified data rate. 11 1.3008
12 1.8008
To enable higher data rates, a high speed, unbuffered option is
13 2.4008
available to allow the comparator to monitor high speed signals. For
14 3.2008
unbuffered operation, the voltage on the VIOUT pin is monitored by
the digital input comparator. Refer to Table 9 for the specified data 15 4.2008
rate for high speed mode. Enable the unbuffered mode by setting 16 5.6008
the DIN_UNBUF_EN bit in the DIN_CONFIG2 register. 17 7.5007
18 10.0007
If using unbuffered mode while sourcing or sinking current to the 19 13.0007
load via the VIOUT pin, consider the voltage drop across RSENSE 1A 18.0006
(100 Ω) and the VIOUT line protector (15 Ω) when setting the
1B 24.0006
threshold voltage.
1C 32.0005
Debounce Function 1D 42.0004
1E 56.0003
The digital input comparator outputs are sampled at regular inter- 1F 75.0000
vals and passed to a user-programmable debounce operation.
The comparator outputs can be debounced for a user-programma-
ble amount of time via the 5-bit DEBOUNCE_TIME bits within Debounce Mode 0 (Default)
the DIN_CONFIG1 register. Set these bits to 0x00 to bypass the
debouncer. Table 21 shows the available programmable debounce In this mode, the sampled comparator outputs are counted. A
times. high sample occurrence is counted in one direction (either up or
down), whereas a low sample occurrence is counted in the opposite
The debounce circuit has the following two modes of operation: direction. The DIN_COMP_OUT register changes state when the
Debounce Mode 0 and Debounce Mode 1. Both modes are pro- programmed counter target is reached.
grammed via the DEBOUNCE_MODE bit in the DIN_CONFIG1
register. Figure 43 shows an example of Debounce Mode 0 in operation.
The debounce time is set to 100 μs in the DIN_CONFIG1 register.
Table 21. Digital Input Programmable Debounce Times
A clock with an approximate period of 800 ns sample counts
DEBOUNCE_TIME Code (Hex) Debounce Time (ms) the comparator signal. After the comparator signal changes state
00 Bypass from the current debounced signal, the debounce function counter
01 0.0130 begins to count the duration of the signal at the new state. The
02 0.0187 count direction changes if the comparator signal reverts back to
03 0.0244 the original state. After the counter reaches the target count, the
04 0.0325 DIN_COMP_OUT register is updated with the state of the compara-
05 0.0423 tor signal.
06 0.0561
Digital Input, Loop Powered voltage proportional to the VAVDD. See the Digital Input Threshold
Setting section for more information on the programmable threshold
Like the current output mode function (see the Current Output voltages.
(IOUT) and IOUT with HART section), the digital input, loop pow-
ered function configures the output stage to provide a high-side The output of the comparators can be debounced (see the De-
current output that can power an external sensor. Program the bounce Function section), passed directly, or inverted to the SPI
DAC_CODE register to provide the required current source limit. and/or to the GPIO_A pin.
The I/OP screw terminal voltage can be monitored by the digital The digital input comparator outputs are monitored by reading from
input function. The unfiltered voltage on the SENSEL pin can be the DIN_COMP_OUT register. The comparator outputs can also be
routed to the on-chip comparator. Use the DIN_UNBUF_EN bit in monitored with the GPIO_A pin. The GPIO_A pin is configured via
the DIN_CONFIG2 register to bypass the input buffer if high speed the GPIO_CONFIGx register to drive out the debounced compara-
digital input data rates are required. See Table 9 for buffered and tor output signal.
unbuffered data rates. Figure 45 shows the current, voltage, and output paths of the digital
This comparator compares the voltage on the selected pin to a input, loop powered mode configuration.
programmable threshold that can either be a fixed voltage or a
Interpreting ADC Data the RSET and short-circuit voltage values. Short-circuit voltages are
indicated in the Table 11.
The ADC is not required for digital input operation. However, the
ADC is available for voltage and current measurements when the Configure the digital output using the DO_EXT_CONFIG register:
digital input, loop powered mode is enabled. In digital input, loop ► Select source, sink, or push-pull capability by using the
powered mode, the ADC, by default, measures the voltage across DO_EXT_MODE bits.
the I/OP to I/ON screw terminals in a 0 V to 12 V range. Use
► Select the source of the data for the digital output circuit using
the ADC measurement result to calculate this voltage by using the
following equation: the DO_EXT_SRC_SEL bit. The digital output data can be pro-
vided by the SPI (via the DO_DATA_EXT bit) or by the GPIO_B
VADC = (ADC_CODE/65,536) × Voltage Range pin for direct hardware control of the circuits.
► Configure the short-circuit timers using the DO_EXT_T1 and
where:
VADC is the measured voltage in volts. DO_EXT_T2 bits. See the Short-Circuit Protection section for
ADC_CODE is the value of the ADC_RESULT1 register. more information on short-circuit functionality. Note that T1 short-
Voltage Range is 12 V, the measurement range of the ADC. circuit limits are not available in push-pull mode
Once the configuration settings are applied, provide stimulus to
Digital Output turn on the selected external FET. For SPI control, a new write is re-
quired to the DO_EXT_CONFIG register, to set the DO_DATA_EXT
The AD74115H supports sourcing and sinking digital outputs. An
bit. Setting the DO_DATA_EXT to 1 turns on the selected external
internal digital output function is available for sourcing or sinking up
FET. In push-pull mode, set the bit to 0 to drive a low on the output
to 100 mA continuous current. For currents higher than 100 mA,
and to 1 to drive a high on the output.
use the external digital output function. A push-pull feature is also
available that combines both the source and sink capabilities to For GPIO control, configure the GPIO_x pin to control the digital
provide high speed, high voltage switching. output circuit by writing 0x0004 to the GPIO_CONFIGx register.
Drive the GPIO_x pin high to turn on the FET. In push-pull mode,
When the digital output functionality is enabled, the recommended
set the GPIO_x pin low for a low on the output and high for a high
configuration of the CH_FUNC_SETUP register is to set it to high
on the output.
impedance.
If changing from one digital output function to another, first disable
Sourcing and Sinking Currents Greater Than the digital output function before changing to the new mode (set
100 mA DO_EXT_MODE to digital output external disable).
The external sourcing digital output operates with an external, Figure 46 shows the current and voltage paths of the sourcing
P-channel field effect transistor (PFET), and the sinking digital digital output mode with the external FET. Figure 47 shows the
output operates with external N-channel FET (NFET). Push-pull current and voltage paths of the sinking digital output mode with the
mode uses both PFET and NFET. Choose the FET types to suit the external FETs.
application requirements. Determine the absolute current value by
Smart Diode The AD74115H has a smart diode feature when using the external
digital output function. An additional FET is connected, along with a
In current sourcing applications, a blocking diode is typically placed resistor and protection Zener, as shown in Figure 48. The gate of
in series with the output FETs to ensure that the digital output the FET is controlled by the DO_SRC_DGATE pin. When the FET
path is protected against reverse overvoltage conditions (when the is disabled, the body diode of the FET conducts. When the FET
I/OP screw terminal voltage is greater than the DO_VDD voltage, is enabled, the power dissipated is calculated by P = I2R, where I
VDO_VDD). This typical configuration is shown in Figure 46. is the sourced current, and R is the RON of the FET. Typically, the
Significant power can be dissipated in this diode when the digital power dissipation in this scenario is <50 mW.
output circuit is sourcing high currents (for example, a 500 mA To enable the smart diode option, set DO_EXT_MODE to an exter-
current source and a diode drop of 0.5 V generates 250 mW of nal source with a smart diode in the DO_EXT_CONFIG register.
power).
Figure 48. Smart Diode Configuration for Current Sourcing with an External FET
Sourcing and Sinking Currents up to 100 mA For GPIO control, configure the GPIO_x pinto control the digital
output circuit by writing 0x0004 to the GPIO_CONFIGx register.
Internal FETs are available to source or sink up to 100 mA continu- Drive the GPIO_x pin high to turn on the FET. In push-pull mode,
ous current. A 200 mA start-up current is also accommodated. Us- set the pin low for a low on the output and high for a high on the
ing the internal FETs to provide the digital output current eliminates output.
the need for external FETs. Push-pull mode uses both the sourcing
and sinking internal FETs. Configure the digital output using the If changing from one digital output function to another, first disable
DO_INT_CONFIG register: the digital output function before changing to the new mode (set
DO_INT_MODE to digital output internal disable).
► Select source, sink, or push-pull capability using the
DO_INT_MODE bits. The power and isolation companion chip, ADP1034, can provide
► Select the source of the data for the digital output circuit using the power required to operate the AD74115H in digital output
the DO_INT_SRC_SEL bit. The digital output data can be provid- mode (using the internal FETs) sourcing continuous currents up to
ed by SPI (via the DO_DATA_INT bit) or by the GPIO_C pin for 100 mA. The ADP1034 also accommodates the 200 mA start-up
faster output rates. current. In this case, the AVDD pin can be externally connected to
► Configure the short-circuit timers using the DO_INT_T1 and the DO_VDD pin, eliminating the need for an additional DO_VDD
DO_INT_T2 bits. See the Short-Circuit Detection section for supply source.
more information on short-circuit functionality. Note that T1 short- Figure 49 shows the current and voltage paths of the digital output
circuit limits are not available in push-pull mode. sourcing mode with the internal FET.
Once the configuration settings are applied, a new write is required Figure 50 shows the current and voltage paths of the digital output
to the DO_INT_CONFIG register, to set the DO_DATA_INT bit. sinking mode with the internal FET.
Setting the DO_DATA_INT to 1 turns on the selected FET. In
push-pull mode, set the bit to 0 to drive a low on the output and to 1
to drive a high on the output.
Figure 49. Digital Output Sourcing Mode with the Internal FET
Figure 50. Digital Output Sinking Mode with the Internal FET
Thermal Shutdown once the digital output FET is turned on using the DO_DATA_INT or
DO_DATA_EXT bit (for internal FETs or external FETs, respective-
When the internal digital output is enabled, a thermal shutdown ly), even if no short-circuit event was triggered. If a short-circuit
function is automatically enabled to protect the AD74115H in short- event occurs, the digital output FET remains on, clamped at the
circuit scenarios. higher short-circuit current for the remainder of the programmed
If the output drivers reach the disable temperature specified in duration of T1. The short-circuit alert is not triggered during this
Table 11, the digital output is disabled. The DO_THERM_RESET time.
bit is set in the ALERT_STATUS register to indicate that thermal A second short-circuit limit is deployed once the T1 time elapses,
shutdown of the digital output circuit has occurred. is a lower current limit, and is active for a programmable duration
Once the die temperature reaches the specified reenabled temper- of time, T2. The T2 counter only starts counting if T1 expires and a
ature in Table 11, the digital output circuit attempts to turn back short circuit is detected. The FET remains on during a short-circuit
on. If the high power dissipation condition persists, the die quickly event, but the current is limited to the lower short-circuit current for
reaches the disabled temperature again. Take care to manage the the programmed duration of T2.
power dissipation to prevent multiple disable and reenable cycles The T2 counter is an up and down counter: when in short circuit,
on the internal digital output. the time increments. If the short-circuit condition goes away, the
time count decrements.
Short-Circuit Protection
T1 and T2 can be programmed in the DO_EXT_CONFIG register
When using the external digital output, short-circuit protection is for external FETs or DO_INT_CONFIG register for internal FETs.
achieved using a current-limit setting resistor, RSET. A short-circuit If the higher short-circuit current limit is not required, T1 can be
event is triggered when the voltage developed across the resistor disabled. See Table 11 for the specified short-circuit values and T1
reaches the short-circuit voltage specified in Table 11. In the event and T2 durations for both internal and external modes of operation.
of a short circuit, the DO_EXT_SC bit is set in the ALERT_STATUS
register, which in turn asserts the ALERT pin. If the short circuit continues to persist after the T2 time expires,
the FET automatically disables. Once disabled, the relevant digital
When using the internal digital output, a short circuit is triggered output timeout bit is set in the ALERT_STATUS register. The digital
when the current reaches the short-circuit current limit specified in output is disabled, which is reflected in the DO_EXT_CONFIG
Table 11. In the event of a short circuit, the DO_INT_SC bit is set in register or the DO_INT_CONFIG register for the external digital
the ALERT_STATUS register, which in turn asserts the ALERT pin. output or the internal digital output, respectively.
There is programmability around how the short-circuit behavior Figure 51 illustrates the operation of the two programmable timeout
operates. The two configurable short-circuit timeout times are T1 times along with the short-circuit current limits.
and T2.
To reenable the digital output circuit after a timeout event:
To support charging of large current loads on initial power-on of
the digital output load, a higher short-circuit current limit can be ► Set the DO_DATA_INT or DO_DATA_EXT bit to 0
enabled for a programmable amount of time, T1. T1 starts counting
analog.com Rev. 0 | 53 of 113
Data Sheet AD74115H
THEORY OF OPERATION
► Choose a mode in the DO_INT_MODE or DO_EXT_MODE bits 0. Consider the additional enabled diagnostics when calculating
in the relevant configuration register to power on the digital conversion times.
output circuit
When using internal FETs, the diagnostic (Diagnostic 2 for the sink-
► Set the DO_DATA_INT or DO_DATA_EXT bit back to 1 to enable
ing current, and Diagnostic 3 for the sourcing current) measures
the FET. the current being sourced or sinked by the digital output circuit.
Use the equations in Table 29 to determine the current from the
returned ADC code, which is read in the ADC_DIAG_RESULTx
register. Note that, if Diagnostic 3 is required to measure sourcing
current in the internal digital output circuit, Diagnostic 2 must also
be enabled in the ADC_CONV_CTRL register to guarantee meas-
urement accuracy. Any diagnostic setting of choice can be selected
on Diagnostic 3. Consider the additional enabled diagnostics when
calculating conversion times.
HART
The AD74115H has an integrated HART modem. The following
sections describe the HART features.
Figure 51. Digital Output Programmable Short-Circuit Control
HART Modem
Current Sensing Diagnostic The AD74115H includes an integrated HART modem that can
A digital output, current sense diagnostic is available to monitor the transmit and receive signals to and from the I/OP screw terminal.
current in the digital output circuit. The HART modem can be used for HART communications in
current output and current input modes of operation.
Select the current sense diagnostics by programming the DI-
AG_ASSIGN register. Figure 52 shows the interface, transmit, and receive paths for the
HART modem on the AD74115H. HART transmit signals are cou-
When using external FETs, the diagnostic (Diagnostic 0 for the pled onto the I/OP screw terminal by injecting the signal from the
sinking current and Diagnostic 1 for the sourcing current) measures HART_TX_OUT pin to the HART_TX_IN pin. An external capacitor
the voltage dropped across the external RSET resistor. Consider ensures that there is no dc contribution from the HART modem to
the resistance of the selected RSET when calculating the current output signal.
being sourced or sinked by the digital output circuit. Note that if
Diagnostic 1 is required to measure sourcing current in the external HART receive signals are coupled directly from the I/OP screw
digital output circuit, and Diagnostic 0 must also be enabled in the terminal to the HART modem via the HART_RX pin. Refer to Table
ADC_CONV_CTRL register to guarantee measurement accuracy. 36 for the recommended external components required for HART
Any diagnostic setting of choice can be selected on Diagnostic operation.
Communicating with the HART Modem ► Enable the HART slew option in the OUTPUT_CONFIG register
if the current output with HART is selected.
Communication with the modem is via the SPI. An internal SPI to
► Power up the HART modem in the HART_CONFIG register. Oth-
universal asynchronous receiver transmitter (UART) implementation
er HART configuration options are available in the HART_CON-
handles the transactions on the SPI and converts these transac-
FIG register and can be configured as required. Note that a
tions to UART commands to and from the modem. The necessary
duplex mode of operation is available to allow for loopback
status bits are provided via the SPI to communicate with an existing
testing of the modem to confirm that data can be transferred and
software stack.
received by the AD74115H.
The SPI manages the HART transactions and the software configu- ► Load the HART transmit FIFO with data required for transmission
rable input and output transactions. via the HART_TX register.
It is also possible to configure the GPIO_x pins to either monitor ► Ensure that the HART alerts are cleared in the
or control the HART modem UART interface by programming the HART_ALERT_STATUS register.
GPIO_SELECT bits in the GPIO_CONFIGx registers. ► Set the RTS bit in the HART_MCR register to start HART
transmissions.
Transmit and Receive FIFOs ► Monitor the HART_ALERT_STATUS register for status alerts on
The AD74115H is equipped with a HART transmit first in, first the progress of the HART communication.
output (FIFO) and HART receive FIFO. Up to 32 bytes of data can ► Read the receive FIFO by using the HART_RX register. Note
be stored in each of the transmit and receive FIFOs. that, the receive bytes of data are stored in the receive FIFO.
The transmit FIFO is loaded using the HART_TX register. Data GETTING STARTED
can be read from the receive FIFO via the HART_RX register. Power up the AD74115H as recommended in Powering on the
An alert is issued if the number of bytes loaded to the transmit AD74115H section. After initial power-up, the ALERT pin is pulled
FIFO falls below the programmable threshold value. Similarly, an low as a result of various bits, such as the RESET_OCCURRED
alert is issued if the number of bytes loaded to the receive FIFO bit being set in the ALERT_STATUS register. It is recommended
goes above the programmable threshold value. These receive and to clear the ALERT_STATUS register before continuing to use
transmit threshold values can be programmed via the TFTRIG and the AD74115H. Write 1 to clear each bit in the ALERT_STATUS
RFTRIG bits in the HART_FCR register. register.
The number of bytes currently stored in the transmit and receive
FIFOs is recorded in the HART_TFC and HART_RFC registers, Using Channel Functions
respectively.
The channel function is selected using the CH_FUNC_SETUP reg-
HART Alerts ister. Once a channel function is selected, the contents of a number
of registers are updated with predefined values, which allows the
The HART_ALERT_STATUS register contains all the alert bits user to configure the device with a minimal set of commands. The
associated with HART communications. If any bit is asserted in the updated settings include configuration of the channel conversion on
HART_ALERT_STATUS register, the HART_ALERT bit is asserted the ADC, Conversion 1. Table 22 outlines the default settings of
in the ALERT_STATUS register, which allows for an interrupt to be the bits for any given channel function. In addition to the default
generated on the ALERT pin. The HART alert bits can be masked settings described in Table 22, these bit fields are set to the
via the HART_ALERT_MASK register. If an alert bit is masked, it following values, irrespective of the CH_FUNC_SETUP selection:
does not generate an interrupt on the ALERT pin when asserted,
but the alert is still seen in the HART_ALERT_STATUS register. ► RTD_MODE_SEL in the RTD3W4W_CONFIG register is set to 0
(selects 3-wire RTD)
Configuring the AD74115H for HART ► RTD_CURRENT in the RTD3W4W_CONFIG register is set to 11
Communications binary (selects 1 mA)
To initiate HART communications with the AD74115H, take the ► DIN_SINK in the DIN_CONFIG1 register is set to 0 (ISINK off)
following steps: ► DIN_THRESH_MODE in the DIN_CONFIG2 register is set to 0
(threshold relative to AVDD)
► Configure the channel in the appropriate function (current output
with HART; current input, loop powered with HART; or current After configuring the channel function, users can configure the
input externally powered with HART). DAC_CODE registers, as required.
► Wait 200 μs before proceeding with another step.
Switching Channel Functions Each conversion has an individual conversion rate and voltage
range control that can be configured in the ADC_CONFIG register.
Take care when switching from one channel function to another.
All functions must be selected for a minimum of 200 μs before The ADC also provides diagnostic information on user-selectable
changing to another function. inputs such as supplies, internal die temperature, reference, and
regulators. See the Diagnostics section for more information on the
The DAC_CODE register is not reset by changing channel func- diagnostics measurements.
tions. Before changing channel functions, it is recommended to
set the DAC code to 0x0000 via the DAC_CODE register. Set After the measurements are configured in the ADC_CONFIG
the channel function to high impedance via the CH_FUNC_SETUP register, enable the relevant ADC measurements via the
register before transitioning to the new channel function. ADC_CONV_CTRL register.
For ±12 V voltage output, the DAC_CODE can be updated to Select either single conversion or continuous conversion mode
0x2000 before the voltage output is enabled to ensure that the by setting the appropriate value to the CONV_SEQ bits in the
output stage powers up to 0 V. Refer to the Voltage Output section. ADC_CONV_CTRL register.
After the new channel function is configured, it is recommended to In single conversion mode, the ADC sequencer starts conversions
wait 200 μs before updating the DAC code. on Conversion 1 and Conversion 2 followed by the enabled diag-
nostics. After each enabled input is converted once, the ADC enters
ADC FUNCTIONALITY idle mode, and conversions are stopped.
The AD74115H provides a single, 16-bit Σ-Δ ADC that can be In continuous conversion mode, the ADC channel sequencer con-
sequenced to measure up to two channel measurements and up to tinuously converts the enabled channel conversions and each ena-
four diagnostics measurements for a single conversion sequence or bled diagnostic until a command is written to stop the conversions.
for continuous conversions. The two channel measurements allow Set the stop command by setting the CONV_SEQ bits in the
for various voltage and current monitoring options on the I/OP ADC_CONV_CTRL register to idle mode or power-down mode. The
screw terminal and the auxiliary high voltage SENSE_EXT1 and command stops conversions at the end of the current sequence.
SENSE_EXT2 pins.
If the measurement configuration requires a change, continuous
Conversion 1 is targeted at supporting the measurements required conversions must be stopped before making the changes. Restart
for each of the AD74115H use cases. Table 23 shows the measure- the continuous conversions after making the appropriate changes.
ments available for Conversion 1. When any mode of operation
is selected in the CH_FUNC_SETUP register, Conversion 1 is After a sequence is complete, all data results are transferred
configured to a default measurement. These default measurements to the relevant ADC_RESULT1, ADC_RESULT2, and ADC_DI-
are described in the Using Channel Functions section. AG_RESULTn registers and the ADC_RDY pin is asserted.
Conversion 2 can be used for additional diagnostics measurements
on the channel or to monitor other external nodes. Table 24 shows
the measurements available for Conversion 2.
Table 23. Selection Options for ADC Conversion 1
CONV1_MUX Settings in the
ADC_CONFIG Register Measurement Selection Description
00 SENSELF to AGND_SENSE Voltage measurement across the I/OP and I/ON screw terminals
01 SENSEHF to SENSELF Voltage measurement across the RSENSE resistor
10 SENSE_EXT2 to SENSE_EXT1 Voltage measurement across SENSE_EXT2 and SENSE_EXT1 for 4-wire RTD measurement
11 SENSELF to SENSE_EXT1 Voltage measurement across SENSE_EXT1 and SENSELF for 3-wire RTD measurement
Saving Power When Using the ADC ► The initial pipeline delay before the first conversion.
► The conversion time for each ADC conversion.
Each of the high voltage sense pins available for measure-
ment by the ADC (SENSEHF, SENSELF, SENSE_EXT1, and Figure 53 shows the timing breakdown of a single conversion
SENSE_EXT2) has a high voltage buffer that is powered up by example. In this example, the ADC and high voltage buffers are in
default. The typical current drawn from each of these buffers is a power-down state before a single conversion on the channel is
specified in Table 14. enabled, and continuous conversions are initiated with a 4.8 kSPS
If any of the sense pins are not required for measurement by conversion rate.
the ADC, the high voltage buffer associated with that pin can The time to the first complete conversion (the SYNC pin falling
be put in standby mode to save total power consumption by the edge to the ADC_RDY pin falling edge) is 384.32 µs and is calcu-
AD74115H. Configure the AD74115H into the desired channel func- lated by adding the SPI transfer time, the ADC and high voltage
tion and put any of the high voltage sense pin buffers in standby. buffer power-up time, the pipeline delay time, and the conversion
Buffers are put into standby by setting the appropriate bit in the rate on the channel at 4.8 kSPS (208.33 µs). The time between
PWR_OPTIM_CONFIG register. Wait for the appropriate power-up conversions (the ADC_RDY pin falling edge to the ADC_RDY pin
time, specified in Table 14, when taking the buffers out of standby falling edge) is 208.33 μs.
mode.
For multiple conversions, consider the following components when
For optimal performance, power up the buffers before starting the calculating the overall sequence time:
conversion sequence.
► The time taken for the SPI transaction to start the conversions.
Do not update the PWR_OPTIM_CONFIG settings while an ADC ► The time required to power up the ADC and high voltage buffers,
conversion sequence is taking place. if previously powered down.
► An initial pipeline delay before the first conversion.
ADC Conversion Rates
► The conversion time required for each ADC conversion.
The available ADC conversion rates on the AD74115H are 10 SPS, ► The channel switch time for each time the selected ADC channel
20 SPS, 1.2 kSPS, 4.8 kSPS, and 9.6 kSPS. In addition, 50 Hz and is switched.
60 Hz rejection is provided on the 10 SPS and 20 SPS conversion
rates. Figure 54 shows an example of the timing breakdown for a mul-
tichannel conversion. In this example, Conversion 1, Conversion
Configure each of the channel conversion rates via the ADC_CON- 2, Diagnostic 1, and Diagnostic 2 are all enabled. Continuous
FIG register. The conversion rate of the diagnostics inputs is set conversions are initiated with a 20 SPS conversion rate. In this
via the ADC_CONV_CTRL register. One conversion rate selection example, the ADC is in idle mode, and the high voltage buffers are
applies to all diagnostic inputs. powered up.
The time it takes for a sequence of conversions to complete is The time it takes for the first complete conversion (SYNC falling
dependent on several factors, such as the number of selected edge to ADC_RDY falling edge), is 200.149 ms and is calculated
inputs, the selected conversion rates, and whether single or contin- by adding the SPI transfer time, the pipeline delay time, and the
uous mode conversions are enabled. Conversions are clocked by conversion time on Conversion 1 at 20 SPS, followed by adding
an on-chip oscillator. Table 27 outlines the various components the channel switch time and conversion time for the remaining three
required to estimate a complete conversion time for any given conversions.
sequence.
The time between all subsequent conversion sequences (the
For single conversions, consider the following time components ADC_RDY pin falling edge to the ADC_RDY pin falling edge) is
when calculating the overall sequence time: 200.0976 ms and is calculated by adding the channel switch time
► The time taken for the SPI transaction to start the conversions. with the conversion time for the four selected ADC inputs.
► The time required to power up the ADC and high voltage buffers,
if previously powered down.
Table 27. Conversion Times Components
ADC and/or Buffer SPI Transfer Time (μs), Single ADC Channel Switch Time, Multiple
Conversion Rate Power-Up Time (μs) 42 ns SCLK Start-Up Pipeline Delay (µs) Conversion Time Enabled Conversions (μs)
9.6 kSPS 100 1.99 55 104.17 μs 24.4
4.8 kSPS 100 1.99 81 208.33 μs 24.4
1.2 kSPS 100 1.99 81 833.33 μs 24.4
20 SPS 100 1.99 87 50 ms 33.6
The ADC_RDY pin deasserts in any of the following scenarios: See Figure 55 and Figure 56 for timing diagrams of the ADC_RDY
pin in single and continuous conversion modes.
ADC Noise typical and are generated with a differential input voltage of 0 V
when the ADC is continuously converting on a single channel.
Table 28 shows the peak-to-peak noise of the AD74115H for each
of the output data rates and voltage ranges. These numbers are
Table 28. Peak-to-Peak Noise in LSBs per Voltage Range and Output Data Rate (Inputs Shorted)
+0.625 V Range ±104 mV Range
Output Data Rate +12 V Range (LSBs) ±12 V Range (LSBs) +2.5 V Range (LSBs) ±2.5 V Range (LSBs) (LSBs) (LSBs)
10 SPS 0.1 0.07 0.16 0.08 0.3 0.7
20 SPS 0.2 0.1 0.2 0.1 0.5 1.0
1.2 kSPS 1.1 0.5 1.4 0.7 3.0 8.9
4.8 kSPS 2.7 1.4 3.6 1.8 8.5 18.1
9.6 kSPS 6.0 3.0 7.2 3.6 17.9 33.3
Diagnostics ing three conversion rates are available for selection within the
ADC_CONV_CTRL register: 9.6 kSPS, 4.8 kSPS, and 20 SPS. In
The AD74115H has a diagnostic function that allows the ADC to addition, 50 Hz and 60 Hz rejection is provided on the 20 SPS
measure various on-chip voltages. These diagnostic voltages are conversion rate.
scaled to be measurable within the ADC range.
Table 29 shows a full list of available diagnostics, and the equations
The diagnostics inputs are independent of the two available chan- required to calculate the diagnostic value.
nel measurements of the AD74115H. The DIAG_ASSIGN register
assigns the voltage measurements to each diagnostic input. Select In the equations listed in Table 29, DIAG_CODE is the ADC result
a diagnostic input to be measured by the ADC by enabling that code read from the ADC_DIAG_RESULTn registers, and the volt-
input in the ADC_CONV_CTRL register. Users can also select age range is the ADC measurement range and is 2.5 V.
the conversion rate via the ADC_CONV_CTRL register. The follow-
Table 29. User-Selectable Diagnostics1
Diagnostic Formula to Interpret ADC Result Measurement Range
Temperature Sensor (Internal Die See Table 17 for recommended maximum junction
Temperature = DIAG_CODE
8.95
− 2034
− 40
Temperature Measurement)/°C temperature
Voltage on AVDD Pin (VAVDD) VAVDD = DIAG_CODE
65, 536 × 50 0 V to 50 V
Voltage Across RSET in External Digital Output 0 V to 0.3125 V (equivalent to 2.08 A when using
VRSET = DIAG_CODE
65, 536 × 0.3125
Sourcing Mode recommended 0.15 Ω external resistor)
Voltage Across RSET in External Digital Output 0 V to 2.5 V (equivalent to 16 A when using
VRSET = DIAG_CODE
65, 536 × 2.5
Sinking Mode recommended 0.15 Ω external resistor)
Current Flowing Through RSET in Internal DIAG_CODE × 0.3125 0 mA to 226 mA
IRSET = 65, 536
Digital Output Sourcing Mode 1.38
Current Flowing Through RSET in Internal DIAG_CODE × 2.5 0 mA to 1.8 A
IRSET = 65, 536
Digital Output Sinking Mode 1.38
DAC FUNCTIONALITY The code loaded to the DAC from either of the two sources is also
loaded to the DAC_ACTIVE register. The DAC_ACTIVE register
The AD74115H contains a 14-bit DAC. The DAC core is a 14-bit contains the current code loaded to the DAC, irrespective of the
string DAC. The architecture structure consists of a string of resis- code source.
tors, each with a value of R. The digital input code that is loaded
to the DAC_CODE register determines which node on the string DAC Transfer Function
the voltage is tapped off from and fed into the output amplifier. This
architecture is inherently monotonic and linear. Table 30 shows the input code to ideal analog output relationship
for each of the available output ranges.
There are two sources for the code loaded to the DAC. The typical
option is to load a code to the DAC from the DAC_CODE register.
The second option is to enable slewing to control the rate at which
the DAC code is loaded to the DAC.
Table 30. Ideal DAC Input Code to Output Relationship
DAC Code Analog Output
MSBs LSBs ±12 V 0 V to 12 V 0 mA to 25 mA
0000 0000 0000 0000 −12 V 0V 0 mA
0000 0000 0000 0001 24 × (1/16,384) − 12 12 × (1/16,384) 25 mA × (1/16,384)
0010 0000 0000 0000 0V 6V 12.5 mA
0011 1111 1111 1110 24 × (16,382/16,384) − 12 12 V × (16,382/16,384) 25 mA × (16,382/16,384)
0011 1111 1111 1111 24 × (16,383/16,384) − 12 12 V × (16,383/16,384) 25 mA × (16,383/16,384)
Digital Linear Slew Rate Control rate at which the codes are updated. Table 31 shows the typical
programmable slew rates for a zero-scale to full-scale (or full-scale
The digital linear slew rate control feature of the AD74115H controls to zero-scale) DAC update that is available on the AD74115H.
the rate at which the output transitions to the new value. This slew
rate control feature is available for both the current and voltage The DAC_ACTIVE register can monitor the progress of slewing to
outputs. a target DAC code. This register contains the code that is currently
loaded to the DAC.
When the slew rate control feature is disabled, the output value
transitions at a rate limited by the output drive circuitry and the If the digital slewing is disabled before the end code in the
attached load. DAC_CODE register is reached, the value remains at the DAC_AC-
TIVE value, and does not ramp to the end code.
To reduce the slew rate, enable the digital slew rate control feature
via the OUTPUT_CONFIG register. HART Compliant Slew
After the digital slew rate control feature is enabled, the output An enhanced slew option is available to allow compatibility with the
steps digitally at a rate defined by the user in the OUTPUT_CON- HART analog rate of change requirements. Set the SLEW_EN bit in
FIG register. The SLEW_LIN_STEP bits dictate the number of the OUTPUT_CONFIG register to enable this slew option.
codes per increment, and the SLEW_LIN_RATE bits dictate the
Table 31. Programmable Slew Times for a Zero-Scale to Full-Scale Code Update
Step Size (% of Full-Scale DAC Voltage), Programmable via SLEW_LIN_STEP Bits1
Update Slew Rate, Programmable via SLEW_LIN_RATE Bits (kHz) 0.8% 1.5% 6.1% 22.2%
4 31.3 ms 16.7 ms 4.1 ms 1.1 ms
64 2.0 ms 1.0 ms 256 μs 70.4 μs
150 833 μs 444 μs 109 μs 30.0 μs
240 521 μs 277 μs 68.3 μs 18.8 μs
1 These are theoretical values. The final slew rate is limited by the CLOAD value.
Driving Inductive Loads The ALERT_MASK register prevents error conditions from activat-
ing the ALERT pin.
It is recommended to use the digital slew rate control when driving
inductive loads greater than approximately 4 mH. Controlling the Channel Faults
output slew rate minimizes ringing when stepping the output current
by minimizing the current rate of change (di/dt). See the IOUT typical The AD74115H is equipped with multiple open-circuit and short-cir-
performance of the settling time with an inductive load with and cuit faults in the various functions as described in the Device
without the slew rate enabled in the Figure 11. Functions section. Manage faults as these faults appear and reset
the channel, if necessary, to avoid overheating the device.
RESET FUNCTION
After the AD74115H is reset, all registers are reset to the default Power Supply Monitors
state, and the calibration memory is refreshed. The device is config- The AD74115H includes six power supply monitors to detect a
ured in high impedance mode. A reset can be initiated in several supply failure. If any of the supplies fall to less than the defined
ways. threshold detailed in Table 14, the corresponding bit is set in the
The hardware reset is initiated by pulsing the RESET pin low. The ALERT_STATUS register.
RESET pulse width must comply with the specifications in Table 15.
Thermal Alert and Thermal Reset
A software reset is initiated by writing the 0x15FA code (Software
Reset Key 1) followed by the 0xAF51 code (Software Reset Key 2) If the AD74115H die temperature reaches the alert temperature
to the CMD_KEY register. described in Table 14, a high temperature error bit (TEMP_ALERT)
is set in the ALERT_STATUS register to alert the user of the
A reset can also be initiated via the thermal reset function, which is increasing die temperature.
described in the Thermal Alert and Thermal Reset section.
The device can also be configured to reset at higher die temper-
If the VDLDO1V8 or the VDVCC drop below the specified power supply atures. To reset the device at higher temperatures, enable the
monitors threshold highlighted in Table 14 the internal power-on thermal reset function by setting the EN_THERM_RST bit in the
reset function resets the AD74115H. The device does not come out THERM_RST register. After this bit is set, the device goes through
of reset until the VDLDO1V8 and the VDVCC rise above these voltage a full reset after the die temperature reaches the reset temperature
levels. described in Table 14.
After a reset cycle completes, the RESET_OCCURRED bit is set
in the ALERT_STATUS register. If an SPI transfer is attempted Burnout Currents
before the reset cycle is complete (see Table 14 for typical reset
time), the CAL_MEM_ERR bit in the SUPPLY_ALERT_STATUS Burnout currents are used to verify the integrity of an attached
register is also set to indicate that the calibration memory is not sensor and to ensure that it has not gone open circuit before taking
fully refreshed. After the reset time elapses, clear these bits in the a measurement from it. The AD74115H can be enabled to provide
ALERT_STATUS register before continuing to use the device. a user programmable, current source that can be programmed
to a fixed value between 50 nA and 10 μA. Burnout currents
FAULTS AND ALERTS are available on the VIOUT (to monitor the I/OP screw terminal),
SENSE_EXT1, and SENSE_EXT2 pins and can be programmed to
The AD74115H is equipped with several fault monitors to detect an source or sink current.
error condition.
The burnout current sources are disabled on power up. Program
If an alert or fault condition occurs, the ALERT pin asserts. To the burnout current using the bits in the I_BURNOUT_CONFIG
determine the source of the alert condition, read the ALERT_ register. The full list of available current settings can be found in
STATUS register. This register contains a latched bit for each alert Table 14.
condition.
The current source can be enabled at all times or alternatively
After the error condition is removed, clear the activated flag by writ- enabled when needed for diagnostic purposes. When a burnout
ing 1 to the location of the corresponding bits in the ALERT_STA- current source is enabled, the selected current is switched onto the
TUS register (write 0xFFFF to the ALERT_STATUS register to selected pin, and it flows in the external load.
clear all alert bits). Alerts asserted in SUPPLY_ALERT_STATUS or
HART_ALERT_STATUS must be cleared before the ALERT_STA- FET LEAKAGE COMPENSATION
TUS register.
A software configurable input and output solution can include a
The LIVE_STATUS register is a live representation of the error precision analog input and output capability along with a high
conditions. The bits in this register are not latched and clear current, digital output capability on a single screw terminal. In this
automatically when the error condition is no longer present. case, the external FET used in the digital output function may
contribute off-leakage to the screw terminal when not in use. This For sourcing the digital output, connect the DO_SRC_INT pin to
leakage can affect the accuracy of the analog functions, especially the drain of the FET as shown in Figure 57. Similarly, for sinking
to RTD measurements. the digital output, connect the DO_SNK_INT pin to the drain of the
sinking FET as shown in Figure 58.
The AD74115H has a FET leakage compensation feature that
provides an alternative path to the FET leakage to prevent it from The FET leakage compensation feature can be used if the specified
flowing in the I/OP screw terminal. leakage of the chosen external FET is expected to contribute error
to the precision analog measurements like the current input or
To enable this feature, configure the FET_LKG_COMP register. Set 3-wire and 4-wire RTD measurements. This feature is not recom-
the FET_SRC_LKG_COMP_EN bit for sourcing digital output and mended for use in 2-wire RTD mode.
set the FET_SNK_LKG_COMP_EN bit for sinking digital output.
Figure 57. Configuration for Digital Output Sourcing with FET Leakage Compensation
Figure 58. Configuration for Digital Output Sinking with FET Leakage Compensation
Table 34. SDO Contents for a Read Operation When the SPI_RD_RET_INFO Bit = 0
MSB LSB
D31 [D30:D24] [D23:D8] [D7:D0]
1 READBACK_ADDR[6:0] Read data CRC
Table 35. SDO Contents for a Read Operation When the SPI_RD_RET_INFO Bit = 1
MSB LSB
D31 D30 D29 D28 D27 D26 D25 D24 [D23:D8] [D7:D0]
1 0 ALERT ADC_DATA_RDY HART_ALERT 0 0 DIN_COMP_OUT Read data CRC
SPI CRC Clear the SPI_ERR bit in the ALERT_STATUS register by setting
it to 1. Once the alert bit clears, the ALERT pin is deasserted
To ensure that data is received correctly in noisy environments, the (assuming that there are no other active alerts). The SPI CRC error
AD74115H has a CRC implemented in the SPI. This CRC is based can be masked by writing to the relevant bit in the ALERT_MASK
on an 8-bit CRC. The device controlling the AD74115H generates register.
an 8-bit frame check sequence using the following polynomial:
C(x) = x8 + x2 + x1 + 1 SPI SCLK Count Feature
This frame check sequence is added to the end of the data-word, An SCLK count feature is built into the SPI diagnostics. Only SPI
and the 32-bit data-word is sent to the AD74115H before taking the frames with exactly 32 SCLK falling edges are accepted by the
SYNC pin high. SPI as a valid write. In burst read mode, the number of SCLK
rising edges must equal 32 + (n × 24), where n is the number of
A frame 32 bits wide containing the 24 data bits and 8 CRC bits transactions.
must be supplied by the user. If the CRC check is valid, the data is
written to the selected register. If the CRC check fails, the data is SPI frames of lengths other than the valid cases previously listed
ignored, the SPI_ERR status bit in the ALERT_STATUS register is are ignored, and the SPI_ERR bit asserts in the ALERT_STATUS
asserted, and the ALERT pin goes low. register. Mask the SPI_ERR bit via the ALERT_MASK register.
An 8-bit CRC is also provided with the data read during a register
readback that can be used by the host microcontroller to verify that
there are no SPI errors during the read transaction.
POWER AND ISOLATION The ADP1034 provides digital isolation to the AD74115H SPI pins
(SCLK, SYNC, SDO, and SDI). Isolation is available for two other
The AD74115H is designed to operate with a companion power and digital output pins and one digital input pin. The block diagram in
isolation chip. The ADP1034 provides programmable power control Figure 63 shows that the RESET, ADC_RDY, and ALERT pins are
(PPC) to the analog supply (AVDD) so that VAVDD can be software isolated using the ADP1034.
controlled. The ADP1034 also provides fixed power supply voltages
to the following AD74115H supply pins: AVSS, AVCC, and DVCC. Refer to the ADP1034 data sheet for more information.
The ADP1034 is controlled by the AD74115H via the PPC_CTRL One-Wire Serial Interface
pin using an OWSI. The host controller issues commands to adjust
the AVDD supply voltage to the PPC_TX register. In turn, the Programmable power control is implemented via an OWSI between
AD74115H passes the required VAVDD changes to the ADP1034 the AD74115H and the ADP1034.
using the OWSI. Once the ADP1034 receives a command to modify
VAVDD, it updates the VAVDD accordingly. The AD74115H acts as the OWSI main, using the PPC_CTRL pin.
An OWSI transaction requires a number of elements, as shown in
Choose the PPC_TX register code based on the following equation: Figure 62. OWSI timing specifications are listed in Table 16. The
VÀVDD
OWSI frame is broken into bit periods. Each start event, data bit,
PPC_CODE = 252 × VAVDD_MAX −1 and acknowledge (ACK) bit occurs within a bit period, and each
timing specification is defined from the start of that bit period.
where:
PPC_CODE is the code that must be programmed to the PPC_TX A start sequence is defined by two successive rising edge pulses.
register for the desired VAVDD value. Once the start command is transmitted, 16 data bits follow to make
VAVDD is the desired AVDD supply voltage. up the address, data, and CRC bits. Finally, an acknowledge se-
VAVDD_MAXis the maximum voltage that can be generated by quence is required from the OWSI subordinate. The acknowledge is
the ADP1034 with the selected feedback resistors. Refer to the comprised of two bits: an ACK bit and a parity bit.
ADP1034 data sheet for more information. The AD74115H pulls the OWSI bus high at the start of the ACK and
The AVDD supply from the ADP1034 can be dynamically changed parity bit periods. The OWSI bus is sampled by the AD74115H for
as the load requirement and selected use case changes. Any a fixed time during the ACK and parity bits during which the OWSI
changes must be done in a coordinated manner. If the voltage on subordinate can drive the bus low. Refer to Figure 3 for a detailed
the I/OP screw terminal is expected to increase due to a change view of the OWSI timing and to Table 16 for the appropriate timing
in conditions, VAVDD must be adjusted first. If the voltage on the specifications.
I/OP screw terminal is expected to decrease due to the change During a successful transaction, the OWSI subordinate remains
in conditions, VAVDD must be adjusted after the change in load, high during the ACK bit and drives the bus low during the parity bit.
current, or selected use case.
If the transaction is not successful, the OWSI subordinate drives the
The diagnostics function can confirm that the voltage is set on bus low during the ACK bit and remains high during the parity bit.
the AVDD pin. Select AVDD in one of the available diagnostics in
the DIAG_ASSIGN register. Enable an ADC conversion using the
ADC_CONFIG register and read the diagnostics result using the
relevant ADC_DIAG_RESULTx register.
EXTERNAL COMPONENTS
Table 36 lists the external components that are recommended to
operate the AD74115H.
Table 36. External Components
Value
Component Min Typical Max Voltage Rating (V) Suggested Component1 Notes/Comments
Decoupling
AVDD Decoupling 10 μF 50 Generic
0.1 μF 50 Generic
AVSS Decoupling 10 μF 502 Generic
100 nF 501 Generic
AVCC Decoupling 10 μF 16 Generic
100 nF Generic
DVCC Decoupling 10 μF 16 Generic
0.1 μF 16 Generic
DO_VDD 10 μF 100 Generic
ALDO1V8 Decoupling 1 μF 2.2 μF 6.3 GRM21BR70J225MA01
DLDO1V8 Decoupling 1 μF 2.2 μF 6.3 GRM21BR70J225MA01
REFOUT Decoupling 22.0 nF 50 nF 6.3 Generic
Charge Pump When using the charge pump, connect
CP_OUT to AVSS.
Fly Capacitor 330 nF 10 GRM188R71A334KA61 Connect this capacitor between the
CPUMP_P and CPUMP_N pins.
Analog Input and Output
CCOMP Pin Compensation 220 pF 100 Generic This pin is recommended for a total
CLOAD > 14 nF and tied between
the CCOMP pin and the I/OP screw
terminal.
SENSEHF Filter Capacitor3 4.7 nF 100 Generic
SENSEHF Filter Resistor3 2.7 kΩ Generic Generic 1% accuracy.
SENSELF Filter Capacitor3 4.7 nF 100 Generic
SENSELF Filter Resistor3 2.7 kΩ Generic Generic 1% accuracy.
SENSEH Precision 2 kΩ Generic Generic The SENSEH resistor accuracy directly
affects RTD specifications.
SENSEL 2 kΩ Generic Generic 1% accuracy.
RSENSE 100 Ω Generic Generic RSENSE accuracy directly affects current
output, current input, and RTD
accuracy.
Screw Terminal
Load Capacitor 4.7 nF 100 Generic
36 V TVS 36 SMBJ36CA
HART See Figure 52 for implementation.
HART Coupling Capacitor 100 nF 6.3 Generic This capacitor is tied between
HART_TX_IN and HART_TX_OUT.
HART_TX_OUT Capacitor 22 nF 6.3 Generic This ceramic capacitor is tied between
HART_TX_OUT and ground.
HART_RX Band-Pass Filter 27 kΩ Generic Generic
1 nF 100 Generic
2.2 nF 100 Generic
BOARD DESIGN AND LAYOUT When grounding the AD74115H pins, it is recommended to connect
CONSIDERATIONS the AGND pins and DGND pins to a single ground plane. The I/ON
screw terminal must also be tied to this ground plane.
This section outlines the critical board design and layout considera-
tions for the AD74115H. Track the SENSEH, SENSEHF, SENSEL, and SENSELF pins di-
rectly to the pad of the RSENSE resistor.
To guarantee stability for the SENSEL pin, limit the capacitance to
ground between the SENSEL pin and the required 2 kΩ resistor to Track the DO_SRC_SNS and DO_SNK_SNS pins directly to the
<10 pF. pad of the external RSET resistors.
To guarantee stability for the SENSEH pin, limit the capacitance to The AGND_SENSE pin senses the voltage at the I/ON screw
ground between the SENSEH pin and the required 2 kΩ resistor to terminal and provides this voltage as an input to the ADC. It is not
<10 pF. recommended to directly connect the AGND_SENSE pin to ground.
Instead, users must route a single trace from the AGND_SENSE
To guarantee stability for the CCOMP pin, limit the capacitance pin to the I/ON screw terminal. This connection can be done by
to ground between the CCOMP pin and the CCOMP capacitor (if connecting the AGND_SENSE pin to the I/ON screw terminal on
required) to <10 pF. the AD74115H board.
For correct operation of the programmable power control interface,
limit the capacitance to ground on the PPC_CTRL pin to 30 pF.
To optimize thermal performance, design the AD74115H boards
with a minimum of four layers and with multiple thermal vias con-
necting the paddle to the bottom layer of the board. See the JEDEC
JESD-51 specifications for more details. Users are recommended
to thermally connect the exposed pad of the AD74115H to the
thermal vias.
Table 37 summarizes the register map for the AD74115H with information on how to read and write to and from the registers. R indicates read
only access, R/W indicates read and write access, R/W1C indicates read, write, or clear, and W indicates write only access.
Table 38 summarizes the HART register map with information on how to read and write to and from the registers. R indicates read only access,
R/W indicates read and write access, and W indicates write only access.
NOP Register
Address: 0x00, Reset: 0x0000, Name: NOP
Read only register. Writing to this register results in a no operation (NOP) command.
This register enables compensation for leakage in the external digital output FETs. This feature can be enabled during precision analog
input and output measurements. Only use this register when the DO_INT_MODE is programmed to digital output internal disable, and the
DO_EXT_MODE is programmed to digital output external disable.
Command Register
Address: 0x78, Reset: 0x0000, Name: CMD_KEY
This register is used to issue specific commands to the device.
Silicon ID 0 Register
Address: 0x7C, Reset: 0x0000, Name: SILICON_ID0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Silicon ID 1 Register
Address: 0x7D, Reset: 0x0000, Name: SILICON_ID1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Silicon ID 2 Register
Address: 0x7E, Reset: 0x0000, Name: SILICON_ID2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Silicon ID 3 Register
Address: 0x7F, Reset: 0x0000, Name: SILICON_ID3
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
When the address of this register is written to the READ_SELECT register, the clock to the HART UART logic is automatically enabled.
Therefore, when finished using the UART, write any address other than HART_RX to the READ_SELECT register to disable the clock to the
UART to save power.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EVALUATION BOARDS
Model1 Description
EVAL-AD74115H-ARDZ Evaluation Board
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