DB Tef07f32x32hd18 PHRM C180518 120a

TEF07F32X32HD18_PHRM_C180518
TSMC Electrical Fuse Datasheet Version 120A

09/14/2018
TEF07F32X32HD18_PHRM_C180518 – 1024 bits High Density Electrical Fuse

IP Naming Rule
TEF07F 32X32 HD18 POSTFIX
N07F Array size High Density “P” : power-switch
-Word depth:32 1.8V program “H” : power-down
-I/O bus:X32 “R” : redundancy
“M” : margin read1
General Description Read Condition and Spec
■ VQPS: 0V or floating or 1.8V+/-10%
TEF07F32X32HD18_PHRM_C180518 macro
VDD: 0.75V+/-10%
is organized as 32-bit by 32 (1024 bits)
Temp: -40oC~125oC
one-time programmable electrical fuse array
■ Above read condition is subject to change and
with random access interface. Electrical fuse
will be finalized after silicon data is available.
is a type of non-volatile memory and is
■ Max accumulative read access time MUST be
fabricated in standard CMOS logic process. It
less than 20 seconds per each bit when
is widely used in chip ID, memory
CSB=L,LOAD=H,PGENB=H,STROBE=H
redundancy, security code, configuration
■ Max accumulative numbers of read MUST be
setting, and feature selection, etc.
less than 20 million reads per each bit when
EFuse is only guaranteed to operate at the CSB=L,LOAD=H,PGENB=H,STROBE=H
voltage and temperature conditions specified Features
within this document or permanent damage
■ For 7nm FinFET technology 0.75V with 1.8V
may occur. I/O process.
■ Embedded power-switch.
■ Embedded one test row and two test columns.
Technology
■ Embedded four redundancy bits.
The cell layout is a 1P5M structure using ■ Provide power-down and standby mode.
TSMC 7nm FinFET process. ■ Asynchronous signal interface.
■ Requiring standard-Vt GO1 (Core device)
transistors.
Program Condition
■ Also requiring GO2 (I/O device) transistors.
■ VQPS:1.8V+/-5%
■ “TEF07FESD_P_C180518” macro is provided
VDD: 0.75V+/-10% for ESD protection, which MUST be used
Temp: -40oC~125oC in-pair with this electrical fuse IP.
Program time: 5us+/-10% ■ TEF07FESD_P_C180518 is only for FE-kits
■ Above program condition is subject to usage only. For back-end kits, please refer
to TEF07FESD_P library.
change and will be finalized after silicon data
■ The GDS drawn dimension:
is available. X=210.9605 um, Y=155.1900 um
Area=32738.959995 um2
Effective bit cell size: 31.97 um2 (rounded to
two digits after decimal point)
© Copyright 2018. Taiwan Semiconductor Manufacturing Company, Ltd. All rights reserved. www.tsmc.com
TSMC reserves the right to change features or specifications at any time without notice.
1
Block Diagram
VDD VQPS
PD Power Switch PS
X-decoder
A3~A0 Electrical Fuse

Array
CSB
STROBE
PGENB Control Y-Decoder I/O- Sense Register of
RWL Decoder Amplifier RIR
RSB
TRCS
AT1~AT0
LOAD A4 A9~A5 MR Q31~Q0 RF3~RF0
© Copyright 2018 Taiwan Semiconductor Manufacturing Company, Ltd. All rights reserved. www.tsmc.com
2
Pin Definition
Pin Name Signal Type Description

CSB Input Chip select enable (active low)
STROBE Input High to turn ‘ON’ the array for read or program access
LOAD Input High to turn ‘ON’ sense amplifier and load data into latch
Q31~Q0 Output Data output
A9~A0 Input Address pins
PGENB Input Program enable (active low)
Read trip point setting: MR = L for normal read mode; MR = H for margin read1
MR Input
mode
RSB Input Redundancy enable/disable (active low)
RWL Input Redundancy information row select (active high)
TRCS Input Test row/column select enable (active high)
st
Test row/column setting: [AT1, AT0] = [0,0] for test row; [1,0] for 1 test column
AT1~AT0 Input nd
and [1,1] for 2 test column
RF3~RF0 Output High when redundancy bit is used
PS Input High to pass 1.8V program voltage to internal for program
PD Input Power down enable (active high)
VQPS Supply High voltage (1.8V) for fuse programming
VDD Supply Core supply voltage
VSS Supply Ground
3
Operation Mode Truth Table
Mode CSB STROBE LOAD PGENB PS PD MR RSB RWL TRCS VQPS
L H H H L L L L L L
A_READ mode 0V or floating or 1.8V+/-10%
L H H H L L L H X L
R _READ mode L H H H L L L L H L 0V or floating or 1.8V+/-10%
T_READ mode L H H H L L L X X H 0V or floating or 1.8V+/-10%
Margin A_READ1 L H H H L L H L L L
0V or floating or 1.8V+/-10%
mode L H H H L L H H X L
Margin R_READ1
L H H H L L H L H L 0V or floating or 1.8V+/-10%
mode
Margin T_READ1
L H H H L L H X X H 0V or floating or 1.8V+/-10%
mode
L H L L H L X L L L
A_PGM mode 1.8V+/-5%
L H L L H L X H X L
R _PGM mode L H L L H L X L H L 1.8V+/-5%
T_PGM mode L H L L H L X X X H 1.8V+/-5%
Standby mode H X X X L L X X X X 0V or floating or 1.8V+/-10%
Power-down mode H X X X L H X X X X 0V or floating or 1.8V+/-10%
Note
(1) Logic “H” is the 0.75V nominal supply voltage for TSMC 7nm FinFET technology, unless otherwise defined.
(2) Logic “L” is 0V, at ground.
(3) For device reliability concern, VQPS MUST NOT exceed 1.8V when PS=H, and the accumulative time
under VQPS= 1.8V, PS=H should be less than 0.2 second. (subject to change)
(4) Please always keep PS at “L” except program mode.
(5) Max accumulative read access time should be less than 20 seconds for each bit when CSB=L, LOAD=H,
PGENB=H, STROBE=H. (subject to change)
(6) Max accumulative numbers of read MUST be less than 20 million reads for each bit when CSB=L,
LOAD=H, PGENB=H, STROBE=H. (subject to change)
(7) PS=H, PD=H state is NOT allowed to prevent unintended program.
(8) Please keep VQPS=0V when input signals are in unknown states or VDD is floating to prevent mis-program.
(9) RSB signal (active low) is used to disable/enable redundancy feature (repair function). Suggest customers to
4
tie RSB to DC-low directly if select to enable redundancy feature and tie RSB to DC-high directly if select NOT
to enable redundancy feature in product design stage.
(10)If RSB is at “L” and enable redundancy function, please MUST enter the redundancy read mode (R_READ or
Margin R_READ1) and read the RIR data once prior to the array read mode (A_READ or Margin A_READ1)
after power-up even if repairing is not needed. Redundancy read requires two strobe cycles to read out the
complete repairing information. The data will be stored in registers and will remain there until power-down or
power-off. In subsequent array read, when read access the failure bit in the main array, the corresponding
output data will be corrected automatically.
Capacitance
Pin Symbol Min Max Unit

A9~A0 CADRESS - 41.992 fF
STROBE CSTROBE - 27.712 fF
LOAD CLOAD - 27.569 fF
CSB CCSB - 27.468 fF
RWL CRWL - 26.187 fF
TRCS CTRCS - 43.049 fF
AT1~AT0 CAT - 38.294 fF
RSB CRSB - 25.019 fF
PGENB CPGENB - 27.051 fF
MR CMR - 106.573 fF
PS CPS - 26.952 fF
PD CPD - 23.618 fF
5
Timing Parameters
Mode Item Description ffg0p825v1p980v125c ffgnp0p825v1p980v125c ffgnp0p825v1p980v0c Unit
TSUR_PD_CS PD to CSB setup time in read mode 596.016 596.396 607.446 ns

THR_PD_CS PD to CSB hold time in read mode 45.323 45.352 46.192 ns
TSUR_PS_CS PS to CSB setup time in read mode 115.79 115.864 118.01 ns
THR_PS_CS PS to CSB hold time in read mode 93.704 93.764 95.501 ns
PD to STROBE setup time in read
TSUR_PD 640.15 640.558 652.427 ns
mode
THR_PD PD to STROBE hold time in read mode 119.541 119.617 121.833 ns
PS to STROBE setup time in read
TSUR_PS 159.924 160.026 162.991 ns
mode
THR_PS PS to STROBE hold time in read mode 167.922 168.029 171.142 ns
RWL to STROBE setup time in read
TSUR_RWL 88.269 88.325 89.962 ns
mode
RWL to STROBE hold time in read
THR_RWL 88.18 88.236 89.871 ns
mode
RSB to STROBE setup time in read
TSUR_RSB 89.232 89.288 90.923 ns
mode
RSB to STROBE hold time in read
THR_RSB 88.858 88.914 90.549 ns
mode
CSB to STROBE setup time in read
TSUR_CS 44.134 44.162 44.981 ns
mode
CSB to STROBE hold time in read
Read THR_CS 74.218 74.265 75.641 ns
mode
Mode PGENB to STROBE setup time in read
TSUR_PG 88.269 88.325 89.962 ns
mode
&
PGENB to STROBE hold time in read
THR_PG 148.437 148.532 151.284 ns
Margin mode
Read strobe pulse width in Array Read
Read1 TRD 160 161 163.416 ns
Mode
Mode Read strobe pulse width in Margin
TRD_M 399 400 407.249 ns
Read1 Mode
A4~A0 & AT1~AT0 to STROBE setup
TSUR_A 26.821 26.838 27.335 ns
time in read mode
A4~A0 & AT1~AT0 to STROBE hold
THR_A 32.289 32.31 32.909 ns
time in read mode
LOAD to STROBE setup time in read
TSUR_LD 88.269 88.325 89.962 ns
mode
LOAD to STROBE hold time in read
THR_LD 148.437 148.532 151.284 ns
mode
MR to STROBE setup time in read
TSUR_MR 52.961 52.995 53.977 ns
mode
THR_MR MR to STROBE hold time in read mode 89.059 89.116 90.767 ns
TRCS to STROBE setup time in read
TSUR_TRCS 46.95 46.98 47.851 ns
mode
TRCS to STROBE hold time in read
THR_TRCS 44.603 44.631 45.458 ns
mode
Q31~Q0 access time from STROBE
TSQ 155.074 155.173 158.048 ns
high in Array Read Mode
TSQ_M 393.786 394.037 401.338 ns
high in Margin Read1 Mode
TSQH Q31~Q0 hold time to the next STROBE 0 0 0 ns
6
TSUP_PD_PS PD to PS setup time in PGM mode 596.054 596.435 607.485 ns
THP_PD_PS PD to PS hold time in PGM mode 46.017 46.046 46.899 ns
TSUP_PS_CS PS to CSB setup time in PGM mode 115.79 115.864 118.01 ns
THP_PS_CS PS to CSB hold time in PGM mode 93.704 93.764 95.501 ns

PD to STROBE setup time in PGM
TSUP_PD 755.978 756.461 770.476 ns
mode
THP_PD PD to STROBE hold time in PGM mode 213.939 214.075 218.041 ns
PS to STROBE setup time in PGM
TSUP_PS 159.924 160.026 162.991 ns
mode
THP_PS PS to STROBE hold time in PGM mode 167.922 168.029 171.142 ns
RWL to STROBE setup time in PGM
TSUP_RWL 88.269 88.325 89.962 ns
mode
RWL to STROBE hold time in PGM
THP_RWL 88.172 88.228 89.857 ns
mode
RSB to STROBE setup time in PGM
TSUP_RSB 89.223 89.279 90.908 ns
mode
RSB to STROBE hold time in PGM
PGM THP_RSB 88.849 88.905 90.534 ns
mode
Mode TSUP_CS CSB to STROBE setup time in PGM
44.134 44.162 44.981 ns
mode
CSB to STROBE hold time in PGM
THP_CS 74.218 74.265 75.641 ns
mode
PGENB to STROBE setup time in PGM
TSUP_PG 88.269 88.325 89.962 ns
mode
PGENB to STROBE hold time in PGM
THP_PG 148.437 148.532 151.284 ns
mode
TPGM* Typical program strobe pulse width 5 5 5 us
TSUP_A 26.821 26.838 27.335 ns
time in PGM mode
THP_A 34.107 34.129 34.761 ns
time in PGM mode
TRCS to STROBE setup time in PGM
TSUP_TRCS 46.95 46.98 47.851 ns
mode
TRCS to STROBE hold time in PGM
THP_TRCS 44.603 44.631 45.458 ns
mode
LOAD to STROBE setup time in PGM
TSUP_LD 88.269 88.325 89.962 ns
mode
LOAD to STROBE hold time in PGM
THP_LD 148.437 148.532 151.284 ns
mode
Average read current during STROBE
ILOAD_VDD 30.429 30.121 26.916 mA
high – VDD domain
Average current during normal read
IACTIVE_VDD (STROBE:10Mhz / 50% duty) – VDD mA
Active 15.261 15.106 13.472
domain
current ILOAD_VQPS Average read current during STROBE
13.837 13.837 2.055 uA
high – VQPS domain
IACTIVE_VQPS (STROBE:10Mhz / 50% duty)– VQPS uA
13.835 13.835 2.055
domain
Standby ISTANDBY_VDD Standby current –VDD domain 87.916 81.47 3.919 uA

current
ISTANDBY_VQPS Standby current –VQPS domain 13.835 13.835 2.055 uA
Power IPD_VDD Power-down current –VDD domain 6.848 6.657 0.366 uA

down
current IPD_VQPS Power-down current –VQPS domain 13.83 13.83 2.046 uA
7
Mode Item Description ffgnp0p825v1p980vm40c ffgnp0p750v1p800v85c tt0p750v1p800v85c Unit
TSUR_PD PD to STROBE setup time in read mode 660.204 646.197 665.929 ns
TSUR_PS PS to STROBE setup time in read mode 164.934 161.435 166.364 ns
TSUR_RWL RWL to STROBE setup time in read mode 91.034 89.103 91.824 ns
THR_RWL RWL to STROBE hold time in read mode 90.942 89.013 91.73 ns
TSUR_RSB RSB to STROBE setup time in read mode 91.994 90.065 92.782 ns
THR_RSB RSB to STROBE hold time in read mode 91.62 89.691 92.408 ns
TSUR_CS CSB to STROBE setup time in read mode 45.517 44.551 45.911 ns
THR_CS CSB to STROBE hold time in read mode 76.543 74.919 77.207 ns
Read
TSUR_PG PGENB to STROBE setup time in read mode 91.034 89.103 91.824 ns
Mode
THR_PG PGENB to STROBE hold time in read mode 153.087 149.84 154.415 ns
&
TRD Read strobe pulse width in Array Read Mode 165 162.111 166 ns
Margin
TRD_M Read strobe pulse width in Margin Read1 Mode 412 403.334 415 ns
Read1
A4~A0 & AT1~AT0 to STROBE setup time in
Mode 27.074
TSUR_A 27.661 27.901 ns
read mode
A4~A0 & AT1~AT0 to STROBE hold time in read

THR_A 33.301 32.594 33.589 ns
mode
TSUR_LD LOAD to STROBE setup time in read mode 91.034 89.103 91.824 ns
THR_LD LOAD to STROBE hold time in read mode 153.087 149.84 154.415 ns
TSUR_MR MR to STROBE setup time in read mode 54.62 53.462 55.094 ns
TSUR_TRCS TRCS to STROBE setup time in read mode 48.421 47.394 48.841 ns
THR_TRCS TRCS to STROBE hold time in read mode 46 45.024 46.399 ns
Q31~Q0 access time from STROBE high in

TSQ 159.932 156.539 161.319 ns
Array Read Mode
Q31~Q0 access time from STROBE high in

TSQ_M 406.122 397.506 409.644 ns
Margin Read1 Mode
8
TSUP_PD PD to STROBE setup time in PGM mode 779.66 763.12 786.421 ns
TSUP_PS PS to STROBE setup time in PGM mode 164.934 161.435 166.364 ns
TSUP_RWL RWL to STROBE setup time in PGM mode 91.034 89.103 91.824 ns
THP_RWL RWL to STROBE hold time in PGM mode 90.925 89.002 91.711 ns
TSUP_RSB RSB to STROBE setup time in PGM mode 91.976 90.053 92.762 ns
THP_RSB RSB to STROBE hold time in PGM mode 91.602 89.679 92.388 ns
PGM
TSUP_CS CSB to STROBE setup time in PGM mode 45.517 44.551 45.911 ns
Mode
THP_CS CSB to STROBE hold time in PGM mode 76.543 74.919 77.207 ns
TSUP_PG PGENB to STROBE setup time in PGM mode 91.034 89.103 91.824 ns
THP_PG PGENB to STROBE hold time in PGM mode 153.087 149.84 154.415 ns
A9~A0 & AT1~AT0 to STROBE setup time in

TSUP_A 27.661 27.074 27.901 ns
PGM mode
A9~A0 & AT1~AT0 to STROBE hold time in PGM

THP_A 35.175 34.429 35.481 ns
mode
TSUP_TRCS TRCS to STROBE setup time in PGM mode 48.421 47.394 48.841 ns
THP_TRCS TRCS to STROBE hold time in PGM mode 46 45.024 46.399 ns
TSUP_LD LOAD to STROBE setup time in PGM mode 91.034 89.103 91.824 ns
THP_LD LOAD to STROBE hold time in PGM mode 153.087 149.84 154.415 ns
Average read current during STROBE high –

ILOAD_VDD mA
VDD domain 25.98 23.21 19.365

IACTIVE_VDD mA
Active (STROBE:10Mhz / 50% duty) – VDD domain 13.003 11.619 9.69
current Average read current during STROBE high –

ILOAD_VQPS uA
VQPS domain 1.135 2.908 0.933

IACTIVE_VQPS uA
(STROBE:10Mhz / 50% duty) – VQPS domain 1.134 2.907 0.931
Standby current –VDD domain 2.239 14.223 5.668

Standby ISTANDBY_VDD uA
current

down
9
Mode Item Description tt0p750v1p800v70c tt0p750v1p800v25c ssgnp0p675v1p620v125c Unit

TSUR_PD 670.433 688.44 712.176 ns
mode
TSUR_PS 167.489 171.988 177.918 ns
mode
TSUR_RWL 92.445 94.927 98.2 ns
mode
THR_RWL 92.35 94.83 98.099 ns
mode
TSUR_RSB 93.402 95.882 99.151 ns
mode
THR_RSB 93.028 95.508 98.777 ns
mode
TSUR_CS 46.222 47.464 49.1 ns
mode
Read THR_CS 77.729 79.817 82.569 ns
mode
TSUR_PG 92.445 94.927 98.2 ns
mode
&
THR_PG 155.459 159.634 165.138 ns
Margin mode
Read1 TRD 167.2 172 178 ns
Mode
TRD_M 417.801 429 444 ns
Read1 Mode
TSUR_A 28.09 28.844 29.839 ns
time in read mode
THR_A 33.816 34.725 35.922 ns
time in read mode
TSUR_LD 92.445 94.927 98.2 ns
mode
THR_LD 155.459 159.634 165.138 ns
mode
TSUR_MR 55.467 56.956 58.92 ns
mode
TSUR_TRCS 49.171 50.492 52.233 ns
mode
THR_TRCS 46.713 47.968 49.622 ns
mode
TSQ 162.41 166.772 172.522 ns
TSQ_M 412.414 423.49 438.091 ns
10

TSUP_PD 791.739 813.004 841.035 ns
mode
TSUP_PS 167.489 171.988 177.918 ns
mode
TSUP_RWL 92.445 94.927 98.2 ns
mode
THP_RWL 92.329 94.801 98.059 ns
mode
TSUP_RSB 93.38 95.852 99.111 ns
mode
PGM THP_RSB 93.006 95.478 98.736 ns
mode
46.222 47.464 49.1 ns
mode
THP_CS 77.729 79.817 82.569 ns
mode
TSUP_PG 92.445 94.927 98.2 ns
mode
THP_PG 155.459 159.634 165.138 ns
mode
TSUP_A 28.09 28.844 29.839 ns
time in PGM mode
THP_A 35.721 36.68 37.944 ns
time in PGM mode
TSUP_TRCS 49.171 50.492 52.233 ns
mode
THP_TRCS 46.713 47.968 49.622 ns
mode
TSUP_LD 92.445 94.927 98.2 ns
mode
THP_LD 155.459 159.634 165.138 ns
mode
ILOAD_VDD 18.992 17.881 13.184 mA
high – VDD domain
Active 9.502 8.946 6.6
domain
0.732 0.36 1.874 uA
IACTIVE_VQPS (STROBE:10Mhz / 50% duty) – VQPS uA
0.73 0.358 1.87
domain
Standby ISTANDBY_VDD Standby current –VDD domain 3.385 0.965 14.053 uA

current

down
11
Mode Item Description ssgnp0p675v1p620v0c ssgnp0p675v1p620vm40c Unit
TSUR_PD_CS PD to CSB setup time in read mode 711.23 735.466 ns

THR_PD_CS PD to CSB hold time in read mode 54.084 55.927 ns
TSUR_PS_CS PS to CSB setup time in read mode 138.173 142.881 ns
THR_PS_CS PS to CSB hold time in read mode 111.817 115.627 ns
TSUR_PD 763.896 789.927 ns
mode
THR_PD PD to STROBE hold time in read mode 142.649 147.51 ns
TSUR_PS 190.839 197.342 ns
mode
THR_PS PS to STROBE hold time in read mode 200.382 207.21 ns
TSUR_RWL 105.332 108.921 ns
mode
THR_RWL 105.221 108.806 ns
mode
TSUR_RSB 106.273 109.858 ns
mode
THR_RSB 105.899 109.484 ns
mode
TSUR_CS 52.666 54.461 ns
mode
Read THR_CS 88.565 91.583 ns
mode
TSUR_PG 105.332 108.921 ns
mode
&
THR_PG 177.13 183.166 ns
Margin mode
Read1 TRD 190.639 197 ns
Mode
TRD_M 476.595 493 ns
Read1 Mode
TSUR_A 32.006 33.096 ns
time in read mode
THR_A 38.531 39.844 ns
time in read mode
TSUR_LD 105.332 108.921 ns
mode
THR_LD 177.13 183.166 ns
mode
TSUR_MR 63.199 65.352 ns
mode
THR_MR MR to STROBE hold time in read mode 106.275 109.897 ns
TSUR_TRCS 56.026 57.935 ns
mode
THR_TRCS 53.225 55.039 ns
mode
TSQ 185.051 191.357 ns
TSQ_M 469.905 485.918 ns
TSQH Q31~Q0 hold time to the next STROBE 0 0 ns
12
TSUP_PD_PS PD to PS setup time in PGM mode 711.273 735.511 ns
THP_PD_PS PD to PS hold time in PGM mode 54.912 56.783 ns
TSUP_PS_CS PS to CSB setup time in PGM mode 138.173 142.881 ns
THP_PS_CS PS to CSB hold time in PGM mode 111.817 115.627 ns

TSUP_PD 902.112 932.853 ns
mode
THP_PD PD to STROBE hold time in PGM mode 255.294 263.993 ns
TSUP_PS 190.839 197.342 ns
mode
THP_PS PS to STROBE hold time in PGM mode 200.382 207.21 ns
TSUP_RWL 105.332 108.921 ns
mode
THP_RWL 105.159 108.732 ns
mode
TSUP_RSB 106.211 109.784 ns
mode
PGM THP_RSB 105.836 109.409 ns
mode
52.666 54.461 ns
mode
THP_CS 88.565 91.583 ns
mode
TSUP_PG 105.332 108.921 ns
mode
THP_PG 177.13 183.166 ns
mode
TPGM* Typical program strobe pulse width 5 5 us
TSUP_A 32.006 33.096 ns
time in PGM mode
THP_A 40.7 42.087 ns
time in PGM mode
TSUP_TRCS 56.026 57.935 ns
mode
THP_TRCS 53.225 55.039 ns
mode
TSUP_LD 105.332 108.921 ns
mode
THP_LD 177.13 183.166 ns
mode
ILOAD_VDD 10.253 9.361 mA
high – VDD domain
Active 5.128 4.682
domain
0.236 0.124 uA
IACTIVE_VQPS (STROBE:10Mhz / 50% duty) – VQPS uA
0.233 0.122
domain
Standby ISTANDBY_VDD Standby current –VDD domain 0.315 0.172 uA

current
ISTANDBY_VQPS Standby current –VQPS domain 0.233 0.122 uA
Power IPD_VDD Power-down current –VDD domain 0.038 0.016 uA

down
current IPD_VQPS Power-down current –VQPS domain 0.223 0.111 uA
13
Note: * TPGM_MIN = 4.5us, TPGM_MAX = 5.5us

(1) ffg0p825v1p980v125c: 7nm FinFET model, FFG, 125C, VDD=0.825V, VQPS=1.980V
ffgnp0p825v1p980v125c: 7nm FinFET model, FFGNP, 125C, VDD=0.825V, VQPS=1.980V
ffgnp0p825v1p980vm40c: 7nm FinFET model, FFGNP, -40C, VDD=0.825V, VQPS=1.980V
tt0p750v1p800v85c: 7nm FinFET model, TT, 85C, VDD=0.750V, VQPS=1.800V
ssgnp0p675v1p620v125c: 7nm FinFET model, SSGNP, 125C, VDD=0.675V, VQPS=1.620V
ssgnp0p675v1p620v0c: 7nm FinFET model, SSGNP, 0C, VDD=0.675V, VQPS=1.620V
ssgnp0p675v1p620vm40c: 7nm FinFET model, SSGNP, -40C, VDD=0.675V, VQPS=1.620V
(2) The power-down current, standby current, load current and active current (I PD_VDD/ISTANDBY_VDD/ILOAD_VDD
/IACTIVE_VDD and IPD_VQPS /ISTANDBY_VQPS/ILOAD_VQPS /IACTIVE_VQPS) are based on simulation.
(3) The characterization is based on simulation condition with input slew rate 0.01ns and output load 0.009pF.
The Power Information of VQPS during Programming Mode
Mode Symbol Description WC TC BC Unit
IVQPS_UNPROG The VQPS current flow when CSB=H, PS=H 34.954 2.726 2.441 mA
IVSS_UNPROG The VSS current flow when CSB=H, PS=H 35.042 2.730 2.443 mA
VQPS IVDD_ UNPROG The VDD current flow when CSB=H, PS=H 0.088 0.004 0.002 mA
Current IVQPS_PROG The VQPS current flow during programming 63.954 38.045 37.497 mA
IVSS_PROG The VSS current flow during programming 64.043 38.049 37.499 mA
IVDD_PROG The VDD current flow during programming 0.089 0.004 0.002 mA
Note
(1) WC (worst corner) : 7nm FinFET model, FF, 125C, VDD=0.825, VQPS=1.89V
TC (typical corner): 7nm FinFET model, TT, 25C, VDD=0.75V, VQPS=1.8V
BC (best corner): 7nm FinFET model, SS, -40C, VDD=0.675V, VQPS=1.71V
(2) The power information is based on simulation.
14
Operation Modes
This electrical fuse macro has 11 operation The data will be stored in registers and remain
modes: array program (A_PGM), redundancy there until power-down or power-off. In subsequent
program (R_PGM), array read (A_READ), array read, when read access the failure bit in the
redundancy read (R_READ), power-down, standby main array, the corresponding output data will be
modes and 5 test modes: margin A_READ1, margin corrected automatically.
R_READ1, T_READ, margin T_READ1 and
T_PGM modes. Redundancy Program Mode (R_PGM)
In this mode, this macro is ready for electrical fuse
Array Program Mode (A_PGM)
programming on redundancy bits. Any bit within the
In this mode, this macro is ready for electrical redundancy array can be programmed in any order
fuse programming. Any bit in this macro can be by raising STROBE high with a proper address
programmed in any order by raising STROBE high selected. The selected address needs to satisfy
with a proper address selected. The selected setup and hold time with respect to STROBE to be
address needs to satisfy setup and hold time with valid. Only one bit is programmed at a time.
respect to STROBE to be valid. Only one bit is
programmed at a time. Redundancy Read Mode (R_READ); Margin
R_READ1 Mode
Array Read Mode (A_READ); Margin A_READ1 In these 2 modes, this macro is ready to read data
Mode from redundancy information row to register,
In these 2 modes, this macro is ready to read Q31~Q0 and RF3~RF0 by two cycles STROBE
data from fuse cells. 32 bits Q31~Q0 can be read high. During redundancy read operation, address
out by raising STROBE high with a proper address signals A9~A0 are “don’t care” except A4.
selected. During read operations, address signals The read trip point of Redundancy READ Mode is
A9~A5 are “don’t care”. The read trip point of Array lower than that of Margin R_READ1 Mode.
Read Mode is lower than that of Margin A_READ1
Mode. Power-down Mode
If RSB is at “L” and enable redundancy function, In the power-down mode, the macro consumes
please MUST enter the redundancy read mode the least current from VDD.
(R_READ or Margin R_READ1) and read the RIR
data once prior to the array read mode (A_READ Standby Mode
or Margin A_READ1) after power-up even if When PD=L, PS=L, CSB=H, STROBE, PGENB,
repairing is not needed. Redundancy read requires LOAD, MR, RWL, RSB and TRCS are “don’t care”,
two strobe cycles to read out completed repairing the macro is at standby mode.
information.
15
Test Modes
Test Column Program Mode (T_PGM)
Test row and test columns are used to detect
periphery circuit defects. They are identical to rows In this mode, two test columns are ready for
and columns in the fuse array and are placed at the electrical fuse programming. Any bit within test
edge of the array. columns can be programmed in any order by raising
If both of data ‘0’ and data ‘1’ can be read out STROBE high with a proper address selected. The
correctly, program and read path circuits, selected address needs to satisfy setup and hold
corresponding decoders and other periphery circuits time with respect to STROBE to be valid. Only one
are assumed to be working correctly. bit is programmed at a time.
The test row and test columns can serve as a When one of the test columns is selected,
simple early defect screening feature before product address signals A9~A4 are “don’t care” and A3~A0
ship-out. For example, if some fuses are reserved to can control which bit in this test column is
be programmed in field, customers can use this programmed.
feature to check peripheral circuit before ship parts to Note that test row is read-only.
field stage to avoid the field return with higher cost

paid.
Test Row/Column Read Mode (T_READ); Margin

T_READ1 Mode
In these 2 modes, one test row and two test

columns are ready to read data from fuse cells. 32 bits
Q31~Q0 can be read out by raising STROBE high with
a proper address selected. The read trip point of
T_READ Mode is lower than that of Margin T_READ1
Mode.
When the test row is selected, address signals
A3~A0 and A9~A5 are “don ’ t care ”. Address
signal A4 can control to read which bit line within the
IO in this test row and read out from Q31~Q0.
When one of the test columns is selected, address
signals A9~A4 are “don’t care” and A3~A0 can control
to read which bit in this test column. Only one test
column will be accessed at one time so either the data
of 1st test column can be read out from Q0 or the data
of 2nd test column can be read out from Q31.
16
Timing Diagram of Operation Modes
A_PGM Mode
TSUP_PD THP_PD
PD T SUP_PD_PS THP_PD_PS
TSUP_PS THP_PS
PS TSUP_PS_CS THP_PS_CS
TSUP_CS T HP_CS
CSB
TSUP_PG THP_PG
PGENB
A9~A0
TPGM
TSUP_A THP_A
STROBE
LOAD TSUP_LD THP_LD
RWL TSUP_RWL THP_RWL
RSB TSUP_RSB THP_RSB
TRCS TSUP_TRCS THP_TRCS
Q31~Q0
RF3~RF0
A_READ Mode; Margin A_READ1 Mode

TSUR_PD THR_PD
PD T SUR_PD_CS THR_PD_CS
TSUR_PS T HR_PS
PS TSUR_PS_CS THR_PS_CS
CSB TSUR_CS THR_CS
MR TSUR_MR THR_MR
PGENB
TSUR_PG THR_PG
A4~A0
TRD;TRD_M
TSUR_A THR_A
STROBE
LOAD TSUR_LD THR_LD
TSUR_RWL THR_RWL
RWL
TSUR_RSB THR_RSB
RSB
TSUR_TRCS THR_TRCS
TRCS
TSQ;TSQ_M TSQ;TSQ_M
Q31~Q0
TSQH
RF3~RF0
17
R_PGM Mode
TSUP_PD THP_PD
PD TSUP_PD_PS THP_PD_PS
TSUP_PS THP_PS
TSUP_CS THP_CS
CSB
TSUP_PG THP_PG
PGENB
A9~A4
TPGM
TSUP_A THP_A
STROBE
TSUP_LD THP_LD
LOAD
TSUP_RSB THP_RSB
RSB
RWL TSUP_RWL THP_RWL

TSUP_TRCS THP_TRCS
TRCS
Q31~Q0
RF3~RF0
R_READ Mode; Margin R_READ1 Mode

TSUR_PD THR_PD
PD TSUR_PD_CS THR_PD_CS
TSUR_PS THR_PS
TSUR_CS THR_CS
CSB
MR TSUR_MR THR_MR
PGENB TSUR_PG THR_PG
A4
TRD;TRD_M
STROBE TSUR_A THR_A
LOAD TSUR_LD THR_LD

TSUR_RSB THR_RSB
RSB
RWL TSUR_RWL THR_RWL

TSUR_TE THR_TE
TRCS TSQH
TSQ ;TSQ_M
[Q31~Q0]0 [Q31~Q0]1
Q31~Q0
TSQ ;TSQ_M
RF3~RF2
TSQ ;TSQ_M
RF1~RF0
18
T_PGM Mode
TSUP_PD THP_PD
PD TSUP_PD_PS THP_PD_PS
TSUP_PS THP_PS
TSUP_CS THP_CS
CSB
TSUP_PG THP_PG
PGENB
A9~A0
TPGM
TSUP_A THP_A
STROBE
LOAD TSUP_LD THP_LD
TSUP_RWL THP_RWL
RWL
TSUP_RSB THP_RSB
RSB
TSUR_TRCS THR_TRCS
TRCS TSUP_A THP_A
AT0
AT1 THP_A
Q31~Q0
RF3~RF0
T_READ Mode; Margin T_READ1 Mode

TSUR_PD THR_PD
PD T SUR_PD_CS THR_PD_CS
TSUR_PS THR_PS
CSB TSUR_CS THR_CS
MR TSUR_MR THR_MR
PGENB
TSUR_PG THR_PG
A4~A0
TRD;TRD_M
TSUR_A THR_A
STROBE
LOAD TSUR_LD THR_LD
TSUR_RWL THR_RWL
RWL
TSUR_RSB THR_RSB
RSB
TSUR_TRCS THR_TRCS
TRCS
TSUR_A THR_A
AT1~AT0
TSQ;TSQ_M TSQ;TSQ_M
Q31~Q0
TSQH
RF3~RF0
19
Note
(1) [Q31~Q0]0 = [FB[1]_Disable, N/A , N/A, N/A, FB[1]_A9, FB[1]_A8, …, FB[1]_A1, FB[1]_A0, FB[1]_data, RF[1],
FB[0]_Disable, N/A , N/A, N/A, FB[0]_A9, FB[0]_A8, …, FB[0]_A1, FB[0]_A0, FB[0]_data, RF[0]]
[Q31~Q0]1 = [FB[3]_Disable, N/A , N/A, N/A, FB[3]_A9, FB[3]_A8, …, FB[3]_A1, FB[3]_A0, FB[3]_data, RF[3],
FB[2]_Disable, N/A , N/A, N/A, FB[2]_A9, FB[2]_A8, …, FB[2]_A1, FB[2]_A0, FB[2]_data, RF[2]]
th
(2) FB[n]_Disable is used to disregard the n redundancy bits. When set to 1, the contents of the corresponding
redundancy bits are ignored.
(3) Please MUST set PS=L except program mode.
(4) Please MUST set PD=L except power-down mode.
(5) PS=H, PD=H state is not allowed.
(6) Q31~Q0 will be reset to “0” once CSB at high.
(7) RF3~RF0 will be reset to “0” once CSB at high or RSB/TRCS goes high.
(8) During redundancy program operation, address signals A3~A0 are “don’t care”.
(9) During array read operation and margin A_READ1 mode, address signals A9~A5 are “don’t care”.
(10) During redundancy read operation and margin R_READ1 mode, address signals A9~A5 and A3~A0 are
“don’t care”.
(11) No data access allowed at the rising edge of CSB.
(12) Two STROBE cycles ([A4] = [0], [1] or [1], [0]) are needed in order to completely load the data into registers.
(13) ONLY the allowable operation modes defined in the datasheet are covered in Verilog model.
(14) Verilog model may not report timing violation for all illegal-timing condition. In order to avoid misuse of
electrical fuse IP, customer has to follow the spec of datasheet.
(15) Post layout Verilog simulation should be included in design flow.
20
The Mapping Table of Redundancy Bits
A9 A8 A7 A6 A5 A4 A3~A0
RF[0] 0 0 0 0 0 0 X
FB[0]_Data 0 0 0 0 1 0 X
FB[0]_A0 0 0 0 1 0 0 X
FB[0]_A1 0 0 0 1 1 0 X
FB[0]_A2 0 0 1 0 0 0 X
FB[0]_A3 0 0 1 0 1 0 X
FB[0]_A4 0 0 1 1 0 0 X
FB[0]_A5 0 0 1 1 1 0 X
FB[0]_A6 0 1 0 0 0 0 X
FB[0]_A7 0 1 0 0 1 0 X
FB[0]_A8 0 1 0 1 0 0 X
FB[0]_A9 0 1 0 1 1 0 X
N/A 0 1 1 0 0 0 X
N/A 0 1 1 0 1 0 X
N/A 0 1 1 1 0 0 X
FB[0]_Disable 0 1 1 1 1 0 X
RF[1] 1 0 0 0 0 0 X
FB[1]_Data 1 0 0 0 1 0 X
FB[1]_A0 1 0 0 1 0 0 X
FB[1]_A1 1 0 0 1 1 0 X
FB[1]_A2 1 0 1 0 0 0 X
FB[1]_A3 1 0 1 0 1 0 X
FB[1]_A4 1 0 1 1 0 0 X
FB[1]_A5 1 0 1 1 1 0 X
FB[1]_A6 1 1 0 0 0 0 X
FB[1]_A7 1 1 0 0 1 0 X
FB[1]_A8 1 1 0 1 0 0 X
FB[1]_A9 1 1 0 1 1 0 X
N/A 1 1 1 0 0 0 X
N/A 1 1 1 0 1 0 X
N/A 1 1 1 1 0 0 X
FB[1]_Disable 1 1 1 1 1 0 X
21
A9 A8 A7 A6 A5 A4 A3~A0
RF[2] 0 0 0 0 0 1 X
FB[2]_Data 0 0 0 0 1 1 X
FB[2]_A0 0 0 0 1 0 1 X
FB[2]_A1 0 0 0 1 1 1 X
FB[2]_A2 0 0 1 0 0 1 X
FB[2]_A3 0 0 1 0 1 1 X
FB[2]_A4 0 0 1 1 0 1 X
FB[2]_A5 0 0 1 1 1 1 X
FB[2]_A6 0 1 0 0 0 1 X
FB[2]_A7 0 1 0 0 1 1 X
FB[2]_A8 0 1 0 1 0 1 X
FB[2]_A9 0 1 0 1 1 1 X
N/A 0 1 1 0 0 1 X
N/A 0 1 1 0 1 1 X
N/A 0 1 1 1 0 1 X
FB[2]_Disable 0 1 1 1 1 1 X
RF[3] 1 0 0 0 0 1 X
FB[3]_Data 1 0 0 0 1 1 X
FB[3]_A0 1 0 0 1 0 1 X
FB[3]_A1 1 0 0 1 1 1 X
FB[3]_A2 1 0 1 0 0 1 X
FB[3]_A3 1 0 1 0 1 1 X
FB[3]_A4 1 0 1 1 0 1 X
FB[3]_A5 1 0 1 1 1 1 X
FB[3]_A6 1 1 0 0 0 1 X
FB[3]_A7 1 1 0 0 1 1 X
FB[3]_A8 1 1 0 1 0 1 X
FB[3]_A9 1 1 0 1 1 1 X
N/A 1 1 1 0 0 1 X
N/A 1 1 1 0 1 1 X
N/A 1 1 1 1 0 1 X
FB[3]_Disable 1 1 1 1 1 1 X
22
Note
A9~A0 is the address of RIR (Redundancy Information Row).
RF[n] is the flag to record whether the redundancy bit has been used or not.
th
FB[n]_Data is the correct data of n redundancy bit, which will be stored in RIR.
th
FB[n]_A9~A0 is the address data of n redundancy bit, which will be stored in RIR.
th
FB[n]_Disable is used to disregard the n redundancy bits. When set to “1”, this repaired bit will be ineffective and
disregarded.
Logic Scramble
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AT0 AT1
X0 X1 X2 X3 Y0 D0 D1 D2 D3 D4 T0 T1
Word Line Decoder BL Decoder Output (Q31 ~ Q0) Decoder Test row/columns Decoder
A9~A0 and AT1~AT0 are the address pins.
X3~X0 are used as Word Line decoder. Y0 are used as Bit Line decoder. D4~D0 are used as output (Q31~Q0)
scramble. And T1~T0 are used as test row and test columns decoder.
Test Row/Column Truth Table
Mode TRCS AT1 AT0 Remark

st
H H L Select 1 test column
T_PGM mode nd
H H H Select 2 test column
Mode TRCS AT1 AT0 Remark

H L L Select test row
T_READ mode & st
H H L Select 1 test column
Margin T _READ1 nd
H H H Select 2 test column
Fixed test row = [CCCC,CCCC,CCCC,CCCC]

When selecting test row for reading, A[4]=0, Q[31:0]= [AAAA,AAAA]hex
When selecting test row for reading, A[4]=1, Q[31:0]= [AAAA,AAAA]hex
23
Redundancy Examples
Step1: Decide to enable or disable redundancy feature (repair function) in product design stage
 Enable => Tie RSB to DC-Low; Disable=> Tie RSB to DC-High

 When RSB is at “H” to disable the redundancy feature (repair function), it’s not necessary to enter the
redundancy read mode (R_READ or Margin R_READ1) and read the RIR data once prior to the array
read mode (A_READ or Margin A_READ1) after power-up.
 When RSB is at “L” to enable the redundancy feature (repair function), please MUST enter the
redundancy read mode (R_READ or Margin R_READ1) and read the RIR data once prior to the array
read mode (A_READ or Margin A_READ1) after power-up even if repairing is not needed. Redundancy
read requires two strobe cycles to read out the complete repairing information. The data will be stored in
registers and will remain there until power-down or power-off. In subsequent array read, when read
access the failure bit in the main array, the corresponding output data will be corrected automatically.
Step2: Identified 1 failure bit in the array, use 1 redundancy bit to replace this 1 failed array bit
[10101,01010] denotes [A9..A5, A4..A0] and A9=1, A8=0, A7=1, A6=0, A5=1, A4=0, A3=1, A2=0, A1=1,
A0=0.
 Expected logic-1 but read out is logic-0 at address Q30[xxxxx,00000]=[11110,00000]. Then enter the
R_PGM and program RF[0]=1; FB[0]_data=1, FB[0]_A0=0, FB[0]_A1=0, FB[0]_A2=0, FB[0]_A3=0,
FB[0]_A4=0, FB[0]_A5=0, FB[0]_A6=1, FB[0]_A7=1, FB[0]_A8=1, FB[0]_A9=1, FB[0]_Disable=0
according to mapping table of redundancy bits. In tabular format:
Set RF[0]=1 by programming [00000,0xxxx]
Set FB[0]_data=1 by programming [00001,0xxxx]
Set FB[0]_A0=0 by NOT programming [00010,0xxxx]
Set FB[0]_A6=1 by programming [01000,0xxxx]
don’t care by NOT programming [01100,0xxxx]
Set FB[0]_Disable=0 by NOT programming [01111,0xxxx]
24
Step3: Repair after repair=> Give up the failed repair bit and use another repair bit to replace it.
 After repair, the failed array bit still can’t be fixed (i.e. wrong information (either address or data or RF)
was programmed into the repair bit). Then we can disable and give up repair the failed array bit by
program FB[0]_Disable to “1” and use another repair bit such as FB[1] to repair the failed array bit
again.
 Enter the R_PGM and program FB[0]_Disable=1, RF[1]=1; FB[1]_data=1, FB[1]_A0=0, FB[1]_A1=0,
FB[1]_A2=0, FB[1]_A3=0, FB[1]_A4=0, FB[1]_A5=0, FB[1]_A6=1, FB[1]_A7=1, FB[1]_A8=1,
FB[1]_A9=1, FB[1]_Disable=0 according to mapping table of redundancy bits. In tabular format:
Set FB[0]_Disable=1 by programming [01111,0xxxx]
Set RF[1]=1 by programming [10000,0xxxx]
Set FB[1]_data=1 by programming [10001,0xxxx]
Set FB[1]_Disable=0 by NOT programming [11111,0xxxx]
Note
When RSB is at “L” to enable the redundancy feature (repair function), please MUST enter the redundancy
read mode (R_READ or Margin R_READ1) and read the RIR data once prior to the array read mode
(A_READ or Margin A_READ1) after power-up even if repairing is not needed. Redundancy read requires
two strobe cycles to read out the complete repairing information. The data will be stored in registers and will
remain there until power-down or power-off. In subsequent array read, when read access the failure bit in the
main array, the corresponding output data will be corrected automatically.
25
Power and Ground Bus
 The electrical fuse macros require strong  The MAX number of electrical fuse macros
current during programming. A small for sharing one VQPS Pad/ Bump is 8.
resistance difference can reduce the  Above electrical fuse macro power
programming effectiveness (weak program)
connection resistance calculation is based on
and can cause yield loss as well as long term
the following assumptions - only one
reliability issue. Therefore, there are
electrical fuse macro is programmed at a
limitations in power and ground bus time , the remaining electrical fuse macros
resistance connected to this macro.
should be inactive with PS=L and CSB=H all
 Fig.1 describes the power and ground the time. This is to avoid inducing
connection of electrical fuse macros and unnecessary leakage current and cause
VQPS pad. electrical fuse program failure.
 Only one electrical fuse bit can be
 R(n)VSS is the connection resistance
between Electrical Fuse Macro_(n) and VSS programmed at a time due to large program
pad/bump; current needed. Thus only one electrical fuse
macro can be activated for program at a time.
R(n)VDD is the connection resistance
between Electrical Fuse Macro_(n) and VDD  Adapting higher-than-spec program voltage
pad/bump; or longer-than-spec program time to
compensate for higher-than-spec routing
R(n)VQPS is the connection resistance resistance is NOT allowed.
between Electrical Fuse Macro_(n) and
VQPS pad/bump;  For tester program, please make sure the
The MAX R(0,1,n-1,n)VSS is 1 ohm VQPS pad is connected to a power channel
rather than a signal channel in order to
The MAX R(0,1,n-1,n)VQPS 2 ohm provide the large current necessary for
The MAX R(0,1,n-1,n)VDD is 3 ohm programming.
VDD
R(0)VDD
R(0) VQPS Electrical
Fuse
Macro _(0)
R(0) VSS VSS
VDD
R(n-1)VDD
R(n-1) VQPS Electrical
VQPS Pad
or Fuse
Bump Macro_(n-1)
R(n-1) VSS VSS
VDD
R(n)VDD
R(n) VQPS Electrical
Fuse
Macro_(n)
R(n) VSS VSS
Fig.1
26
Power Sequence
 Power-up and down sequence is important

to electrical fuse operations since electrical
fuse bits are sensitive to unintended current
surge. Current surge may change the data
in the electrical fuse.
 Please MUST keep PS=L, STROBE=L
during VQPS and VDD power-up to avoid
unintentional program.
 CSB MUST go High (follow VDD) when
VDD reached logic operation level to avoid
 VQPS ramp-up slew rate MUST be slower
than 1.8V/30us to avoid latch-up on ESD
macro.
 PS=H, PD=H state is not allowed to avoid
 Please MUST set PS=L except program
mode.
 Please MUST set PD=L except power-down
mode.
 Please check “Power-up & Power-down
Sequence Guideline” in chapter 3 of
Application Note for details.
27
ESD Guideline
 TEF07FESD_P_C180518 is only for  If TSMC IO is used and IO voltage is 1.8V,
front-end kits usage only. For back-end then “PVDD2ANA” is suggested to be used.
kits, please refer to TEF07FESD_P library. Please confirm with your FAE to ensure the
use of the latest IO library version.
 MUST insert one “TEF07FESD_P” ESD
macro between VQPS pad and electrical
fuse IP for ESD protection.
 MUST connect “ TEF07FESD_P” ESD
macro between VQPS and VSS.
 For each VQPS power domain, MUST have
one ESD macro, either TEF07FESD_P_V or
TEF07FESD_P_H from the library,
TEF07FESD_P. Please refer to the diagram
for the connections.
 One ESD macro is enough for one VQPS
power domain.  Please check “Layout Guidelines for
 The connection resistance (RXESD), where x Latch-Up” in chapter 9 of Design Rules,
th
= 0 to m, between ESD macro and x VQPS T-N07-CL-DR-001, for details.
pad/bump should be less than the minimum  The boundary to OD injector is required to
connection resistance {min[R XEFUSE(0), be larger than 15um.
RXEFUSE(1),…RXEFUSE(n)]} between electrical
th
fuse IPs and x VQPS pad/bump.  The customer need to run Latch-Up rule
check.
VQPS PAD(0) VQPS PAD(1) VQPS PAD(m)

...
R1ESD
ESD macro
R1EFUSE(0)
R1EFUSE(n) VSS
R1EFUSE(1)
Efuse IP(0) Efuse IP(1) ... Efuse IP(n)
28
Double Bits Design
 Double bits solution is strongly suggested to assure better yield and reliability for early NTO before
qualification is completed.
An Example of Double Bits Design
 The same data bit is stored in both efuse macro 0 and efuse macro 1. The final data is obtained by an
“OR” operation of values from both macros with the same address.
 Customers can replicate the fuse macros as shown below to create double bits design:
PS[0] PS[1]
Efuse Efuse
Macro 0 Macro 1
CSB
STROBE
...
ADDRESS
Q0<31:0> Q1<31:0>
Q<31:0>
 Double bits can be implemented by programming the same data twice within the same macro at different
addresses, then implementing exclusive “OR” operation to obtain the final data. Please choose a macro
with density equal to or larger than twice the density intended to use.
PS
CSB
STROBE 2K Efuse Macro (Physical)
... 1K Efuse Macro (Logical)
ADDRESS
Q<0> Q<1> Q<31>
Blue represents the physical

array and output
DB0*DB1 Black represents the logical
DB0*DB1 DB0*DB1 array and output
Q<0:1> Q<30:31>
29
Special Note
 Double bit solution is strongly suggested to
assure better yield and reliability for early NTO
 The maximum total bit count on the chip should not
before qualification is completed.
exceed 64K. Use of over 64K bit count should be
 Please customers MUST integrate both Margin consulted with TSMC and got approval.
A_READ1 and Margin R_READ1 mode into chip
design.  All power pins at different locations MUST be
connected, but connection can be made to just one
 Please customers MUST integrate redundancy
of the metal layers if the power pins are overlaid for
feature and all redundancy bits of this electrical
different metal layers.
fuse macro into chip design except when double
bits is implemented for the electrical fuse macro.  ONLY the allowable operation modes defined in the
 Please customers MUST refer to “e-Fuse test datasheet are covered in Verilog model.
flow”, which is defined in “TSMC Electrical Fuse  Verilog model may not report timing violation for all
General Application Notes”. illegal-timing condition. In order to avoid misuse of
 To prevent false operation of redundancy circuit electrical fuse IP, customer has to follow the spec of
that results in false data output, when RSB is at datasheet.
“L” to enable the redundancy feature (repair  Post layout Verilog simulation should be included in
function), please MUST enter the redundancy design flow.
read mode (R_READ or Margin R_READ1) and
read the RIR data once prior to the array read  It MUST drop sufficient VIAs from metal top down to
mode (A_READ or Margin A_READ1) after all the power and ground pins of metal 5 for ESD
power-up even if repairing is not needed. cells TEF07FESD_P.
 Each individual fuse bit can be programmed only  It is necessary to select the proper
once. If the same fuse bit is programmed more TEF07FESD_P_V or TEF07FESD_P_H cell
than once, the result will become unpredictable.
according to its placement.
 Wire routing is allowed on metal6 and above.
 All power pins MUST be connected.
poly
 The P/G metal width is required to be the same
as those of IP macro’s P/G pins during P/G
TEF07FESD_P_V
routing.
 The P/G metal width should not be less than IP
macro’s P/G pins.
poly
 Read operation is to unload data from electrical TEF07FESD_P_H
fuse. The default value (not program) of bit cell is Length
Length
logic “0”. A programmed electrical fuse bit cell is
(0,0) (0,0)
logic “1”. To insure the functionality of the
electrical fuse, it’s preferred to unload/read the
fuse data to check its values (should be all
“zeros”) before programming.
 For I/O 1.8V,
TEF07F32X32HD18_PHRM_C180518 electrical
fuse IP is in-pair with TEF07FESD_P ESD
macro.
Technology Electrical fuse IP In-pair ESD macro I/O voltage
TEF07FESD_P
N7 FinFET TEF07F32X32HD18_PHRM_C180518 1.8V
TEF07FESD_P_C180518
* TEF07FESD_P_C180518 is only for FE-kits usage.
30

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TEF07F32X32HD18_PHRM_C180518

TSMC Electrical Fuse Datasheet Version 120A

TEF07F32X32HD18_PHRM_C180518 – 1024 bits High Density Electrical Fuse

A3~A0 Electrical Fuse

LOAD A4 A9~A5 MR Q31~Q0 RF3~RF0

Pin Name Signal Type Description

Operation Mode Truth Table

Mode CSB STROBE LOAD PGENB PS PD MR RSB RWL TRCS VQPS

R _READ mode L H H H L L L L H L 0V or floating or 1.8V+/-10%

T_READ mode L H H H L L L X X H 0V or floating or 1.8V+/-10%

R _PGM mode L H L L H L X L H L 1.8V+/-5%

T_PGM mode L H L L H L X X X H 1.8V+/-5%

Standby mode H X X X L L X X X X 0V or floating or 1.8V+/-10%

Power-down mode H X X X L H X X X X 0V or floating or 1.8V+/-10%

Pin Symbol Min Max Unit

Mode Item Description ffg0p825v1p980v125c ffgnp0p825v1p980v125c ffgnp0p825v1p980v0c Unit

TSUR_PD_CS PD to CSB setup time in read mode 596.016 596.396 607.446 ns

TSUP_PD_PS PD to PS setup time in PGM mode 596.054 596.435 607.485 ns

THP_PD_PS PD to PS hold time in PGM mode 46.017 46.046 46.899 ns

TSUP_PS_CS PS to CSB setup time in PGM mode 115.79 115.864 118.01 ns

THP_PS_CS PS to CSB hold time in PGM mode 93.704 93.764 95.501 ns

Standby ISTANDBY_VDD Standby current –VDD domain 87.916 81.47 3.919 uA

Power IPD_VDD Power-down current –VDD domain 6.848 6.657 0.366 uA

Mode Item Description ffgnp0p825v1p980vm40c ffgnp0p750v1p800v85c tt0p750v1p800v85c Unit

TSUR_PD_CS PD to CSB setup time in read mode 614.687 601.646 620.018 ns

THR_PD_CS PD to CSB hold time in read mode 46.743 45.751 47.148 ns

TSUR_PS_CS PS to CSB setup time in read mode 119.417 116.884 120.453 ns

THR_PS_CS PS to CSB hold time in read mode 96.639 94.589 97.477 ns

TSUR_PD PD to STROBE setup time in read mode 660.204 646.197 665.929 ns

THR_PD PD to STROBE hold time in read mode 123.286 120.67 124.355 ns

TSUR_PS PS to STROBE setup time in read mode 164.934 161.435 166.364 ns

THR_PS PS to STROBE hold time in read mode 173.182 169.508 174.684 ns

A4~A0 & AT1~AT0 to STROBE hold time in read

TSUR_MR MR to STROBE setup time in read mode 54.62 53.462 55.094 ns

THR_MR MR to STROBE hold time in read mode 91.849 89.901 92.646 ns

THR_TRCS TRCS to STROBE hold time in read mode 46 45.024 46.399 ns

Q31~Q0 access time from STROBE high in

Q31~Q0 access time from STROBE high in

TSQH Q31~Q0 hold time to the next STROBE 0 0 0 ns

TSUP_PD_PS PD to PS setup time in PGM mode 614.726 601.685 620.057 ns

THP_PD_PS PD to PS hold time in PGM mode 47.458 46.451 47.87 ns

TSUP_PS_CS PS to CSB setup time in PGM mode 119.417 116.884 120.453 ns

THP_PS_CS PS to CSB hold time in PGM mode 96.639 94.589 97.477 ns

TSUP_PD PD to STROBE setup time in PGM mode 779.66 763.12 786.421 ns

THP_PD PD to STROBE hold time in PGM mode 220.64 215.959 222.554 ns

TSUP_PS PS to STROBE setup time in PGM mode 164.934 161.435 166.364 ns

THP_PS PS to STROBE hold time in PGM mode 173.182 169.508 174.684 ns

TPGM* Typical program strobe pulse width 5 5 5 us

A9~A0 & AT1~AT0 to STROBE setup time in

A9~A0 & AT1~AT0 to STROBE hold time in PGM

THP_TRCS TRCS to STROBE hold time in PGM mode 46 45.024 46.399 ns

Average read current during STROBE high –

Average current during normal read

current Average read current during STROBE high –

Average current during normal read

Standby current –VDD domain 2.239 14.223 5.668

Power IPD_VDD Power-down current –VDD domain 0.164 1.092 0.402 uA

Mode Item Description tt0p750v1p800v70c tt0p750v1p800v25c ssgnp0p675v1p620v125c Unit

TSUR_PD_CS PD to CSB setup time in read mode 624.211 640.976 663.076 ns