8085 4 Direct Memory Acces & Parallel Data Transfer

METHODS OF DATA TRANSFER
AND INTERRUPT STRUCTURE IN 8085 157
enoram will be executed as ISRs. It is an efficient technique because processor

eis not wasted in waiting while
I/0 device is
an
getting ready or not ready.
slow /0 devices can be interfaced for data transfer
the using interrupt-driven
technique.
54 DIRECT MEMORY ACCESS oo d

Tn nrogrammed I/O data transter, the processor is
actively involved in the entire
data transfer process. So, the data transfer rate is limited. The processor is tied
un and processor time is wasted. To overcome these disadvantages, the direct
memory access (DMA) method of data transfer is used.
Direct memory access is a technique to transfer data between the
peripheral
VO devices and the memory, without the intervention of the processor. The basic
dea is to transfer blocks of data directly between the memory and the peripherals.
Even though the transtfer is done without the processor, the processor initiates the
DMA operation. This technique is generally used to transfer large blocks of data
between memory and I/O. During DMA data transfer, the processor/CPU is kept
in an idle suspended state called as Hold state. DMA performs high-speed data
transfer to and from mass storage peripheral devices such as hard disk drives,
magnetic tapes, CD ROMs, and video controllers. A hard disk may have a transfer
rate of 5 Mbps, i.e., one byte every 200ns. Performing such data transfer using the
CPU is not only undesirable but also unnecessary, since the CPU transfer rate is
limited by the speed of the memory and peripheral devices.
Under normal circumstances, the CPU has full control of the address and data
buses in the system. When direct memory access occurs, an external device or
DMA controller takes over the temporary control of the system bus from the CPU.
The CPU writes necessary control words into the DMA controller, to indicate the
following details about the data transfer: read or write operation, device address
involved, starting address of the data memory block and the amount of data to
be transferred. After this initialization, the DMA controller takes care of the data
transfer. In the 8085, the hold request is received and acknowledged using the
HOLD and HLDA pins, respectively.
The sequence of events in a typical DMA process is as follows:
) The peripheral or the DMA controller asserts one of the request pins (such
as HOLD) for holding the
processor
i) The processor completes its current instruction and enters into the Hold
state. In the Hold state, the processor temporarily stops the execution of the
instruction and releases the address and data buses by making them enter
into a high impedance state.
n The processor issues a Hold Acknowledge (HLDA) signal to indicate the
release of bus control to the peripheral or the DMA controller,
iv) The DMA operation starts.
(Upon completion of the DMA operation, the peripheral or the DMA
controller removes the Hold signal applied to the processor and relinquishes
bus control.
158 MICROPROCESSORS AND MICROCONTROLLERS
In general, a DMA controller can interface several peripherals that mav

request DMA with the processor. It is the controller that decides the priority of
DMA requests that are received simultaneously from many peripherals. It then
communicates with the peripheral device and the processor, and provides memory
addresses for transferring data. The 8237 programmable DMA controller is the
controller device that is most commonly used with the 8085 and 8088. It is a
four-channel device, with each channel being dedicated to a particular peripheral
device. In addition, each channel is capable of addressing 64 KB of memory.
DMA data transfer can be divided into two types:

) burst or block transfer mode
(i) cycle stealing or interleaved mode
In burst mode of DMA data transfer, a complete block of data is transferred in a
or DMA controller
single DMA cycle. The system bus is released by the peripheral
mode of data
only after the required bytes of data are transferred. In cycle stealing
transfer, a block of data is transferred over many DMA cycles. The system bus is
released to the processor after a byte or a set of bytes are transferred in one DMA
activities for a long time.
cycle. Thus, the processor is not suspended from its
takes several DMA cycles to complete the transfer of one block of data.
5.5 PARALLEL DATA TRANSFERn0o

In parallel mode of data transfer, all the bits in a word are simultaneously
transmitted. Since the 8085 word consists of eight bits, all the eight bits are
transmitted and received in parallel form. In some special cases, the number of
data bits transferred will be lesser than eight. In general, parallel data transfer
is used for transfer of data over short distances such as within a system, within
a printed circuit board (PCB), etc. It can be done either in polled mode or in
interrupt-driven mode. In polled method, data is read from the input device by the
processor at a time determined by the processor. This polled mode of data transfer
can be done in two ways-synchronous or simple I/0 and handshake /O.
In simple or synchronous mode, data is read from the input device by the
processor irrespective of the status of the input device. It is assumed that the
input device is in synchronism with the processor and that it is ready with data
whenever the processor reads the data. Similarly, the data is writteninto the output
device irrespective of its status. The processor assumes that the output device is in
synchronism with the processor.
In handshake VO mode, the processor checks for the status of the 10 devices
before data transfer. An input device gives a signal to the
processor, indicating that
it is ready with the data. The processor checks continuously for the reception or
this signal and upon reception can read the data.
Similarly, an output device gives
a signal to the processor, indicating that it can accept data. The processor, before
writing data to the output device, checks for this signal. If the signal indicating
readiness of the output device is available, the processor can write the data o
the output device. The signals that are transferred between the devices and tne
processor are called handshake signals.

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METHODS OF DATA TRANSFER

AND INTERRUPT STRUCTURE IN 8085 157

enoram will be executed as ISRs. It is an efficient technique because processor

54 DIRECT MEMORY ACCESS oo d

In general, a DMA controller can interface several peripherals that mav

DMA data transfer can be divided into two types:

5.5 PARALLEL DATA TRANSFERn0o

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