JS28F128J3D
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Datasheet
Product Features
■ Architecture ■ Security
— High-density symmetrical 128-Kbyte — Enhanced security options for code
blocks protection
—128 Mbit (128 blocks) — 128-bit Protection Register
—64 Mbit (64 blocks) —64-bit Unique device identifier
—32 Mbit (32 blocks) —64-bit User-programmable OTP cells
■ Performance — Absolute protection with V PEN = GND
— 75 ns Initial Access Speed (128/64/32 — Individual block locking
-Mbit densities) — Block erase/program lockout during
— 25 ns 8-word and 4-word power transitions
Asynchronous page-mode reads ■ Software
— 32-Byte Write buffer — Program and erase suspend support
—4 µs per Byte Effective
— Flash Data Integrator (FDI), Common
programming time
Flash Interface (CFI) Compatible
■ System Voltage and Power ■ Quality and Reliability
— VCC = 2.7 V to 3.6 V — Operating temperature:
— VCCQ = 2.7 V to 3.6 V -40 °C to +85 °C
— 100K Minimum erase cycles per block
— 0.13 µm ETOX™ VIII Process
■ Packaging
— 56-Lead TSOP package
— 64-Ball Intel® Easy BGA package
The Intel® Embedded Flash Memory J3 Version D (J3 v. D) provides improved mainstream performance
with enhanced security features, taking advantage of the high quality and reliability of the NOR-based Intel
0.13 µm ETOX™ VIII process technology. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit
densities, the J3 v. D device brings reliable, low-voltage capability (3 V read, program, and erase) with high
speed, low-power operation.
The J3 v. D device takes advantage of the proven manufacturing experience and is ideal for code and data
applications where high density and low cost are required, such as in networking, telecommunications,
digital set top boxes, audio recording, and digital imaging.
Intel Flash Memory components also deliver a new generation of forward-compatible software support. By
using the Common Flash Interface (CFI) and Scalable Command Set (SCS), customers can take advantage
of density upgrades and optimized write capabilities of future Intel® Flash Memory devices.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the
latest datasheet before finalizing a design.
308551- 002
Sept 2005
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Embedded Flash Memory (J3 v. D) may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © 2005, Intel Corporation. All rights reserved.
Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
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Contents
1.0 Introduction .................................................................................................................. 6
1.1 Nomenclature ........................................................................................................ 6
1.2 Acronyms............................................................................................................... 6
1.3 Conventions........................................................................................................... 6
2.0 Functional Overview ................................................................................................. 8
2.1 Block Diagram ..................................................................................................... 10
2.2 Memory Map........................................................................................................11
3.0 Package Information ............................................................................................... 12
3.1 56-Lead TSOP Package...................................................................................... 12
3.2 Easy BGA Package ............................................................................................. 13
4.0 Ballouts and Signal Descriptions ...................................................................... 15
4.1 Easy BGA Ballout (32/64/128 Mbit) ..................................................................... 15
4.2 56-Lead TSOP Package Pinout (32/64/128 Mbit) ...............................................16
4.3 Signal Descriptions .............................................................................................. 17
5.0 Maximum Ratings and Operating Conditions...............................................19
5.1 Absolute Maximum Ratings ................................................................................. 19
5.2 Operating Conditions ........................................................................................... 19
5.3 Power Up/Down................................................................................................... 20
5.3.1 Power-Up/Down Characteristics............................................................. 20
5.3.2 Power Supply Decoupling.......................................................................20
5.4 Reset ................................................................................................................... 20
6.0 Electrical Characteristics ...................................................................................... 21
6.1 DC Current Specifications ................................................................................... 21
6.2 DC Voltage specifications.................................................................................... 22
6.3 Capacitance......................................................................................................... 23
7.0 AC Characteristics ................................................................................................... 24
7.1 Read Specifications ............................................................................................. 25
7.2 Write Specifications ............................................................................................. 28
7.3 Program, Erase, Block-Lock Specifications......................................................... 30
7.4 Reset Specifications ............................................................................................31
7.5 AC Test Conditions.............................................................................................. 32
8.0 Bus Interface .............................................................................................................. 33
8.1 Bus Reads ........................................................................................................... 34
8.1.1 Asynchronous Page Mode Read ............................................................ 34
8.1.1.1 Enhanced Configuration Register (ECR)................................... 34
8.1.2 Output Disable ........................................................................................ 35
8.2 Bus Writes ........................................................................................................... 35
8.3 Standby................................................................................................................ 36
8.3.1 Reset/Power-Down ................................................................................. 36
8.4 Device Commands .............................................................................................. 36
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Revision History
Date of Revision Version Description
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1.0 Introduction
This document contains information pertaining to the Intel® Embedded Flash Memory (J3 v. D) device
features, operation, and specifications.
1.1 Nomenclature
1.2 Acronyms
1.3 Conventions
h: Hexadecimal Affix
k (noun): 1,000
M (noun): 1,000,000
Nibble 4 bits
Byte: 8 bits
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Word: 16 bits
Kword: 1,024 words
Kb: 1,024 bits
KB: 1,024 bytes
Mb: 1,048,576 bits
MB: 1,048,576 bytes
Brackets: Square brackets ([]) will be used to designate group membership or to define a
group of signals with similar function (i.e. A[21:1], SR[4,1] and D[15:0]).
00FFh: Denotes 16-bit hexadecimal numbers
00FF 00FFh: Denotes 32-bit hexadecimal numbers
DQ[15:0]: Data I/O signals
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Product Description
The Intel® Embedded Flash Memory (J3 v. D) family contains high-density memory organized in
any of the following configurations:
• 16 Mbytes or 8 Mword (128-Mbit), organized as one-hundred-twenty-eight 128-Kbyte
(131,072 bytes) erase blocks
• 8 Mbytes or 4 Mword (64-Mbit), organized as sixty-four 128-Kbyte erase blocks
• 4 Mbytes or 2 Mword (32-Mbit), organized as thirty-two 128-Kbyte erase blocks
These devices can be accessed as 8- or 16-bit words. See Figure 1, “J3 v. D Memory Block
Diagram” on page 10 for further details.
A 128-bit Protection Register has multiple uses, including unique flash device identification.
The Intel® Embedded Flash Memory (J3 v. D) device includes new security features that were not
available on the (previous) 0.25µm and 0.18µm versions of the J3 family. These new security
features prevent altering of code through different protection schemes that can be implemented,
based on user requirements.
The J3 v. D device optimized architecture and interface dramatically increases read performance by
supporting page-mode reads. This read mode is ideal for non-clock memory systems.
A Common Flash Interface (CFI) permits software algorithms to be used for entire families of
devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-
compatible software support for the specified flash device families. Flash vendors can standardize
their existing interfaces for long-term compatibility.
Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work
with all SCS-compliant flash memory devices, independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest
system/device data transfer rates and minimizes device and system-level implementation costs.
A Command User Interface (CUI) serves as the interface between the system processor and
internal operation of the device. A valid command sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM) automatically executes the algorithms and
timings necessary for block erase, program, and lock-bit configuration operations.
A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second,
independent of other blocks. Each block can be independently erased 100,000 times. Block erase
suspend mode allows system software to suspend block erase to read or program data from any
other block. Similarly, program suspend allows system software to suspend programming (byte/
word program and write-to-buffer operations) to read data or execute code from any other block
that is not being suspended.
Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming
performance. By using the Write Buffer, data is programmed in buffer increments.
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Blocks are selectively and individually lockable in-system. Individual block locking uses block
lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations.
Lock-bit configuration operations set and clear lock-bits (using the Set Block Lock-Bit and Clear
Block Lock-Bits commands).
The Status Register indicates when the WSM’s block erase, program, or lock-bit configuration
operation is finished.
The STS (STATUS) output gives an additional indicator of WSM activity by providing both a
hardware signal of status (versus software polling) and status masking (interrupt masking for
background block erase, for example). Status indication using STS minimizes both CPU overhead
and system power consumption. When configured in level mode (default mode), it acts as a RY/
BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lock-
bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is
suspended (and programming is inactive), program is suspended, or the device is in reset/power-
down mode. Additionally, the configuration command allows the STS signal to be configured to
pulse on completion of programming and/or block erases.
Three CE signals are used to enable and disable the device. A unique CE logic design (see
Table 15, “Chip Enable Truth Table” on page 33) reduces decoder logic typically required for
multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-
chip miniature card or SIMM module.
Figure 1, “J3 v. D Memory Block Diagram” on page 10 shows a device block diagram.
When the device is disabled (see Table 15, “Chip Enable Truth Table” on page 33), with CEx at
VIH and RP# at VIH, the standby mode is enabled. When RP# is at VIL, a further power-down
mode is enabled which minimizes power consumption and provides write protection during reset.
A reset time (tPHQV) is required from RP# going high until data outputs are valid. Likewise, the
device has a wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP#
at VIL, the WSM is reset and the Status Register is cleared.
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DQ0 - DQ15
Output
VCCQ Input Buffer
Buffer
Query VCC
I/O Logic
Latch/Multi pl exer
BYTE#
Write Buffe r
Register
Output
Identifier CE0
CE
Data
Register CE1
Command Logic
CE2
User
WE #
Status Interface
Register OE#
RP#
A0 - A2 Multiplexer
Data
Comparator
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0FFFFFF 7FFFFF
128-Kbyte Block 127 64-Kword Block 127
0FE0000 7F0000
07FFFFF 3FFFFF
128-Kbyte Block 63 64-Kword Block 63
07E0000 3F0000
128-Mbit
03FFFFF 1FFFFF
64-Mbit
128-Kbyte Block 31 64-Kword Block 31
03E0000 1F0000
32-Mbit
003FFFF 01FFFF
128-Kbyte Block 1 64-Kword Block 1
0020000 010000
001FFFF 00FFFF
128-Kbyte Block 0 64-Kword Block 0
0000000 000000
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Z
See Note 2 A2
See Notes 1 and 3
Pin 1
e
E See Detail B
D1 A1
D Seating
Plane
See Detail A
Detail A
Detail B
0 b
L
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Ball A1 Ball A1
Corner Corner
D S1
1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2
A A
B B
C C
D D b
E
E E
F F
G G
e
H H
A1
A2
A
Seating
Plane
Y
Note: Drawing not to scale
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Package Body Width (32 Mb, 64 Mb, 128 Mb) D 9.900 10.000 10.100 1 0.3898 0.3937 0.3976
Package Body Length (32 Mb, 64 Mb, 128 Mb) E 12.900 13.000 13.100 1 0.5079 0.5118 0.5157
Corner to Ball A1 Distance Along D (32/64/128 Mb) S1 1.400 1.500 1.600 1 0.0551 0.0591 0.0630
Corner to Ball A1 Distance Along E (32/64/128 Mb) S2 2.900 3.000 3.100 1 0.1142 0.1181 0.1220
NOTES:
1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at:
www.intel.com/design/packtech/index.htm
2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page at: www.intel.com/
design/packtech/index.htm
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Intel® Embedded Flash Memory (J3 v. D) is available in two package types. Each density of the J3
v. D is supported on both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP)
packages. Figure 5, and Figure 6 show the pinouts.
1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1
A A
A1 A6 A8 VPEN A13 VCC A18 A22 A22 A18 VCC A13 VPEN A8 A6 A1
B B
A2 VSS A9 CE0# A14 RFU A19 CE1# CE1# A19 RFU A14 CE0# A9 VSS A2
C C
A3 A7 A10 A12 A15 RFU A20 A21 A21 A20 RFU A15 A12 A10 A7 A3
D D
A4 A5 A11 RP# RFU RFU A16 A17 A17 A16 RFU RFU RP# A11 A5 A4
E E
D8 D1 D9 D3 D4 RFU D15 STS STS D15 RFU D4 D3 D9 D1 D8
F F
BYTE# D0 D10 D11 D12 RFU RFU OE# OE# RFU RFU D12 D11 D10 D0 BYTE#
G G
A23 A0 D2 VCCQ D5 D6 D14 WE# WE# D14 D6 D5 VCCQ D2 A0 A23
H H
CE2# RFU VCC VSS D13 VSS D7 RFU RFU D7 VSS D13 VSS VCC RFU CE2#
Intel® Embedded Flash Memory (28FXXXJ3D) Intel® Embedded Flash Memory (28FXXXJ3D)
Easy BGA Easy BGA
Top View- Ball side down Bottom View- Ball side up
32/64/128 Mbit 32/64/128 Mbit
NOTES:
1. Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC).
2. Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC).
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A22 1 56 RFU
CE1 2 55 WE#
A21 3 54 OE#
A20 4 53 STS
A19 5 52 DQ15
A18 6 51 DQ7
A17 7 50 DQ14
A16 8 Intel® Embedded Flash Memory 49 DQ6
VCC 9 48 GND
A15 10 (28FXXXJ3D) 47 DQ13
A14 11 46 DQ5
A13 12 56-Lead TSOP 45 DQ12
A12 13 44 DQ4
Standard Pinout
CE0 14 43 VCCQ
14 mm x 20 mm GND
VPEN 15 42
Top View DQ11
RP# 16 41
A11 17 40 DQ3
A10 18 39 DQ10
A9 19 38 DQ2
A8 20 32/64/128 Mbit 37 VCC
GND 21 36 DQ9
A7 22 35 DQ1
A6 23 34 DQ8
A5 24 33 DQ0
A4 25 32 A0
A3 26 31 BYTE#
A2 27 30 A23
A1 28 29 CE2
NOTES:
1. A22 exists on 64- and 128- densities. On 32-Mbit density this signal is a no-connect (NC).
2. A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC)
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BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode.
A0 Input This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is
turned off when BYTE# is high).
ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are
internally latched during a program cycle:
A[MAX:1] Input 32-Mbit — A[21:1]
64-Mbit — A[22:1]
128-Mbit — A[23:1]
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands
D[7:0] Input/Output during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data is
internally latched during write operations.
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.
D[15:8] Input/Output Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register
reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode
CHIP ENABLES: Activate the 32-, 64- and 128 Mbit devices’ control logic, input buffers, decoders,
and sense amplifiers. When the device is de-selected (see Table 15, “Chip Enable Truth Table” on
page 33), power reduces to standby levels.
CE[2:0] Input All timing specifications are the same for these three signals. Device selection occurs with the first
edge of CE0#, CE1#, or CE2# that enables the device. Device deselection occurs with the first
edge of CE0#, CE1#, or CE2# that disables the device (see Table 15, “Chip Enable Truth Table” on
page 33).
RESET: RP#-low resets internal automation and puts the device in power-down mode. RP#-high
RP# Input enables normal operation. Exit from reset sets the device to read array mode. When driven low,
RP# inhibits write operations which provides data protection during power transitions.
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE# Input
OE# is active low.
WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low.
WE# Input
Addresses and data are latched on the rising edge of WE#.
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to
Open Drain
STS indicate program and/or erase completion. For alternate configurations of the STATUS signal, see
Output
the Configurations command and Section 9.6, “Status Signal (STS)” on page 45. STS is to be tied
to VCCQ with a pull-up resistor.
BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0], while
D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-high places
BYTE# Input
the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the lowest-order
address bit.
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or
VPEN Input configuring lock-bits.
With VPEN ≤ VPENLK, memory contents cannot be altered.
CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC
VCC Power ≤ VLKO.
Caution: Device operation at invalid Vcc voltages should not be attempted.
VCCQ Power I/O Power Supply: Power supply for Input/Output buffers.This ball can be tied directly to VCC.
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GND Supply Ground: Ground reference for device logic voltages. Connect to system ground.
NC — No Connect: Lead is not internally connected; it may be driven or floated.
Reserved for Future Use: Balls designated as RFU are reserved by Intel for future device
RFU —
functionality and enhancement.
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NOTICE: This document contains information available at the time of its release. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet
before finalizing a design.
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Additionally, for every eight flash devices, a 4.7 µF electrolytic capacitor should be placed between
VCC and VSS at the power supply connection. This 4.7 µF capacitor should help overcome
voltage slumps caused by PCB (printed circuit board) trace inductance.
5.4 Reset
By holding the flash device in reset during power-up and power-down transitions, invalid bus
conditions may be masked. The flash device enters reset mode when RP# is driven low. In reset,
internal flash circuitry is disabled and outputs are placed in a high-impedance state. After return
from reset, a certain amount of time is required before the flash device is able to perform normal
operations. After return from reset, the flash device defaults to asynchronous page mode. If RP# is
driven low during a program or erase operation, the program or erase operation will be aborted and
the memory contents at the aborted block or address are no longer valid. See Figure 12, “AC
Waveform for Reset Operation” on page 31 for detailed information regarding reset timings.
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6.3 Capacitance
Table 9. J3 v. D Capacitance
Symbol Parameter1 Type Max Unit Condition2
NOTES:
1. sampled. not 100% tested.
2. TA = +25 °C, f = 1 MHZ
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7.0 AC Characteristics
Timing symbols used in the timing diagrams within this document conform to the following
convention:
t E L Q V
Source Signal Target State
Source State Target Signal
Address A High H
Data - Read Q Low L
Data - Write D High-Z Z
Chip Enable (CE#) E Low-Z X
Output Enable (OE#) G Valid V
Write Enable (WE#) W Invalid I
Address Valid (ADV#) V
Reset (RST#) P
Clock (CLK) C
WAIT T
Note: Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol that refers
to the aggregate initial-access delay as determined by tAVQV, tELQV, and tGLQV (whichever is
satisfied last) of the flash device. tAPA is specified in the flash device’s data sheet, and is the
address-to-data delay for subsequent page-mode reads.
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-75 -95
# Sym Parameter Density Unit Notes
Min Max Min Max
32 Mbit 75 1,2
R1 tAVAV Read/Write Cycle Time 64 Mbit 75 ns 1,2
128 Mbit 75 1,2
32 Mbit 75 1,2
R2 tAVQV Address to Output Delay 64 Mbit 75 ns 1,2
128 Mbit 75 1,2
32 Mbit 75 1,2
R3 tELQV CEX to Output Delay 64 Mbit 75 ns 1,2
128 Mbit 75 1,2
R4 tGLQV OE# to Non-Array Output Delay 25 25 ns 1,2,4
32 Mbit 150 1,2
R5 tPHQV RP# High to Output Delay 64 Mbit 180 ns 1,2
128 Mbit 210 1,2
R6 tELQX CEX to Output in Low Z 0 0 ns 1,2,5
R7 tGLQX OE# to Output in Low Z 0 0 ns 1,2,5
R8 tEHQZ CEX High to Output in High Z 25 25 ns 1,2,5
R9 tGHQZ OE# High to Output in High Z 15 15 ns 1,2,5
Output Hold from Address,
R10 tOH CEX, or OE# Change, 0 0 ns 1,2,5
Whichever Occurs First
tELFL/
R11 CEX Low to BYTE# High or Low 10 10 ns 1,2,5
tELFH
tFLQV/ All
R12 BYTE# to Output Delay 1 1 µs 1,2
tFHQV
R13 tFLQZ BYTE# to Output in High Z 1 1 µs 1,2,5
R14 tEHEL CEx High to CEx Low 0 0 ns 1,2,5
All
R15 tAPA Page Address Access Time 25 25 ns 5, 6
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0,
CE1, or CE2 that disables the device (see Table 15, “Chip Enable Truth Table” on page 33).
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
2. OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, or CE2 that enables the device (see
Table 15, “Chip Enable Truth Table” on page 33) without impact on tELQV.
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3. See Figure 13, “AC Input/Output Reference Waveform” on page 32 and Figure 14, “Transient Equivalent
Testing Load Circuit” on page 32 for testing characteristics.
4. Sampled, not 100% tested.
5. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
R1
R2
Address [A]
R3 R8
CEx [E]
R9
OE# [G]
WE# [W]
R4
R16
R7
R6 R10
Data [D/Q]
R11 R12
R13
BYT E#[F]
R5
RP# [P]
NOTES:
1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the
first edge of CE0, CE1, or CE2 that disables the device (see Table 15, “Chip Enable Truth Table” on
page 33).
2. When reading the flash array a faster tGLQV (R16) applies. For non-array reads, R4 applies (i.e., Status
Register reads, query reads, or device identifier reads).
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R1
R2
A[MAX:3] [A]
A[2:1] [A] 00 01 10 11
R3
CEx [E]
R4
OE# [G]
WE# [W]
R8
R6 R10 R10
R7 R15 R9
D[15:0] [Q] 1 2 3 4
R5
RP# [P]
NOTE: CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at
the first edge of CE0, CE1, or CE2 that disables the device (see Table 15, “Chip Enable Truth Table” on
page 33).
R1
R2
A[MAX:4] [A]
A[3:1] [A]
R3
CEx [E]
R4
OE# [G]
WE# [W]
R10
R6 R10 R8
R7 R15 R9
D[15:0] [Q] 1 2 7 8
R5
RP# [P]
BYTE#
NOTES:
1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the
first edge of CE0, CE1, or CE2 that disables the device (see Table 15, “Chip Enable Truth Table” on
page 33).
2. In this diagram, BYTE# is asserted high
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W5 W8
ADDRESS [A]
W6
CEx (WE#) [E (W)]
W2 W3 W9
WE# (CEx) [W (E)]
OE# [G]
W4 W7
DATA [D/Q] D
W13
ST S[R]
W1
RP# [P]
W11
VPEN [V]
W5 W8
Address [A]
W6
CE# [E]
W2 W3
WE# [W]
W12
OE# [G]
W4 W7
Data [D/Q] D
W1
RST#/ RP# [P]
W11
VPEN [V]
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STS (R)
P1 P2
RP# (P)
P3
Vcc
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VCCQ
Input VCCQ/2 Test Points VCCQ/2 Output
0.0
NOTE: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and
output timing ends, at VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
Device
Under Test Out
CL
VCCQ = VCCQMIN 30
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This section provides an overview of Bus operations. Basically, there are three operations you can
do with flash memory: Read, Program (Write), and Erase.The on-chip Write State Machine (WSM)
manages all erase and program algorithms. The system CPU provides control of all in-system read,
write, and erase operations through the system bus. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles. Table 14 summarizes the necessary states of each
control signal for different modes of operations.
Async., Status, Query and Identifier Reads VIH Enabled VIL VIH X DOUT High Z 4,6
NOTES:
1. See Table 15 for valid CEx Configurations.
2. OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
3. DQ refers to DQ[7:0} when BYTE# is low and DQ[15:0] if BYTE# is high.
4. Refer to DC characteristics. When VPEN ≤ VPENLK, memory contents can be read but not altered.
5. X should be VIL or VIH for the control pins and VPENLK or VPENH for VPEN. For outputs, X should be VOL or
VOH.
6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or a lock-bit
configuration algorithm. It is VOH (pulled up by an external pull up resistance ~= 10k) when the WSM is not
busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset power-
down mode.
7. See Table 18, “Command Bus Operations for J3 v. D” on page 37 for valid DIN (user commands) during a
Write operation
8. Array writes are either program or erase operations. /
The next few sections detail each of the basic flash operations and some of the advanced features
available on flash memory.
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To perform a bus read operation, CEx (refer to Table 15 on page 33) and OE# must be asserted.
CEx is the device-select control; when active, it enables the flash memory device. OE# is the data-
output control; when active, the addressed flash memory data is driven onto the I/O bus. For all
read states, WE# and RP# must be de-asserted. See Section 9.2, “Read Operations” on page 39.
After the initial access delay, the first word out of the page buffer corresponds to the initial address.
In Four-Word Page mode, address bits A[2:1] determine which word is output from the page buffer
for a x16 bus width, and A[2:0] determine which byte is output from the page buffer for a x8 bus
width. Subsequent reads from the device come from the page buffer. These reads are output on
D[15:0] for a x16 bus width and D[7:0] for a x8 bus width after a minimum delay as long as A[2:0]
(Four-Word Page mode) or A[3:0] (Eight-Word Page mode).
Data can be read from the page buffer multiple times, and in any order. In Four-Word Page mode, if
address bits A[MAX:3] (A[MAX:4] for Eight-Word Page Mode) change at any time, or if CE# is
toggled, the device will sense and load new data into the page buffer. Asynchronous Page mode is
the default read mode on power-up or reset.
To perform a Page mode read after any other operation, the Read Array command must be issued to
read from the flash array. Asynchronous Page mode reads are permitted in all blocks and are used
to access register information. During register access, only one word is loaded into the page buffer.
The ECR is shown in Table 16. 8-word page mode Command Bus-Cycle is captured in Table 17.
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Note: For forward compatibility reasons, if the 8-word Asynchronous Page mode is used on J3 v. D, a
Clear Status Register command must be executed after issuing the Set Enhanced Configuration
Register command. See Table 17 for further details.
ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS DESCRIPTION NOTES
ECR[15:14] RFU All bits should be set to 0.
• “1” = 8 Word Page mode
ECR[13]
• “0” = 4 Word Page mode
ECR[12:0] RFU All bits should be set to 0.
Erasing is performed on a block basis – all flash cells within a block are erased together. Any
information or data previously stored in the block will be lost. Erasing is typically done prior to
programming. The Block Erase command requires appropriate command data and an address
within the block to be erased. The Byte/Word Program command requires the command and
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address of the location to be written. Set Block Lock-Bit commands require the command and
block within the device to be locked. The Clear Block Lock-Bits command requires the command
and address within the device to be cleared.
The CUI does not occupy an addressable memory location. It is written when the device is enabled
and WE# is active. The address and data needed to execute a command are latched on the rising
edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 15 on
page 33). Standard microprocessor write timings are used.
8.3 Standby
CE0, CE1, and CE2 can disable the device (see Table 15 on page 33) and place it in standby mode.
This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are
placed in a high-impedance state independent of OE#. If deselected during block erase, program, or
lock-bit configuration, the WSM continues functioning, and consuming active power until the
operation completes.
8.3.1 Reset/Power-Down
RP# at V IL initiates the reset/power-down mode.
In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and
turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is
required after return from reset mode until initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The CUI is reset to read array mode and Status Register is
set to 0080h.
During Block Erase, Program, or Lock-Bit Configuration modes, RP#-low will abort the operation.
In default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until
the reset operation is complete. Memory contents being altered are no longer valid; the data may be
partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time
tPHWL is required after RP# goes to logic-high (V IH) before another command can be written.
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash memory. Automated flash memories provide
status information when accessed during Block Erase, Program, or Lock-Bit Configuration modes.
If a CPU reset occurs with no flash memory reset, proper initialization may not occur because the
flash memory may be providing status information instead of array data. Intel® Flash memories
allow proper initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
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A command sequence is issued in two consecutive write cycles - a Setup command followed by a
Confirm command. However, some commands are single-cycle commands consisting of a setup
command only. Generally, commands that alter the contents of the flash device, such as Program or
Erase, require at least two write cycles to guard against inadvertent changes to the flash device.
Flash commands fall into two categories: Basic Commands and Extended Commands. Basic
commands are recognized by all Intel® Flash devices, and are used to perform common flash
operations such as selecting the read mode, programming the array, or erasing blocks. Extended
commands are product-dependant; they are used to perform additional features such as software
block locking. Table 18 describes all applicable commands on Intel® Embedded Flash Memory (J3
v. D).
Program Enhanced Configuration Register Register Data 0060h Register Data 0004h
Registers
Program OTP Register Device Address 00C0h Register Offset Register Data
Clear Status Register Device Address 0050h --- ---
Program STS Configuration Register Device Address 00BS8h Device Address Register Data
Read Array Device Address 00FFh --- ---
Read Modes
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This section describes the operational features of flash memory. Operations are command-based,
wherein command codes are first issued to the device, then the device performs the desired
operation. All command codes are issued to the device using bus-write cycles (see Chapter 8.0,
“Bus Interface”). A complete list of available command codes can be found in Appendix A,
“Device Command Codes”.
SR status bits are set and cleared by the device. SR error bits are set by the device, but must be
cleared using the Clear Status Register command. Upon power-up or exit from reset, the Status
Register defaults to 80h. Page-mode reads are not supported in this read mode. Status Register
contents are latched on the falling edge of OE# or the first edge of CEx that enables the device.
OE# must toggle to VIH or the device must be disabled before further reads to update the Status
Register latch. The Read Status Register command functions independently of VPEN voltage.
Table 19 shows Status Register bit definitions.
Program
Erase Program Block-
Ready Erase Program /Erase
Suspend Suspend Locked Reserved
Status Error Error Voltage
Status Status Error
Error
7 6 5 4 3 2 1 0
SR5 SR4
5 Erase Command 0 0 = Program or erase operation successful.
Error Sequence 0 1 = Program error - operation aborted.
Program Error 1 0 = Erase error - operation aborted.
4 1 1 = Command sequence error - command aborted.
Error
0 = VPEN within acceptable limits during program or erase operation.
3 VPEN Error 1 = VPEN not within acceptable limits during program or erase
operation. Operation aborted.
0 = Program suspend not in effect.
2 Program Suspend Status
1 = Program suspend in effect.
0 = Block NOT locked during program or erase - operation successful.
1 Block-Locked Error
1 = Block locked during program or erase - operation aborted.
0 Reserved Not used - Reserved for future use.
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Issuing the Clear Status Register command places the device in Read Status Register mode.
Note: Care should be taken to avoid Status Register ambiguity. If a command sequence error occurs
while in an Erase Suspend condition, the Status Register will indicate a Command Sequence error
by setting SR4 and SR5. When the erase operation is resumed (and finishes), any errors that may
have occurred during the erase operation will be masked by the Command Sequence error. To
avoid this situation, clear the Status Register prior to resuming a suspended erase operation. The
Clear Status Register command functions independent of the voltage level on VPEN.
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To change the device to Read Array mode while it is programming or erasing, first issue the
Suspend command. After the operation has been suspended, issue the Read Array command. When
the program or erase operation is subsequently resumed, the device will automatically revert back
to Read Status mode.
Note: Issuing the Read Array command to the device while it is actively programming or erasing causes
subsequent reads from the device to output invalid data. Valid array data is output only after the
program or erase operation has finished.
The Read Array command functions independent of the voltage level on VPEN.
The Status Register is updated on the falling edge of CE#, or OE# when CE# is low. Status Register
contents are valid only when SR7 = 1. When WSM us active, SR7 indicates the WSM’s state and
SR[6:0] are in hig-Z state.
The Read Status Register command functions independent of the voltage level on VPEN.
The device remains in Read Device Information mode until a different read command is issued.
Also, performing a program, erase, or block-lock operation changes the device to Read Status
Register mode.
The Read Device Information command functions independent of the voltage level on VPEN.
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Issuing the CFI Query command places the device in CFI Query mode. Subsequent reads output
CFI information on DQ[15:0] (see Appendix D, “Common Flash Interface”).
The device remains in CFI Query mode until a different read command is issued, or a program or
erase operation is performed, which changes the read mode to Read Status Register mode.
The CFI Query command functions independent of the voltage level on VPEN.
Information is programmed into the flash array by issuing the appropriate command. J3 v. D
supports two different programming methods: Byte/Word and Write-to-Buffer. Table 24 shows the
two-cycle command sequences used for each method.
Note: All programming operations require the addressed block to be unlocked, and a valid VPEN voltage
applied throughout the programming operation. Otherwise, the programming operation will abort,
setting the appropriate Status Register error bit(s).
During programming, STS and the Status Register indicate a busy status (SR7 = 0). Upon
completion, STS and the Status Register indicate a ready status (SR7 = 1). The Status Register
should be checked for any errors (SR4), then cleared.
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Note: Issuing the Read Array command to the device while it is actively programming causes subsequent
reads from the device to output invalid data. Valid array data is output only after the program
operation has finished.
Standby power levels are not be realized until the programming operation has finished. Also,
asserting RP# aborts the programming operation, and array contents at the addressed location are
indeterminate. The addressed block should be erased, and the data re-programmed. If a Single-
Word/Byte program is attempted when the corresponding block lock-bit is set, SR1 and SR4 will
be set.
Note: Optimal performance and power consumption is realized only by aligning the start address on 32-
word boundaries (i.e., A[4:0] = 0b00000). Crossing a 32-word boundary during a buffered
programming operation can cause programming time to double.
To perform a buffered programming operation, first issue the Buffered Program setup command at
the desired starting address. The read mode of the device/addressed partition is automatically
changed to Read Status Register mode.
Polling SR7 determines write-buffer availability (0 = not available, 1 = available). If the write
buffer is not available, re-issue the setup command and check SR7; repeat until SR7 = 1.
Next, issue the word count at the desired starting address. The word count represents the total
number of words to be written into the write buffer, minus one. This value can range from 00h (one
word) to a maximum of 1Fh (32 words). Exceeding the allowable range causes an abort.
Following the word count, the write buffer is filled with user-data. Subsequent bus-write cycles
provide addresses and data, up to the word count. All user-data addresses must lie between
<starting address> and <starting address + word count>, otherwise the WSM continues to run as
normal but, user may advertently change the content in unexpected address locations.
Note: User-data is programmed into the flash array at the address issued when filling the write buffer.
After all user-data is written into the write buffer, issue the confirm command. If a command other
than the confirm command is issued to the device, a command sequence error occurs and the
operation aborts.
After issuing the confirm command, write-buffer contents are programmed into the flash memory
array. The Status Register indicates a busy status (SR7 = 0) during array programming.
Note: Issuing the Read Array command to the device while it is actively programming or erasing causes
subsequent reads from the device to output invalid data. Valid array data is output only after the
program or erase operation has finished.
Upon completion of array programming, the Status Register indicates ready (SR7 = 1). A full
Status Register check should be performed to check for any programming errors, then cleared by
using the Clear Status Register command.
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Additional buffered programming operations can be initiated by issuing another setup command,
and repeating the buffered programming bus-cycle sequence. However, any errors in the Status
Register must first be cleared before another buffered programming operation can be initiated.
To perform a block-erase operation, issue the Block Erase command sequence at the desired block
address. Table 25 shows the two-cycle Block Erase command sequence.
Note: A block-erase operation requires the addressed block to be unlocked, and a valid voltage applied to
VPEN throughout the block-erase operation. Otherwise, the operation will abort, setting the
appropriate Status Register error bit(s).
The Erase Confirm command latches the address of the block to be erased. The addressed block is
preconditioned (programmed to all zeros), erased, and then verified. The read mode of the device is
automatically changed to Read Status Register mode, and remains in effect until another read-mode
command is issued.
During a block-erase operation, STS and the Status Register indicates a busy status (SR7 = 0).
Upon completion, STS and the Status Register indicates a ready status (SR7 = 1). The Status
Register should be checked for any errors, then cleared. If any errors did occur, subsequent erase
commands to the device are ignored unless the Status Register is cleared.
The only valid commands during a block erase operation are Read Array, Read Device
Information, CFI Query, and Erase Suspend. After the block-erase operation has completed, any
valid command can be issued.
Note: Issuing the Read Array command to the device while it is actively erasing causes subsequent reads
from the device to output invalid data. Valid array data is output only after the block-erase
operation has finished.
Standby power levels are not be realized until the block-erase operation has finished. Also,
asserting RP# aborts the block-erase operation, and array contents at the addressed location are
indeterminate. The addressed block should be erased before programming within the block is
attempted.
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Note: All erase and programming operations require the addressed block to remain unlocked with a valid
voltage applied to VPEN throughout the suspend operation. Otherwise, the block-erase or
programming operation will abort, setting the appropriate Status Register error bit(s). Also,
asserting RP# aborts suspended block-erase and programming operations, rendering array contents
at the addressed location(s) indeterminate.
To suspend an on-going erase or program operation, issue the Suspend command to any device
address. The program or erase operation suspends at pre-determined points during the operation
after a delay of tSUSP. Suspend is achieved when STS (in RY/BY# mode) goes high, SR[7,6] = 1
(erase-suspend) or SR[7,2] = 1 (program-suspend).
Note: Issuing the Suspend command does not change the read mode of the device. The device will be in
Read Status Register mode from when the erase or program command was first issued, unless the
read mode was changed prior to issuing the Suspend command.
Not all commands are allowed when the device is suspended. Table 27 shows which device
commands are allowed during Program Suspend or Erase Suspend.
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During Suspend, array-read operations are not allowed in blocks being erased or programmed.
To resume a suspended program or erase operation, issue the Resume command to any device
address. The read mode of the device is automatically changed to Read Status Register. The
operation continues where it left off, STS (in RY/BY# mode) goes low, and the respective Status
Register bits are cleared.
NOTES:
1. In case of 256 Mb device (2x128), the command sequence must be repeated for each die at its base address
2. In case of 256 Mb device (2x128), keep the second cycle to the same address. (ie. Do not toggle A24 for the
second cycle)
To reconfigure the STATUS (STS) signal to other modes, the Configuration command is given
followed by the desired configuration code. The three alternate configurations are all pulse mode
for use as a system interrupt as described in the following paragraphs. For these configurations, bit
0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse.
Supplying the 0x00 configuration code with the Configuration command resets the STS signal to
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the default RY/BY# level mode. The Configuration command may only be given when the device
is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in
SR.4 and SR.5 being set.
Note: STS Pulse mode is not supported in the Clear Lock Bits and Set Lock Bit commands
Pulse on Pulse on
Program Erase
Reserved
Complete Complete
(1) (1)
00 = default, level mode; Controls HOLD to a memory controller to prevent accessing a flash
device ready indication memory subsystem while any flash device's WSM is busy.
Generates a system interrupt pulse when any flash device in an array
01 = pulse on Erase Complete has completed a block erase. Helpful for reformatting blocks after file
system free space reclamation or “cleanup.”
10 = pulse on Program Complete Not supported on this device.
Generates system interrupts to trigger servicing of flash arrays when
11 = pulse on Erase or Program either erase or program operations are completed, when a common
Complete
interrupt service routine is desired.
NOTES:
1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 250 ns.
2. An invalid configuration code will result in both SR4 and SR5 being set.
3. Reserved bits are invalid should be ignored.
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All locked blocks are unlocked simultaneously by issuing the Clear Block Lock Bits command
sequence to any device address. Locked blocks cannot be erased or programmed. Table 30
summarizes the command bus-cycles.
Set Block Lock Bit Block Address 0060h Block Address 0001h
Clear Block Lock Bits Device Address 0060h Device Address 00D0h
After issuing the Set Block Lock Bit setup command or Clear Block Lock Bits setup command, the
device’s read mode is automatically changed to Read Status Register mode. After issuing the
confirm command, completion of the operation is indicated by STS (in RY/BY# mode) going high
and SR7 = 1.
Blocks cannot be locked or unlocked while programming or erasing, or while the device is
suspended. Reliable block lock and unlock operations occur only when VCC and VPEN are valid.
When VPEN ≤ V PENLK, block lock-bits cannot be changed.
When the set lock-bit operation is complete, SR4 should be checked for any error. When the clear
lock-bit operation is complete, SR5 should be checked for any error. Errors bits must be cleared
using the Clear Status Register command.
Block lock-bit status can be determined by first issuing the Read Device Information command,
and then reading from <block base address> + 02h. DQ0 indicates the lock status of the addressed
block (0 = unlocked, 1 = locked).
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0x88
64-bit Segment
(User-Programmable)
0x85
128-Bit Protection Register 0
0x84
64-bit Segment
(Factory-Programmed)
0x81
Lock Register 0
0x80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOTE: A0 is not used in x16 mode when accessing the protection register map. See Table 31 for x16
addressing. If x8 mode A0 is used, see Table 32 for x8 addressing.
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LOCK Both 1 0 0 0 0 0 0 0
0 Factory 1 0 0 0 0 0 0 1
1 Factory 1 0 0 0 0 0 1 0
2 Factory 1 0 0 0 0 0 1 1
3 Factory 1 0 0 0 0 1 0 0
4 User 1 0 0 0 0 1 0 1
5 User 1 0 0 0 0 1 1 0
6 User 1 0 0 0 0 1 1 1
7 User 1 0 0 0 1 0 0 0
NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register
(i.e., A[MAX:9] = 0.)
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LOCK Both 1 0 0 0 0 0 0 0 0
LOCK Both 1 0 0 0 0 0 0 0 1
0 Factory 1 0 0 0 0 0 0 1 0
1 Factory 1 0 0 0 0 0 0 1 1
2 Factory 1 0 0 0 0 0 1 0 0
3 Factory 1 0 0 0 0 0 1 0 1
4 Factory 1 0 0 0 0 0 1 1 0
5 Factory 1 0 0 0 0 0 1 1 1
6 Factory 1 0 0 0 0 1 0 0 0
7 Factory 1 0 0 0 0 1 0 0 1
8 User 1 0 0 0 0 1 0 1 0
9 User 1 0 0 0 0 1 0 1 1
A User 1 0 0 0 0 1 1 0 0
B User 1 0 0 0 0 1 1 0 1
C User 1 0 0 0 0 1 1 1 0
D User 1 0 0 0 0 1 1 1 1
E User 1 0 0 0 1 0 0 0 0
F User 1 0 0 0 1 0 0 0 1
NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register,
i.e., A[MAX:9] = 0.
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Program Enhanced Configuration Register Register Data 0060h Register Data 0004h
Registers
Program OTP Register Device Address 00C0h Register Offset Register Data
Clear Status Register Device Address 0050h --- ---
Program STS Configuration Register Device Address 00B8h --- ---
Read Array Device Address 00FFh --- ---
Read Modes
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Appendix B J3 v. D ID Codes
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Start
Setup
- Write 0xE8
- Block Address
No
SR7 = 1?
Yes
Word Count
- Address = block address
- Data = word count minus 1
(Valid range = 0x00 to0x1F)
Load Buffer
- Fill write buffer up to word count
- Address = within buffer range
- Data = user data
Confirm
- Write 0xD0
- Block address
Read Status
Register (SR)
No
SR7 = 1?
Yes
End
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Start
Command Cycle
- Issue Status Register Command
- Address = any dev ice address
- Data = 0x70
Data Cycle
- Read Status Register SR[7:0]
No
SR7 = '1'
Y es
No
Y es Program Suspend
SR2 = '1'
See Suspend/Resume Flowchart
No
Y es Y es Error
SR5 = '1' SR4 = '1'
Command Sequence
No No
Error
Erase Failure
Y es Error
SR4 = '1'
Program Failure
No
- Set by WSM
- Reset by user
- See Clear Status
Register Y es Error
Command SR3 = '1'
V PEN < VPENLK
No
Y es Error
SR1 = '1'
Block Locked
No
End
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Start Bus
Command Comments
Operation
Check SR.7
Read Status
Standby 1 = WSM Ready
Register 0 = WSM Busy
1. Toggling OE# (low to high to low) updates the status register. This
0 can be done in place of issuing the Read Status Register command.
SR.7 = Repeat for subsequent programming operations.
Byte/Word
Program Complete
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Bus
Start Command Comments
Operation
Check SR.7
Standby 1 - WSM Ready
Read Status Register
0 = WSM Busy
Check SR.6
Standby 1 = Programming Suspended
0 0 = Programming Completed
SR.7 =
Data = FFH
Write Read Array
Addr = X
1
Read array locations other
0 Read
than that being programmed.
SR.2 = Programming Completed
Program Data = D0H
Write
Resume Addr = X
1
Write FFH
No
Done Reading
Yes
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Bus
Start Command Comments
Operation
Data = 20H
Write Erase Block
Addr = Block Address
Erase Data = D0H
Write (Note 1)
Issue Single Block Erase Confirm Addr = Block Address
Command 20H, Block Status register data
Address With the device enabled,
Read
OE# low updates SR
Addr = X
Check SR.7
Standby 1 = WSM Ready
Write Confirm D0H 0 = WSM Busy
Block Address
1. The Erase Confirm byte must follow Erase Setup.
This device does not support erase queuing. Please see
Application note AP-646 For software erase queuing
compatibility.
Read
Status Register Full status check can be done after all erase and write
sequences complete. Write FFH after the last operation to
No reset the device to read array mode.
Suspend
Erase Loop
0 Yes
SR.7 = Suspend Erase
Full Status
Check if Desired
Erase Flash
Block(s) Complete
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Bus
Start Command Comments
Operation
Data = B0H
Write Erase Suspend
Addr = X
Write B0H
Status Register Data
Read
Addr = X
Check SR.7
Standby 1 - WSM Ready
Read Status Register
0 = WSM Busy
Check SR.6
Standby 1 = Block Erase Suspended
0 0 = Block Erase Completed
SR.7 =
Data = D0H
Write Erase Resume
Addr = X
1
0
SR.6 = Block Erase Completed
1
Read Program
Read or Program?
Done?
Yes
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Start Bus
Command Comments
Operation
Check SR.3
1 Standby 1 = Programming Voltage Error
Detect
SR.3 = Voltage Range Error
Check SR.4, 5
0 Standby Both 1 = Command Sequence
Error
1
Command Sequence
SR.4,5 = Standby
Check SR.4
Error 1 = Set Lock-Bit Error
0
SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register
1 command, in cases where multiple lock-bits are set before full status is
SR.4 = Set Lock-Bit Error checked.
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Start Bus
Command Comments
Operation
0 Write FFH after the clear lock-bits operation to place device in read
SR.7 = array mode.
1
Full Status
Check if Desired
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Protection Program
Write Data = C0H
Write C0H Setup
(Protection Reg.
Data = Data to Program
Program Setup) Write Protection Program
Addr = Location to Program
Check SR.7
Standby 1 = WSM Ready
Read Status Register 0 = WSM Busy
Program Complete
1 0 1 Register
0,1 Standby Locked:
Protection Register Aborted
SR.1, SR.4 =
Programming Error
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
1,1 Attempted Program to
SR.1, SR.4 = Locked Register - SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases of multiple protection register program operations before full status is
Aborted checked.
If an error is detected, clear the status register before attempting retry or other
Program Successful error recovery.
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This appendix defines the data structure or “database” returned by the Common Flash Interface
(CFI) Query command. System software should parse this structure to gain critical information
such as block size, density, x8/x16, and electrical specifications. Once this information has been
obtained, the software will know which command sets to use to enable flash writes, block erases,
and otherwise control the flash component. The Query is part of an overall specification for
multiple command set and control interface descriptions called Common Flash Interface, or CFI.
Query data are always presented on the lowest-order data outputs (D[7:0]) only. The numerical
offset value is the address relative to the maximum bus width supported by the device. On this
family of devices, the Query table device starting address is a 10h, which is a word address for x16
devices.
For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R” in ASCII,
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H
data on upper bytes. Thus, the device outputs ASCII “Q” in the low byte (D[7:0]) and 00h in the
high byte (D[15:8]).
At Query addresses containing two or more bytes of information, the least significant data byte is
presented at the lower address, and the most significant data byte is presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal notation, so the
“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always
“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is
shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
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Table 35. Summary of Query Structure Output as a Function of Device and Mode
Query data with maximum Query data with byte
Device Query start location in device bus width addressing addressing
Type/ maximum device bus
Mode width addresses Hex Hex ASCII Hex Hex ASCII
Offset Code Value Offset Code Value
x16 device 10h 10: 0051 “Q” 20: 51 “Q”
x16 mode 11: 0052 “R” 21: 00 “Null”
12: 0059 “Y” 22: 52 “R”
x16 device 20: 51 “Q”
x8 mode N/A(1) N/A(1) 21: 51 “Q”
22: 52 “R”
NOTE:
1. The system must drive the lowest order addresses to access all the device's array data when the device is
configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the
system, is "Not Applicable" for x8-configured devices.
Table 36. Example of Query Structure Output of a x16- and x8-Capable Device
Word Addressing Byte Addressing
Offset Hex Code Value Offset Hex Code Value
A15–A0 D15–D0 A7–A 0 D7–D0
0010h 0051 “Q” 20h 51 “Q”
0011h 0052 “R” 21h 51 “Q”
0012h 0059 “Y” 22h 52 “R”
0013h P_IDLO PrVendor 23h 52 “R”
0014h P_IDHI ID # 24h 59 “Y”
0015h PLO PrVendor 25h 59 “Y”
0016h PHI TblAdr 26h P_IDLO PrVendor
0017h A_IDLO AltVendor 27h P_IDLO ID #
0018h A_IDHI ID # 28h P_IDHI ID #
... ... ... ... ... ...
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P C2 8 F 3 2 0 J 3 D - 7 5
Package
Access Speed
TE= 56-Lead TSOP (J3C, 803)
75 ns
JS = Pb-Free 56-TSOP
RC = 64-Ball Easy BGA
D = Intel® 0.13
PC = 64-Ball Pb-Free Easy BGA micron lithography
Voltage (Vcc/VPEN)
Product line designator 3 = 3 V/3 V
For all Intel® Flash Products
Product Family
J = Intel® Embedded Flash Memory
Device Density
128 = x8/x16 (128 Mbit)
640 = x8/x16 (64 Mbit)
320 = x8/x16 (32 Mbit)
Table 45. Order Information: Intel® Embedded Flash Memory (J3 v. D) Family
56-Lead TSOP 64-Ball Easy BGA
TE28F128J3D-75 RC28F128J3D-75
TE28F640J3D-75 RC28F640J3D-75
TE28F320J3D-75 RC28F320J3D-75
JS28F128J3D-75 PC28F128J3D-75
JS28F640J3D-75 PC28F640J3D-75
JS28F320J3D-75 PC28F320J3D-75
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