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Intel® Embedded Flash Memory (J3 v. D)


(32, 64, and 128 Mbit)

Datasheet
Product Features
■ Architecture ■ Security
— High-density symmetrical 128-Kbyte — Enhanced security options for code
blocks protection
—128 Mbit (128 blocks) — 128-bit Protection Register
—64 Mbit (64 blocks) —64-bit Unique device identifier
—32 Mbit (32 blocks) —64-bit User-programmable OTP cells
■ Performance — Absolute protection with V PEN = GND
— 75 ns Initial Access Speed (128/64/32 — Individual block locking
-Mbit densities) — Block erase/program lockout during
— 25 ns 8-word and 4-word power transitions
Asynchronous page-mode reads ■ Software
— 32-Byte Write buffer — Program and erase suspend support
—4 µs per Byte Effective
— Flash Data Integrator (FDI), Common
programming time
Flash Interface (CFI) Compatible
■ System Voltage and Power ■ Quality and Reliability
— VCC = 2.7 V to 3.6 V — Operating temperature:
— VCCQ = 2.7 V to 3.6 V -40 °C to +85 °C
— 100K Minimum erase cycles per block
— 0.13 µm ETOX™ VIII Process

■ Packaging
— 56-Lead TSOP package
— 64-Ball Intel® Easy BGA package

The Intel® Embedded Flash Memory J3 Version D (J3 v. D) provides improved mainstream performance
with enhanced security features, taking advantage of the high quality and reliability of the NOR-based Intel
0.13 µm ETOX™ VIII process technology. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit
densities, the J3 v. D device brings reliable, low-voltage capability (3 V read, program, and erase) with high
speed, low-power operation.

The J3 v. D device takes advantage of the proven manufacturing experience and is ideal for code and data
applications where high density and low cost are required, such as in networking, telecommunications,
digital set top boxes, audio recording, and digital imaging.

Intel Flash Memory components also deliver a new generation of forward-compatible software support. By
using the Common Flash Interface (CFI) and Scalable Command Set (SCS), customers can take advantage
of density upgrades and optimized write capabilities of future Intel® Flash Memory devices.

Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the
latest datasheet before finalizing a design.

308551- 002
Sept 2005
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Embedded Flash Memory (J3 v. D) may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © 2005, Intel Corporation. All rights reserved.
Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.

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Contents
1.0 Introduction .................................................................................................................. 6
1.1 Nomenclature ........................................................................................................ 6
1.2 Acronyms............................................................................................................... 6
1.3 Conventions........................................................................................................... 6
2.0 Functional Overview ................................................................................................. 8
2.1 Block Diagram ..................................................................................................... 10
2.2 Memory Map........................................................................................................11
3.0 Package Information ............................................................................................... 12
3.1 56-Lead TSOP Package...................................................................................... 12
3.2 Easy BGA Package ............................................................................................. 13
4.0 Ballouts and Signal Descriptions ...................................................................... 15
4.1 Easy BGA Ballout (32/64/128 Mbit) ..................................................................... 15
4.2 56-Lead TSOP Package Pinout (32/64/128 Mbit) ...............................................16
4.3 Signal Descriptions .............................................................................................. 17
5.0 Maximum Ratings and Operating Conditions...............................................19
5.1 Absolute Maximum Ratings ................................................................................. 19
5.2 Operating Conditions ........................................................................................... 19
5.3 Power Up/Down................................................................................................... 20
5.3.1 Power-Up/Down Characteristics............................................................. 20
5.3.2 Power Supply Decoupling.......................................................................20
5.4 Reset ................................................................................................................... 20
6.0 Electrical Characteristics ...................................................................................... 21
6.1 DC Current Specifications ................................................................................... 21
6.2 DC Voltage specifications.................................................................................... 22
6.3 Capacitance......................................................................................................... 23
7.0 AC Characteristics ................................................................................................... 24
7.1 Read Specifications ............................................................................................. 25
7.2 Write Specifications ............................................................................................. 28
7.3 Program, Erase, Block-Lock Specifications......................................................... 30
7.4 Reset Specifications ............................................................................................31
7.5 AC Test Conditions.............................................................................................. 32
8.0 Bus Interface .............................................................................................................. 33
8.1 Bus Reads ........................................................................................................... 34
8.1.1 Asynchronous Page Mode Read ............................................................ 34
8.1.1.1 Enhanced Configuration Register (ECR)................................... 34
8.1.2 Output Disable ........................................................................................ 35
8.2 Bus Writes ........................................................................................................... 35
8.3 Standby................................................................................................................ 36
8.3.1 Reset/Power-Down ................................................................................. 36
8.4 Device Commands .............................................................................................. 36

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9.0 Flash Operations ...................................................................................................... 38


9.1 Status Register .................................................................................................... 38
9.1.1 Clearing the Status Register................................................................... 39
9.2 Read Operations ................................................................................................. 39
9.2.1 Read Array ............................................................................................. 39
9.2.2 Read Status Register ............................................................................. 40
9.2.3 Read Device Information ........................................................................ 40
9.2.4 CFI Query ............................................................................................... 41
9.3 Programming Operations .................................................................................... 41
9.3.1 Single-Word/Byte Programming ............................................................. 41
9.3.2 Buffered Programming ........................................................................... 42
9.4 Block Erase Operations....................................................................................... 43
9.5 Suspend and Resume ......................................................................................... 44
9.6 Status Signal (STS) ............................................................................................. 45
9.7 Security and Protection ....................................................................................... 46
9.7.1 Normal Block Locking............................................................................. 46
9.7.2 Configurable Block Locking .................................................................... 47
9.7.3 OTP Protection Registers....................................................................... 47
9.7.4 Reading the OTP Protection Register .................................................... 48
9.7.5 Programming the OTP Protection Register ............................................ 48
9.7.6 Locking the OTP Protection Register ..................................................... 48
9.7.7 VPP/ VPEN Protection ........................................................................... 50
Appendix A Device Command Codes ................................................................................. 51
Appendix B J3 v. D ID Codes .................................................................................................. 52
Appendix C Flow Charts ........................................................................................................... 53
C.1 Write to Buffer...................................................................................................53
C.2 Status Register .................................................................................................54
C.3 Byte/Word Programming ..................................................................................55
C.4 Program Suspend/Resume ..............................................................................56
C.5 Block Erase.......................................................................................................57
C.6 Block Erase Suspend/Resume .........................................................................58
C.7 Block Locking....................................................................................................59
C.8 Unlock Block .....................................................................................................60
C.9 OTP Protection Register Programming ............................................................61
Appendix D Common Flash Interface ................................................................................. 62
D.2 Query Structure Overview ................................................................................63
D.3 Block Status Register .......................................................................................64
D.4 CFI Query Identification String..........................................................................64
D.5 System Interface Information............................................................................65
D.6 Device Geometry Definition ..............................................................................66
D.7 Primary-Vendor Specific Extended Query Table ..............................................67
Appendix E Additional Information ...................................................................................... 69
Appendix F Ordering Information ......................................................................................... 70

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Revision History
Date of Revision Version Description

July 2005 001 Initial release


-Marketing name was changed from 28FxxxJ3 to J3 v. D
- Table 18 “Command Bus Operations for J3 v. D” on page 37 was updated
- Section 9.2.2, “Read Status Register” on page 40
September 2005 002
- Section 9.3.2, “Buffered Programming” on page 42
- Table 27 “Valid Commands During Suspend” on page 44
- Table 28 “STS Configuration Register” on page 45 was added

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1.0 Introduction

This document contains information pertaining to the Intel® Embedded Flash Memory (J3 v. D) device
features, operation, and specifications.

1.1 Nomenclature

AMIN: All Densities AMIN = A0 for x8


All Densities AMIN = A1 for x16
AMAX: 32 Mbit AMAX = A21
64 Mbit AMAX = A22
128 Mbit AMAX = A23
Block: A group of flash cells that share common erase circuitry and erase simultaneously
Clear: Indicates a logic zero (0)
Program: To write data to the flash array
Set: Indicates a logic one (1)
VPEN: Refers to a signal or package connection name
V PEN: Refers to timing or voltage levels

1.2 Acronyms

CUI: Command User Interface


OTP: One Time Programmable
PLR: Protection Lock Register
PR: Protection Register
PRD: Protection Register Data
RFU: Reserved for Future Use
SR: Status Register
SRD: Status Register Data
WSM: Write State Machine
ECR: Enhanced Configuration Register

1.3 Conventions
h: Hexadecimal Affix
k (noun): 1,000
M (noun): 1,000,000
Nibble 4 bits
Byte: 8 bits

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Word: 16 bits
Kword: 1,024 words
Kb: 1,024 bits
KB: 1,024 bytes
Mb: 1,048,576 bits
MB: 1,048,576 bytes
Brackets: Square brackets ([]) will be used to designate group membership or to define a
group of signals with similar function (i.e. A[21:1], SR[4,1] and D[15:0]).
00FFh: Denotes 16-bit hexadecimal numbers
00FF 00FFh: Denotes 32-bit hexadecimal numbers
DQ[15:0]: Data I/O signals

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2.0 Functional Overview

Product Description
The Intel® Embedded Flash Memory (J3 v. D) family contains high-density memory organized in
any of the following configurations:
• 16 Mbytes or 8 Mword (128-Mbit), organized as one-hundred-twenty-eight 128-Kbyte
(131,072 bytes) erase blocks
• 8 Mbytes or 4 Mword (64-Mbit), organized as sixty-four 128-Kbyte erase blocks
• 4 Mbytes or 2 Mword (32-Mbit), organized as thirty-two 128-Kbyte erase blocks
These devices can be accessed as 8- or 16-bit words. See Figure 1, “J3 v. D Memory Block
Diagram” on page 10 for further details.

A 128-bit Protection Register has multiple uses, including unique flash device identification.

The Intel® Embedded Flash Memory (J3 v. D) device includes new security features that were not
available on the (previous) 0.25µm and 0.18µm versions of the J3 family. These new security
features prevent altering of code through different protection schemes that can be implemented,
based on user requirements.

The J3 v. D device optimized architecture and interface dramatically increases read performance by
supporting page-mode reads. This read mode is ideal for non-clock memory systems.

A Common Flash Interface (CFI) permits software algorithms to be used for entire families of
devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-
compatible software support for the specified flash device families. Flash vendors can standardize
their existing interfaces for long-term compatibility.

Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work
with all SCS-compliant flash memory devices, independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest
system/device data transfer rates and minimizes device and system-level implementation costs.

A Command User Interface (CUI) serves as the interface between the system processor and
internal operation of the device. A valid command sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM) automatically executes the algorithms and
timings necessary for block erase, program, and lock-bit configuration operations.

A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second,
independent of other blocks. Each block can be independently erased 100,000 times. Block erase
suspend mode allows system software to suspend block erase to read or program data from any
other block. Similarly, program suspend allows system software to suspend programming (byte/
word program and write-to-buffer operations) to read data or execute code from any other block
that is not being suspended.

Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming
performance. By using the Write Buffer, data is programmed in buffer increments.

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Blocks are selectively and individually lockable in-system. Individual block locking uses block
lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations.
Lock-bit configuration operations set and clear lock-bits (using the Set Block Lock-Bit and Clear
Block Lock-Bits commands).

The Status Register indicates when the WSM’s block erase, program, or lock-bit configuration
operation is finished.

The STS (STATUS) output gives an additional indicator of WSM activity by providing both a
hardware signal of status (versus software polling) and status masking (interrupt masking for
background block erase, for example). Status indication using STS minimizes both CPU overhead
and system power consumption. When configured in level mode (default mode), it acts as a RY/
BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lock-
bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is
suspended (and programming is inactive), program is suspended, or the device is in reset/power-
down mode. Additionally, the configuration command allows the STS signal to be configured to
pulse on completion of programming and/or block erases.

Three CE signals are used to enable and disable the device. A unique CE logic design (see
Table 15, “Chip Enable Truth Table” on page 33) reduces decoder logic typically required for
multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-
chip miniature card or SIMM module.

The BYTE# signal allows either x8 or x16 read/writes to the device:


• BYTE#-low enables 8-bit mode; address A0 selects between the low byte and high byte.
• BYTE#-high enables16-bit operation; address A1 becomes the lowest order address and
address A0 is not used (don’t care).

Figure 1, “J3 v. D Memory Block Diagram” on page 10 shows a device block diagram.

When the device is disabled (see Table 15, “Chip Enable Truth Table” on page 33), with CEx at
VIH and RP# at VIH, the standby mode is enabled. When RP# is at VIL, a further power-down
mode is enabled which minimizes power consumption and provides write protection during reset.
A reset time (tPHQV) is required from RP# going high until data outputs are valid. Likewise, the
device has a wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP#
at VIL, the WSM is reset and the Status Register is cleared.

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2.1 Block Diagram

Figure 1. J3 v. D Memory Block Diagram

DQ0 - DQ15

Output
VCCQ Input Buffer
Buffer

Query VCC
I/O Logic

Latch/Multi pl exer
BYTE#

Write Buffe r
Register
Output
Identifier CE0
CE

Data
Register CE1
Command Logic
CE2
User
WE #
Status Interface
Register OE#
RP#

A0 - A2 Multiplexer
Data
Comparator

32-Mbit: A0 - A21 Y-Decoder Y-Gating STS


64-Mbit: A0 - A22 Input Buffer Write State
128-Mbit: A0 - A23 32-Mbit: Thirty-two Program/Erase V PEN
64-Mbit: Sixty-four Machine
Voltage Switch
128-Mbit: One-hundred
Address
twenty -eight VCC
Latch X-Decoder
GND
Address
Counter 128-Kbyte Blocks

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2.2 Memory Map

Figure 2. J3 v. D Memory Map

A [23-0]:128 Mbit A [23-1]: 128 Mbit


A [22-0]: 64 Mbit A [22-1]: 64 Mbit
A [21-0]: 32 Mbit A [21-1]: 32 Mbit

0FFFFFF 7FFFFF
128-Kbyte Block 127 64-Kword Block 127
0FE0000 7F0000

07FFFFF 3FFFFF
128-Kbyte Block 63 64-Kword Block 63
07E0000 3F0000

128-Mbit
03FFFFF 1FFFFF

64-Mbit
128-Kbyte Block 31 64-Kword Block 31
03E0000 1F0000

32-Mbit
003FFFF 01FFFF
128-Kbyte Block 1 64-Kword Block 1
0020000 010000
001FFFF 00FFFF
128-Kbyte Block 0 64-Kword Block 0
0000000 000000

Byte-Wide (x8) Mode Word Wide (x16) Mode

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3.0 Package Information

3.1 56-Lead TSOP Package


Figure 3. 56-Lead TSOP Package Mechanical

Z
See Note 2 A2
See Notes 1 and 3
Pin 1
e

E See Detail B

D1 A1
D Seating
Plane

See Detail A

Detail A
Detail B

0 b
L

Table 1. 56-Lead TSOP Dimension Table (Sheet 1 of 2)


Millimeters Inches

Sym Min Nom Max Min Nom Max

Package Height A 1.200 0.047


Standoff A1 0.050 0.002
Package Body Thickness A2 0.965 0.995 1.025 0.038 0.039 0.040
Lead Width b 0.100 0.150 0.200 0.004 0.006 0.008
Lead Thickness c 0.100 0.150 0.200 0.004 0.006 0.008
Package Body Length D1 18.200 18.400 18.600 0.717 0.724 0.732
Package Body Width E 13.800 14.000 14.200 0.543 0.551 0.559
Lead Pitch e 0.500 0.0197
Terminal Dimension D 19.800 20.00 20.200 0.780 0.787 0.795
Lead Tip Length L 0.500 0.600 0.700 0.020 0.024 0.028
Lead Count N 56 56

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Table 1. 56-Lead TSOP Dimension Table (Sheet 2 of 2)


Millimeters Inches

Sym Min Nom Max Min Nom Max

Lead Tip Angle θ 0° 3° 5° 0° 3° 5°


Seating Plane Coplanarity Y 0.100 0.004
Lead to Package Offset Z 0.150 0.250 0.350 0.006 0.010 0.014

3.2 Easy BGA Package

Figure 4. Easy BGA Mechanical Specifications

Ball A1 Ball A1
Corner Corner
D S1

1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2

A A

B B

C C

D D b
E
E E

F F

G G
e
H H

Top View - Ball side down Bottom View - Ball Side Up

A1

A2
A
Seating

Plane
Y
Note: Drawing not to scale

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Table 2. Easy BGA Package Dimensions Table


Millimeters Inches

Symbol Min Nom Max Notes Min Nom Max

Package Height A 1.200 0.0472


Ball Height A1 0.250 0.0098
Package Body Thickness A2 0.780 0.0307

Ball (Lead) Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209

Package Body Width (32 Mb, 64 Mb, 128 Mb) D 9.900 10.000 10.100 1 0.3898 0.3937 0.3976
Package Body Length (32 Mb, 64 Mb, 128 Mb) E 12.900 13.000 13.100 1 0.5079 0.5118 0.5157

Pitch [e] 1.000 0.0394


Ball (Lead) Count N 64 64

Seating Plane Coplanarity Y 0.100 0.0039

Corner to Ball A1 Distance Along D (32/64/128 Mb) S1 1.400 1.500 1.600 1 0.0551 0.0591 0.0630
Corner to Ball A1 Distance Along E (32/64/128 Mb) S2 2.900 3.000 3.100 1 0.1142 0.1181 0.1220

NOTES:
1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at:
www.intel.com/design/packtech/index.htm
2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page at: www.intel.com/
design/packtech/index.htm

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4.0 Ballouts and Signal Descriptions

Intel® Embedded Flash Memory (J3 v. D) is available in two package types. Each density of the J3
v. D is supported on both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP)
packages. Figure 5, and Figure 6 show the pinouts.

4.1 Easy BGA Ballout (32/64/128 Mbit)

Figure 5. Easy BGA Ballout (32/64/128 Mbit)

1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1

A A
A1 A6 A8 VPEN A13 VCC A18 A22 A22 A18 VCC A13 VPEN A8 A6 A1

B B
A2 VSS A9 CE0# A14 RFU A19 CE1# CE1# A19 RFU A14 CE0# A9 VSS A2

C C
A3 A7 A10 A12 A15 RFU A20 A21 A21 A20 RFU A15 A12 A10 A7 A3

D D
A4 A5 A11 RP# RFU RFU A16 A17 A17 A16 RFU RFU RP# A11 A5 A4

E E
D8 D1 D9 D3 D4 RFU D15 STS STS D15 RFU D4 D3 D9 D1 D8

F F
BYTE# D0 D10 D11 D12 RFU RFU OE# OE# RFU RFU D12 D11 D10 D0 BYTE#

G G
A23 A0 D2 VCCQ D5 D6 D14 WE# WE# D14 D6 D5 VCCQ D2 A0 A23

H H
CE2# RFU VCC VSS D13 VSS D7 RFU RFU D7 VSS D13 VSS VCC RFU CE2#

Intel® Embedded Flash Memory (28FXXXJ3D) Intel® Embedded Flash Memory (28FXXXJ3D)
Easy BGA Easy BGA
Top View- Ball side down Bottom View- Ball side up
32/64/128 Mbit 32/64/128 Mbit

NOTES:
1. Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC).
2. Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC).

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4.2 56-Lead TSOP Package Pinout (32/64/128 Mbit)


Figure 6. 56-Lead TSOP Package Pinout (32/64/128 Mbit)

A22 1 56 RFU
CE1 2 55 WE#
A21 3 54 OE#
A20 4 53 STS
A19 5 52 DQ15
A18 6 51 DQ7
A17 7 50 DQ14
A16 8 Intel® Embedded Flash Memory 49 DQ6
VCC 9 48 GND
A15 10 (28FXXXJ3D) 47 DQ13
A14 11 46 DQ5
A13 12 56-Lead TSOP 45 DQ12
A12 13 44 DQ4
Standard Pinout
CE0 14 43 VCCQ
14 mm x 20 mm GND
VPEN 15 42
Top View DQ11
RP# 16 41
A11 17 40 DQ3
A10 18 39 DQ10
A9 19 38 DQ2
A8 20 32/64/128 Mbit 37 VCC
GND 21 36 DQ9
A7 22 35 DQ1
A6 23 34 DQ8
A5 24 33 DQ0
A4 25 32 A0
A3 26 31 BYTE#
A2 27 30 A23
A1 28 29 CE2

NOTES:
1. A22 exists on 64- and 128- densities. On 32-Mbit density this signal is a no-connect (NC).
2. A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC)

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4.3 Signal Descriptions


Table 3 lists the active signals used on J3 v. D and provides a description of each.

Table 3. Signal Descriptions for J3 v. D (Sheet 1 of 2)


Symbol Type Name and Function

BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode.
A0 Input This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is
turned off when BYTE# is high).
ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are
internally latched during a program cycle:
A[MAX:1] Input 32-Mbit — A[21:1]
64-Mbit — A[22:1]
128-Mbit — A[23:1]
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands
D[7:0] Input/Output during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data is
internally latched during write operations.
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.
D[15:8] Input/Output Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register
reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode
CHIP ENABLES: Activate the 32-, 64- and 128 Mbit devices’ control logic, input buffers, decoders,
and sense amplifiers. When the device is de-selected (see Table 15, “Chip Enable Truth Table” on
page 33), power reduces to standby levels.
CE[2:0] Input All timing specifications are the same for these three signals. Device selection occurs with the first
edge of CE0#, CE1#, or CE2# that enables the device. Device deselection occurs with the first
edge of CE0#, CE1#, or CE2# that disables the device (see Table 15, “Chip Enable Truth Table” on
page 33).
RESET: RP#-low resets internal automation and puts the device in power-down mode. RP#-high
RP# Input enables normal operation. Exit from reset sets the device to read array mode. When driven low,
RP# inhibits write operations which provides data protection during power transitions.
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE# Input
OE# is active low.
WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low.
WE# Input
Addresses and data are latched on the rising edge of WE#.
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to
Open Drain
STS indicate program and/or erase completion. For alternate configurations of the STATUS signal, see
Output
the Configurations command and Section 9.6, “Status Signal (STS)” on page 45. STS is to be tied
to VCCQ with a pull-up resistor.
BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0], while
D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-high places
BYTE# Input
the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the lowest-order
address bit.
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or
VPEN Input configuring lock-bits.
With VPEN ≤ VPENLK, memory contents cannot be altered.
CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC
VCC Power ≤ VLKO.
Caution: Device operation at invalid Vcc voltages should not be attempted.
VCCQ Power I/O Power Supply: Power supply for Input/Output buffers.This ball can be tied directly to VCC.

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Table 3. Signal Descriptions for J3 v. D (Sheet 2 of 2)


Symbol Type Name and Function

GND Supply Ground: Ground reference for device logic voltages. Connect to system ground.
NC — No Connect: Lead is not internally connected; it may be driven or floated.
Reserved for Future Use: Balls designated as RFU are reserved by Intel for future device
RFU —
functionality and enhancement.

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5.0 Maximum Ratings and Operating Conditions

5.1 Absolute Maximum Ratings


Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only.

NOTICE: This document contains information available at the time of its release. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet
before finalizing a design.

Table 4. Absolute Maximum Ratings


Parameter Min Max Unit Notes

Temperature under Bias Expanded (TA, Ambient) –40 +85 °C —


Storage Temperature –65 +125 °C —
VCC Voltage –2.0 +5.6 V 2
VCCQ –2.0 +5.6 V 2
Voltage on any input/output signal (except VCC, VCCQ) –2.0 VCCQ (max) + 2.0 V 1
ISH Output Short Circuit Current — 100 mA 3
NOTES:
1. Voltage is referenced to VSS. During infrequent non-periodic transitions, the voltage potential between VSS and
input/output pins may undershoot to –2.0 V for periods < 20 ns or overshoot to VCCQ (max) + 2.0 V for periods < 20
ns.
2. During infrequent non-periodic transitions, the voltage potential between VCC and the supplies may undershoot to –
2.0 V for periods < 20 ns or VSUPPLY (max) + 2.0 V for periods < 20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time

5.2 Operating Conditions


Warning: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond
the “Operating Conditions” may affect device reliability.

Table 6. Temperature and VCC Operating Condition of J3 v. D


Symbol Parameter Min Max Unit Test Condition

TA -40.0 +85 °C Ambient Temperature


VCC VCC Supply Voltage 2.70 3.6 V —
VCCQ VCCQ Supply Voltage 2.70 3.6 V —

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5.3 Power Up/Down


This section provides an overview of system level considerations with regards to the flash device.
It includes a brief description of power-up, power-down and decoupling design considerations.

5.3.1 Power-Up/Down Characteristics


To prevent any condition that may result in a spurious write or erase operation, it is recommended
to power-up and power-down VCC and VCCQ together. It is also recommended to:
• Power-up VPEN after VCC=VCCmin
• Power-down VPEN with or before VCC

5.3.2 Power Supply Decoupling


When the device is enabled, many internal conditions change. Circuits are energized, charge pumps
are switched on, and internal voltage nodes are ramped. All of this internal activities produce
transient signals. The magnitude of the transient signals depends on the device and system loading.
To minimize the effect of these transient signals, a 0.1 µF ceramic capacitor is required across each
VCC/VSS and VCCQ signal. Capacitors should be placed as close as possible to device
connections.

Additionally, for every eight flash devices, a 4.7 µF electrolytic capacitor should be placed between
VCC and VSS at the power supply connection. This 4.7 µF capacitor should help overcome
voltage slumps caused by PCB (printed circuit board) trace inductance.

5.4 Reset
By holding the flash device in reset during power-up and power-down transitions, invalid bus
conditions may be masked. The flash device enters reset mode when RP# is driven low. In reset,
internal flash circuitry is disabled and outputs are placed in a high-impedance state. After return
from reset, a certain amount of time is required before the flash device is able to perform normal
operations. After return from reset, the flash device defaults to asynchronous page mode. If RP# is
driven low during a program or erase operation, the program or erase operation will be aborted and
the memory contents at the aborted block or address are no longer valid. See Figure 12, “AC
Waveform for Reset Operation” on page 31 for detailed information regarding reset timings.

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6.0 Electrical Characteristics

6.1 DC Current Specifications

Table 7. DC Current Characteristics (Sheet 1 of 2)


VCCQ 2.7 - 3.6V

VCC 2.7 - 3.6V Test Conditions Notes

Symbol Parameter Typ Max Unit

VCC = VCC Max; VCCQ = VCCQ Max


ILI Input and VPEN Load Current ±1 µA 1
VIN = VCCQ or VSS
VCC= VCC Max; VCCQ = VCCQ Max
ILO Output Leakage Current ±10 µA 1
VIN = VCCQ or VSS
CMOS Inputs, VCC = VCC Max; Vccq =
VccqMax
50 120 µA Device is disabled (see Table 15, “Chip
Enable Truth Table” on page 33),
RP# = VCCQ ± 0.2 V
ICCS VCC Standby Current 1,2,3
TTL Inputs, VCC = VCC Max,
0.71 2 mA Vccq = VccqMax
Device is disabled (see Table 15, “Chip
Enable Truth Table” on page 33), RP# = VIH
ICCD VCC Power-Down Current 50 120 µA RP# = GND ± 0.2 V, IOUT (STS) = 0 mA
CMOS Inputs, VCC = VCC Max, VCCQ =
VCCQ Max
15 20 mA Device is enabled (see Table 15, “Chip
Enable Truth Table” on page 33)
4-
f = 5 MHz, IOUT = 0 mA
Word
Page CMOS Inputs,VCC = VCC Max, VCCQ =
VCCQ Max
24 29 mA Device is enabled (see Table 15, “Chip 1,3
Enable Truth Table” on page 33)
f = 33 MHz, IOUT = 0 mA
ICCR CMOS Inputs, VCC = VCC Max, VCCQ =
VCC Page Mode Read Current VCCQ Max using standard 8 word page
mode reads.
10 15 mA
Device is enabled (see Table 15, “Chip
Enable Truth Table” on page 33)
8- f = 5 MHz, IOUT = 0 mA
Word CMOS Inputs,VCC = VCC Max, VCCQ =
Page VCCQ Max using standard 8 word page
mode reads.
30 54 mA Device is enabled (see Table 15, “Chip
Enable Truth Table” on page 33)
f = 33 MHz, IOUT = 0 mA
Density: 128-, 64-, and 32- Mbit

VCC Program or Set 35 60 mA CMOS Inputs, VPEN = VCC


ICCW 1,4
Lock-Bit Current 40 70 mA TTL Inputs, VPEN = VCC

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Table 7. DC Current Characteristics (Sheet 2 of 2)


VCCQ 2.7 - 3.6V

VCC 2.7 - 3.6V Test Conditions Notes

Symbol Parameter Typ Max Unit

VCC Block Erase or 35 70 mA CMOS Inputs, VPEN = VCC


ICCE Clear Block Lock-Bits 1,4
Current 40 80 mA TTL Inputs, VPEN = VCC

VCC Program Suspend


ICCWS Device is enabled (see Table 15, “Chip
or Block Erase Suspend 10 mA 1,5
ICCES Enable Truth Table” on page 33)
Current
NOTES:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages
and speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical
specifications.
2. Includes STS.
3. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH.
4. Sampled, not 100% tested.
5. ICCWS and ICCES are specified with the device selected. If the device is read or written while in erase suspend
mode, the device’s current draw is ICCR and ICCWS.

6.2 DC Voltage specifications

Table 8. DC Voltage Characteristics (Sheet 1 of 2)


VCCQ 2.7 - 3.6 V

VCC 2.7 - 3.6 V Test Conditions Notes

Symbol Parameter Min Max Unit

VIL Input Low Voltage –0.5 0.8 V 2, 6, 7


VIH Input High Voltage 2.0 VCCQ + 0.5V V 2, 6, 7
VCC = VCCMin
0.4 V VCCQ = VCCQ Min
IOL = 2 mA
VOL Output Low Voltage 1, 2
VCC = VCCMin
0.2 V VCCQ = VCCQ Min
IOL = 100 µA
VCC = VCCMIN
0.85 × VCCQ V VCCQ = VCCQ Min
IOH = –2.5 mA
VOH Output High Voltage 1, 2
VCC = VCCMIN
VCCQ – 0.2 V VCCQ = VCCQ Min
IOH = –100 µA
VPEN Lockout during
VPENLK Program, Erase and Lock-Bit 2.2 V 2, 3, 4
Operations

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Table 8. DC Voltage Characteristics (Sheet 2 of 2)


VCCQ 2.7 - 3.6 V

VCC 2.7 - 3.6 V Test Conditions Notes

Symbol Parameter Min Max Unit

VPEN during Block Erase,


VPENH Program, or Lock-Bit 2.7 3.6 V 3, 4
Operations
VLKO VCC Lockout Voltage 2.0 V 5
NOTES:
1. Includes STS.
2. Sampled, not 100% tested.
3. Block erases, programming, and lock-bit configurations are inhibited when VPEN ≤ VPENLK, and not
guaranteed in the range between VPENLK (max) and VPENH (min), and above VPENH (max).
4. Typically, VPEN is connected to VCC (2.7 V–3.6 V).
5. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and not
guaranteed in the range between VLKO (min) and VCC (min), and above VCC (max).
6. Includes all operational modes of the device including standby and power-up sequences
7. Input/Output signals can undershoot to -1.0v referenced to VSS and can overshoot to VCCQ = 1.0v for
duration of 2ns or less, the VCCQ valid range is referenced to VSS.

6.3 Capacitance

Table 9. J3 v. D Capacitance
Symbol Parameter1 Type Max Unit Condition2

CIN Input Capacitance 6 8 pF VIN = 0.0 V


COUT Output Capacitance 8 12 pF VOUT = 0.0 V

NOTES:
1. sampled. not 100% tested.
2. TA = +25 °C, f = 1 MHZ

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7.0 AC Characteristics

Timing symbols used in the timing diagrams within this document conform to the following
convention:

t E L Q V
Source Signal Target State
Source State Target Signal

Signal Code State Code

Address A High H
Data - Read Q Low L
Data - Write D High-Z Z
Chip Enable (CE#) E Low-Z X
Output Enable (OE#) G Valid V
Write Enable (WE#) W Invalid I
Address Valid (ADV#) V
Reset (RST#) P
Clock (CLK) C
WAIT T

Note: Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol that refers
to the aggregate initial-access delay as determined by tAVQV, tELQV, and tGLQV (whichever is
satisfied last) of the flash device. tAPA is specified in the flash device’s data sheet, and is the
address-to-data delay for subsequent page-mode reads.

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7.1 Read Specifications

Table 10. Read Operations


Asynchronous Specifications
VCC = 2.7 V–3.6 V (3)
VCCQ = 2.7 V–3.6 V(3)

-75 -95
# Sym Parameter Density Unit Notes
Min Max Min Max

32 Mbit 75 1,2
R1 tAVAV Read/Write Cycle Time 64 Mbit 75 ns 1,2
128 Mbit 75 1,2
32 Mbit 75 1,2
R2 tAVQV Address to Output Delay 64 Mbit 75 ns 1,2
128 Mbit 75 1,2
32 Mbit 75 1,2
R3 tELQV CEX to Output Delay 64 Mbit 75 ns 1,2
128 Mbit 75 1,2
R4 tGLQV OE# to Non-Array Output Delay 25 25 ns 1,2,4
32 Mbit 150 1,2
R5 tPHQV RP# High to Output Delay 64 Mbit 180 ns 1,2
128 Mbit 210 1,2
R6 tELQX CEX to Output in Low Z 0 0 ns 1,2,5
R7 tGLQX OE# to Output in Low Z 0 0 ns 1,2,5
R8 tEHQZ CEX High to Output in High Z 25 25 ns 1,2,5
R9 tGHQZ OE# High to Output in High Z 15 15 ns 1,2,5
Output Hold from Address,
R10 tOH CEX, or OE# Change, 0 0 ns 1,2,5
Whichever Occurs First
tELFL/
R11 CEX Low to BYTE# High or Low 10 10 ns 1,2,5
tELFH
tFLQV/ All
R12 BYTE# to Output Delay 1 1 µs 1,2
tFHQV
R13 tFLQZ BYTE# to Output in High Z 1 1 µs 1,2,5
R14 tEHEL CEx High to CEx Low 0 0 ns 1,2,5

All
R15 tAPA Page Address Access Time 25 25 ns 5, 6

NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0,
CE1, or CE2 that disables the device (see Table 15, “Chip Enable Truth Table” on page 33).
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
2. OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, or CE2 that enables the device (see
Table 15, “Chip Enable Truth Table” on page 33) without impact on tELQV.

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3. See Figure 13, “AC Input/Output Reference Waveform” on page 32 and Figure 14, “Transient Equivalent
Testing Load Circuit” on page 32 for testing characteristics.
4. Sampled, not 100% tested.
5. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).

Figure 7. Single Word Asynchronous Read Waveform

R1
R2
Address [A]

R3 R8
CEx [E]

R9
OE# [G]

WE# [W]

R4
R16
R7
R6 R10
Data [D/Q]

R11 R12
R13
BYT E#[F]

R5
RP# [P]

NOTES:
1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the
first edge of CE0, CE1, or CE2 that disables the device (see Table 15, “Chip Enable Truth Table” on
page 33).
2. When reading the flash array a faster tGLQV (R16) applies. For non-array reads, R4 applies (i.e., Status
Register reads, query reads, or device identifier reads).

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Figure 8. 4-Word Asynchronous Page Mode Read Waveform

R1
R2
A[MAX:3] [A]

A[2:1] [A] 00 01 10 11

R3
CEx [E]

R4
OE# [G]

WE# [W]

R8
R6 R10 R10
R7 R15 R9
D[15:0] [Q] 1 2 3 4

R5
RP# [P]

NOTE: CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at
the first edge of CE0, CE1, or CE2 that disables the device (see Table 15, “Chip Enable Truth Table” on
page 33).

Figure 9. 8-Word Asynchronous Page Mode Read

R1
R2
A[MAX:4] [A]

A[3:1] [A]

R3
CEx [E]

R4
OE# [G]

WE# [W]

R10
R6 R10 R8
R7 R15 R9
D[15:0] [Q] 1 2 7 8

R5
RP# [P]

BYTE#

NOTES:
1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the
first edge of CE0, CE1, or CE2 that disables the device (see Table 15, “Chip Enable Truth Table” on
page 33).
2. In this diagram, BYTE# is asserted high

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7.2 Write Specifications

Table 11. Write Operations


Valid for All
Speeds
# Symbol Parameter Density Unit Notes
Min Max

32 Mbit 150 1,2,3


W1 tPHWL (tPHEL) RP# High Recovery to WE# (CEX) Going Low 64 Mbit 180
128 Mbit 210
W2 tELWL (tWLEL) CEX (WE#) Low to WE# (CEX) Going Low 0 1,2,4
W3 tWP Write Pulse Width 60 1,2,4
W4 tDVWH (tDVEH) Data Setup to WE# (CEX) Going High 50 1,2,5
W5 tAVWH (tAVEH) Address Setup to WE# (CEX) Going High 55 1,2,5
W6 tWHEH (tEHWH) CEX (WE#) Hold from WE# (CEX) High 0 ns 1,2,
W7 tWHDX (tEHDX) Data Hold from WE# (CEX) High 0 1,2,
All
W8 tWHAX (tEHAX) Address Hold from WE# (CEX) High 0 1,2,
W9 tWPH Write Pulse Width High 30 1,2,6
W11 tVPWH (tVPEH) VPEN Setup to WE# (CEX) Going High 0 1,2,3
W12 tWHGL (tEHGL) Write Recovery before Read 35 1,2,7
W13 tWHRL (tEHRL) WE# (CEX) High to STS Going Low 500 1,2,8
W15 tQVVL VPEN Hold from Valid SRD, STS Going High 0 1,2,3,8,9
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of
CE0, CE1, or CE2 that disables the device (see Table 15, “Chip Enable Truth Table” on page 33).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the
same as during read-only operations. Refer to AC Characteristics–Read-Only Operations.
2. A write operation can be initiated and terminated with either CEX or WE#.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE#
going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH .
5. Refer to Table 16, “Enhanced Configuration Register” on page 35 for valid AIN and DIN for block erase,
program, or lock-bit configuration.
6. Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX
or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
8. STS timings are based on STS configured in its RY/BY# default mode.
9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration
success (SR[1,3,4,5] = 0).

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Figure 10. Asynchronous Write Waveform

W5 W8
ADDRESS [A]

W6
CEx (WE#) [E (W)]

W2 W3 W9
WE# (CEx) [W (E)]

OE# [G]

W4 W7
DATA [D/Q] D

W13
ST S[R]

W1
RP# [P]

W11
VPEN [V]

Figure 11. Asynchronous Write to Read Waveform

W5 W8
Address [A]

W6
CE# [E]

W2 W3
WE# [W]

W12
OE# [G]

W4 W7
Data [D/Q] D

W1
RST#/ RP# [P]

W11
VPEN [V]

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7.3 Program, Erase, Block-Lock Specifications

Table 12. Configuration Performance


# Symbol Parameter Typ Max(8) Unit Notes

Write Buffer Byte Program Time


W16 128 654 µs 1,2,3,4,5,6,7
(Time to Program 32 bytes/16 words)
tWHQV3
W16 Byte Program Time (Using Word/Byte Program Command) 40 175 µs 1,2,3,4
tEHQV3
Block Program Time (Using Write to Buffer Command) 0.53 2.4 sec 1,2,3,4
tWHQV4
W16 Block Erase Time 1.0 4.0 sec 1,2,3,4
tEHQV4
tWHQV5
W16 Set Lock-Bit Time 50 60 µs 1,2,3,4,9
tEHQV5
tWHQV6
W16 Clear Block Lock-Bits Time 0.5 0.70 sec 1,2,3,4,9
tEHQV6
tWHRH1
W16 Program Suspend Latency Time to Read 15 20 µs 1,2,3,9
tEHRH1
tWHRH
W16 Erase Suspend Latency Time to Read 15 20 µs 1,2,3,9
tEHRH
WY tSTS STS Pulse Width Low Time 500 ns 1
WX tWHWH Resume Latency to Program/Erase 475 µs 1, 10
NOTES:
1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set.
Subject to change based on device characterization.
2. These performance numbers are valid for all speed versions.
3. Sampled but not 100% tested.
4. Excludes system-level overhead.
5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.
6. Effective per-byte program time (tWHQV1, tEHQV1) is 4µs/byte (typical).
7. Effective per-word program time (tWHQV2, tEHQV2) is 8µs/word (typical).
8. Max values are measured at worst case temperature, data pattern and VCC corner after 100k cycles (except
as noted).
9. Max values are expressed at 25 °C/-40 °C.
10.WX is the minimum time from Erase Resume to an Erase Suspend state. Repeatedly suspending the device
more often may have undetermined effects.

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7.4 Reset Specifications

Figure 12. AC Waveform for Reset Operation

STS (R)

P1 P2
RP# (P)

P3
Vcc

NOTE: STS is shown in its default mode (RY/BY#)

Table 13. Reset Specifications


# Symbol Parameter Min Max Unit Notes

RP# Pulse Low Time


P1 tPLPH (If RP# is tied to VCC, this specification is not 25 µs 1,2
applicable)
RP# High to Reset during Block Erase, Program, or
P2 tPHRH 100 ns 1,3
Lock-Bit Configuration
P3 tVCCPH Vcc Power Valid to RP# de-assertion (high) 60 µs
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not
executing then the minimum required RP# Pulse Low Time is 100 ns.
3. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until
outputs are valid.

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7.5 AC Test Conditions

Figure 13. AC Input/Output Reference Waveform

VCCQ
Input VCCQ/2 Test Points VCCQ/2 Output
0.0
NOTE: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and
output timing ends, at VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.

Figure 14. Transient Equivalent Testing Load Circuit

Device
Under Test Out
CL

NOTE: CL Includes Jig Capacitance

Test Configuration CL (pF)

VCCQ = VCCQMIN 30

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8.0 Bus Interface

This section provides an overview of Bus operations. Basically, there are three operations you can
do with flash memory: Read, Program (Write), and Erase.The on-chip Write State Machine (WSM)
manages all erase and program algorithms. The system CPU provides control of all in-system read,
write, and erase operations through the system bus. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles. Table 14 summarizes the necessary states of each
control signal for different modes of operations.

Table 14. Bus Operations

Mode RP# CEx(1) OE#(2) WE#(2) VPEN DQ15:0(3) STS Notes


(Default Mode)

Async., Status, Query and Identifier Reads VIH Enabled VIL VIH X DOUT High Z 4,6

Output Disable VIH Enabled VIH VIH X High Z High Z


Standby VIH Disabled X X X High Z High Z
Reset/Power-down VIL X X X X High Z High Z

Command Writes VIH Enabled VIH VIL X DIN High Z 6,7


(8)
Array Writes VIH Enabled VIH VIL VPENH X VIL 8,5

NOTES:
1. See Table 15 for valid CEx Configurations.
2. OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
3. DQ refers to DQ[7:0} when BYTE# is low and DQ[15:0] if BYTE# is high.
4. Refer to DC characteristics. When VPEN ≤ VPENLK, memory contents can be read but not altered.
5. X should be VIL or VIH for the control pins and VPENLK or VPENH for VPEN. For outputs, X should be VOL or
VOH.
6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or a lock-bit
configuration algorithm. It is VOH (pulled up by an external pull up resistance ~= 10k) when the WSM is not
busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset power-
down mode.
7. See Table 18, “Command Bus Operations for J3 v. D” on page 37 for valid DIN (user commands) during a
Write operation
8. Array writes are either program or erase operations. /

Table 15. Chip Enable Truth Table


CE2 CE1 CE0 DEVICE

VIL VIL VIL Enabled


VIL VIL VIH Disabled
VIL VIH VIL Disabled
VIL VIH VIH Disabled
VIH VIL VIL Enabled
VIH VIL VIH Enabled
VIH VIH VIL Enabled
VIH VIH VIH Disabled
NOTE: For single-chip applications, CE2 and CE1 can be connected to GND.

The next few sections detail each of the basic flash operations and some of the advanced features
available on flash memory.

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8.1 Bus Reads


Reading from flash memory outputs stored information to the processor or chipset, and does not
change any contents. Reading can be performed an unlimited number of times. Besides array data,
other types of data such as device information and device status is available from the flash.

To perform a bus read operation, CEx (refer to Table 15 on page 33) and OE# must be asserted.
CEx is the device-select control; when active, it enables the flash memory device. OE# is the data-
output control; when active, the addressed flash memory data is driven onto the I/O bus. For all
read states, WE# and RP# must be de-asserted. See Section 9.2, “Read Operations” on page 39.

8.1.1 Asynchronous Page Mode Read


There are two Asynchronous Page mode configurations available on J3 v. D, depending on the
system design requirements:
• Four-Word Page mode: This is the default mode on power-up or reset. Array data can be
sensed up to four words (8 Bytes) at a time.
• Eight-Word Page mode: Array data can be sensed up to eight words (16 Bytes) at a time. This
mode must be enabled on power-up or reset by using the command sequence described in
Table 18 on page 37. Address bits A[3:1] determine which word is output during a read
operation, and A[3:0] determine which byte is output for a x8 bus width.

After the initial access delay, the first word out of the page buffer corresponds to the initial address.
In Four-Word Page mode, address bits A[2:1] determine which word is output from the page buffer
for a x16 bus width, and A[2:0] determine which byte is output from the page buffer for a x8 bus
width. Subsequent reads from the device come from the page buffer. These reads are output on
D[15:0] for a x16 bus width and D[7:0] for a x8 bus width after a minimum delay as long as A[2:0]
(Four-Word Page mode) or A[3:0] (Eight-Word Page mode).

Data can be read from the page buffer multiple times, and in any order. In Four-Word Page mode, if
address bits A[MAX:3] (A[MAX:4] for Eight-Word Page Mode) change at any time, or if CE# is
toggled, the device will sense and load new data into the page buffer. Asynchronous Page mode is
the default read mode on power-up or reset.

To perform a Page mode read after any other operation, the Read Array command must be issued to
read from the flash array. Asynchronous Page mode reads are permitted in all blocks and are used
to access register information. During register access, only one word is loaded into the page buffer.

8.1.1.1 Enhanced Configuration Register (ECR)


The Enhanced Configuration Register (ECR) is a volatile storage register that when addressed by
the Set Enhanced Configuration Register command can select between Four-Word Page mode and
Eight-Word Page mode. The ECR is volatile; all bits will be reset to default values when RP# is
deasserted or power is removed from the device. To modify ECR settings, use the Set Enhanced
Configuration Register command. The Set Enhanced Configuration Register command is written
along with the configuration register value, which is placed on the lower 16 bits of the address bus
A[15:0]. This is followed by a second write that confirms the operation and again presents the
Enhanced Configuration Register data on the address bus. After executing this command, the
device returns to Read Array mode.

The ECR is shown in Table 16. 8-word page mode Command Bus-Cycle is captured in Table 17.

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Note: For forward compatibility reasons, if the 8-word Asynchronous Page mode is used on J3 v. D, a
Clear Status Register command must be executed after issuing the Set Enhanced Configuration
Register command. See Table 17 for further details.

Table 16. Enhanced Configuration Register


Page
Reserved Reserved
Length

ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR ECR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS DESCRIPTION NOTES
ECR[15:14] RFU All bits should be set to 0.
• “1” = 8 Word Page mode
ECR[13]
• “0” = 4 Word Page mode
ECR[12:0] RFU All bits should be set to 0.

Table 17. J3 v. D Asynchronous 8-Word Page Mode Command Bus-Cycle Definition


Bus First Bus Cycle Second Bus Cycle
Command Cycles
Required Oper Addr(1) Data Oper Addr(1) Data

Set Enhanced Configuration


2 Write ECD 0060h Write ECD 0004h
Register (Set ECR)
1. X = Any valid address within the device. ECD = Enhanced Configuration Register Data

8.1.2 Output Disable


With CEx asserted, and OE# at a logic-high level (VIH), the device outputs are disabled. Output
signals D[15:0] are placed in a high-impedance state.

8.2 Bus Writes


Writing or Programming to the device, is where the host writes information or data into the flash
device for non-volatile storage. When the flash device is programmed, ‘ones’ are changed to
‘zeros’. ‘Zeros’ cannot be programed back to ‘ones’. To do so, an erase operation must be
performed. Writing commands to the Command User Interface (CUI) enables various modes of
operation, including the following:
• Reading of array data
• Common Flash Interface (CFI) data
• Identifier codes, inspection, and clearing of the Status Register
• Block Erasure, Program, and Lock-bit Configuration (when VPEN = V PENH)

Erasing is performed on a block basis – all flash cells within a block are erased together. Any
information or data previously stored in the block will be lost. Erasing is typically done prior to
programming. The Block Erase command requires appropriate command data and an address
within the block to be erased. The Byte/Word Program command requires the command and

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address of the location to be written. Set Block Lock-Bit commands require the command and
block within the device to be locked. The Clear Block Lock-Bits command requires the command
and address within the device to be cleared.

The CUI does not occupy an addressable memory location. It is written when the device is enabled
and WE# is active. The address and data needed to execute a command are latched on the rising
edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 15 on
page 33). Standard microprocessor write timings are used.

8.3 Standby
CE0, CE1, and CE2 can disable the device (see Table 15 on page 33) and place it in standby mode.
This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are
placed in a high-impedance state independent of OE#. If deselected during block erase, program, or
lock-bit configuration, the WSM continues functioning, and consuming active power until the
operation completes.

8.3.1 Reset/Power-Down
RP# at V IL initiates the reset/power-down mode.

In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and
turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is
required after return from reset mode until initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The CUI is reset to read array mode and Status Register is
set to 0080h.

During Block Erase, Program, or Lock-Bit Configuration modes, RP#-low will abort the operation.
In default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until
the reset operation is complete. Memory contents being altered are no longer valid; the data may be
partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time
tPHWL is required after RP# goes to logic-high (V IH) before another command can be written.

As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash memory. Automated flash memories provide
status information when accessed during Block Erase, Program, or Lock-Bit Configuration modes.
If a CPU reset occurs with no flash memory reset, proper initialization may not occur because the
flash memory may be providing status information instead of array data. Intel® Flash memories
allow proper initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.

8.4 Device Commands


When the VPEN voltage ≤ V PENLK, only read operations from the Status Register, CFI, identifier
codes, or blocks are enabled. Placing V PENH on VPEN additionally enables block erase, program,
and lock-bit configuration operations. Device operations are selected by writing specific
commands to the Command User Interface (CUI). The CUI does not occupy an addressable
memory location. It is the mechanism through which the flash device is controlled.

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A command sequence is issued in two consecutive write cycles - a Setup command followed by a
Confirm command. However, some commands are single-cycle commands consisting of a setup
command only. Generally, commands that alter the contents of the flash device, such as Program or
Erase, require at least two write cycles to guard against inadvertent changes to the flash device.
Flash commands fall into two categories: Basic Commands and Extended Commands. Basic
commands are recognized by all Intel® Flash devices, and are used to perform common flash
operations such as selecting the read mode, programming the array, or erasing blocks. Extended
commands are product-dependant; they are used to perform additional features such as software
block locking. Table 18 describes all applicable commands on Intel® Embedded Flash Memory (J3
v. D).

Table 18. Command Bus Operations for J3 v. D


Setup Write Cycle Confirm Write Cycle
Command
Address Bus Data Bus Address Bus Data Bus

Program Enhanced Configuration Register Register Data 0060h Register Data 0004h
Registers

Program OTP Register Device Address 00C0h Register Offset Register Data
Clear Status Register Device Address 0050h --- ---
Program STS Configuration Register Device Address 00BS8h Device Address Register Data
Read Array Device Address 00FFh --- ---
Read Modes

Read Status Register Device Address 0070h --- ---


Read Identifier Codes (Read Device Information) Device Address 0090h --- ---
CFI Query Device Address 0098h --- ---
0040h/
Program and Erase

Word/Byte Program Device Address Device Address Array Data


0010h
Buffered Program Word Address 00E8h Device Address 00D0h
Block Erase Device Address 0020h Block Address 00D0h
Program/Erase Suspend Device Address 00B0h --- ---
Program/Erase Resume Device Address 00D0h --- ---
Lock Block Block Address 0060h Block Address 0001h
Security

Unlock Block Block Address 0060h Block Address 00D0h

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9.0 Flash Operations

This section describes the operational features of flash memory. Operations are command-based,
wherein command codes are first issued to the device, then the device performs the desired
operation. All command codes are issued to the device using bus-write cycles (see Chapter 8.0,
“Bus Interface”). A complete list of available command codes can be found in Appendix A,
“Device Command Codes”.

9.1 Status Register


The Status Register (SR) is an 8-bit, read-only register that indicates device status and operation
errors. To read the Status Register, issue the Read Status Register command. Subsequent reads
output Status Register information on DQ[7:0], and 00h on DQ[15:8].

SR status bits are set and cleared by the device. SR error bits are set by the device, but must be
cleared using the Clear Status Register command. Upon power-up or exit from reset, the Status
Register defaults to 80h. Page-mode reads are not supported in this read mode. Status Register
contents are latched on the falling edge of OE# or the first edge of CEx that enables the device.
OE# must toggle to VIH or the device must be disabled before further reads to update the Status
Register latch. The Read Status Register command functions independently of VPEN voltage.
Table 19 shows Status Register bit definitions.

Table 19. Status Register Bit Definitions

Status Register (SR) Default Value = 80h

Program
Erase Program Block-
Ready Erase Program /Erase
Suspend Suspend Locked Reserved
Status Error Error Voltage
Status Status Error
Error

7 6 5 4 3 2 1 0

Bit Name Description

0 = Device is busy; SR[6:0] are invalid (Not driven);


7 Ready Status
1 = Device is ready; SR[6:0] are valid.
0 = Erase suspend not in effect.
6 Erase Suspend Status
1 = Erase suspend in effect.

SR5 SR4
5 Erase Command 0 0 = Program or erase operation successful.
Error Sequence 0 1 = Program error - operation aborted.
Program Error 1 0 = Erase error - operation aborted.
4 1 1 = Command sequence error - command aborted.
Error
0 = VPEN within acceptable limits during program or erase operation.
3 VPEN Error 1 = VPEN not within acceptable limits during program or erase
operation. Operation aborted.
0 = Program suspend not in effect.
2 Program Suspend Status
1 = Program suspend in effect.
0 = Block NOT locked during program or erase - operation successful.
1 Block-Locked Error
1 = Block locked during program or erase - operation aborted.
0 Reserved Not used - Reserved for future use.

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9.1.1 Clearing the Status Register


The Status Register (SR) contain status and error bits which are set by the device. SR status bits are
cleared by the device, however SR error bits are cleared by issuing the Clear Status Register
command (see Table 20). Resetting the device also clears the Status Register.

Table 20. Clear Status Register Command Bus-Cycle


Setup Write Cycle Confirm Write Cycle
Command
Address Bus Data Bus Address Bus Data Bus

Clear Status Register Device Address 0050h --- ---

Issuing the Clear Status Register command places the device in Read Status Register mode.

Note: Care should be taken to avoid Status Register ambiguity. If a command sequence error occurs
while in an Erase Suspend condition, the Status Register will indicate a Command Sequence error
by setting SR4 and SR5. When the erase operation is resumed (and finishes), any errors that may
have occurred during the erase operation will be masked by the Command Sequence error. To
avoid this situation, clear the Status Register prior to resuming a suspended erase operation. The
Clear Status Register command functions independent of the voltage level on VPEN.

9.2 Read Operations


Four types of data can be read from the device: array data, device information, CFI data, and device
status. Upon power-up or return from reset, the device defaults to Read Array mode. To change the
device’s read mode, the appropriate command must be issued to the device. Table 21 shows the
command codes used to configure the device for the desired read mode. The following sections
describe each read mode.

Table 21. Read Mode Command Bus-Cycles


Setup Write Cycle Confirm Write Cycle
Command
Address Bus Data Bus Address Bus Data Bus

Read Array Device Address 00FFh --- ---


Read Status Register Device Address 0070h --- ---
Read Device Information Device Address 0090h --- ---
CFI Query Device Address 0098h --- ---

9.2.1 Read Array


Upon power-up or return from reset, the device defaults to Read Array mode. Issuing the Read
Array command places the device in Read Array mode. Subsequent reads output array data on
DQ[15:0]. The device remains in Read Array mode until a different read command is issued, or a
program or erase operation is performed, in which case, the read mode is automatically changed to
Read Status.

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To change the device to Read Array mode while it is programming or erasing, first issue the
Suspend command. After the operation has been suspended, issue the Read Array command. When
the program or erase operation is subsequently resumed, the device will automatically revert back
to Read Status mode.

Note: Issuing the Read Array command to the device while it is actively programming or erasing causes
subsequent reads from the device to output invalid data. Valid array data is output only after the
program or erase operation has finished.

The Read Array command functions independent of the voltage level on VPEN.

9.2.2 Read Status Register


Issuing the Read Status Register command places the device in Read Status Register mode.
Subsequent reads output Status Register information on DQ[7:0], and 00h on DQ[15:8]. The
device remains in Read Status Register mode until a different read-mode command is issued.
Performing a program, erase, or block-lock operation also changes the device’s read mode to Read
Status Register mode.

The Status Register is updated on the falling edge of CE#, or OE# when CE# is low. Status Register
contents are valid only when SR7 = 1. When WSM us active, SR7 indicates the WSM’s state and
SR[6:0] are in hig-Z state.

The Read Status Register command functions independent of the voltage level on VPEN.

9.2.3 Read Device Information


Issuing the Read Device Information command places the device in Read Device Information
mode. Subsequent reads output device information on DQ[15:0] (see Table 22).

Table 22. Device Information Summary


Device Information Word Address DQ[15:0]

Device Manufacturer Code (Intel) Device Base Address + 00h 0089h


Device ID Code Device Base Address + 01h (See Appendix B, “J3 v. D ID Codes”)
DQ0 = 0 Unlocked
Block Lock Status Block Base Address + 02h DQ0 = 1 Locked
DQ[15:1] = RFU
OTP Lock Register Device Base Address + 80h Lock Register 0 Data
OTP Register - Factory Segment Device Base Address + 81h to 84h Factory-Programmed Data
OTP Register - User-Programmable Segment Device Base Address + 85h to 88h User Data

The device remains in Read Device Information mode until a different read command is issued.
Also, performing a program, erase, or block-lock operation changes the device to Read Status
Register mode.

The Read Device Information command functions independent of the voltage level on VPEN.

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9.2.4 CFI Query


The query table contains an assortment of flash product information such as block size, density,
allowable command sets, electrical specifications, and other product information. The data
contained in this table conforms to the Common Flash Interface (CFI) protocol.

Issuing the CFI Query command places the device in CFI Query mode. Subsequent reads output
CFI information on DQ[15:0] (see Appendix D, “Common Flash Interface”).

The device remains in CFI Query mode until a different read command is issued, or a program or
erase operation is performed, which changes the read mode to Read Status Register mode.

The CFI Query command functions independent of the voltage level on VPEN.

9.3 Programming Operations


Programming the flash array changes ‘ones’ to ‘zeros’. To change zeros to ones, an erase operation
must be performed (see Section 9.4, “Block Erase Operations”). Only one programming operation
can occur at a time. Programming is permitted during an erase suspend.

Information is programmed into the flash array by issuing the appropriate command. J3 v. D
supports two different programming methods: Byte/Word and Write-to-Buffer. Table 24 shows the
two-cycle command sequences used for each method.

Table 24. Program Command Bus-Cycles


Setup Write Cycle Confirm Write Cycle
Command
Address Bus Data Bus Address Bus Data Bus

Single-Word/Byte Program Device Address 0040h/0010h Device Address Array Data


Buffered Program Device Address 00E8h Device Address 00D0h

Note: All programming operations require the addressed block to be unlocked, and a valid VPEN voltage
applied throughout the programming operation. Otherwise, the programming operation will abort,
setting the appropriate Status Register error bit(s).

The following sections describe each programming method.

9.3.1 Single-Word/Byte Programming


Array programming is performed by first issuing the Single-Word/Byte Program command. This is
followed by writing the desired data at the desired array address. The read mode of the device is
automatically changed to Read Status Register mode, which remains in effect until another read-
mode command is issued.

During programming, STS and the Status Register indicate a busy status (SR7 = 0). Upon
completion, STS and the Status Register indicate a ready status (SR7 = 1). The Status Register
should be checked for any errors (SR4), then cleared.

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Note: Issuing the Read Array command to the device while it is actively programming causes subsequent
reads from the device to output invalid data. Valid array data is output only after the program
operation has finished.

Standby power levels are not be realized until the programming operation has finished. Also,
asserting RP# aborts the programming operation, and array contents at the addressed location are
indeterminate. The addressed block should be erased, and the data re-programmed. If a Single-
Word/Byte program is attempted when the corresponding block lock-bit is set, SR1 and SR4 will
be set.

9.3.2 Buffered Programming


Buffered programming operations simultaneous program multiple words into the flash memory
array, significantly reducing effective word-write times. User-data is first written to a write buffer,
then programmed into the flash memory array in buffer-size increments. Appendix C, “Flow
Charts” contains a flow chart of the buffered-programming operation.

Note: Optimal performance and power consumption is realized only by aligning the start address on 32-
word boundaries (i.e., A[4:0] = 0b00000). Crossing a 32-word boundary during a buffered
programming operation can cause programming time to double.

To perform a buffered programming operation, first issue the Buffered Program setup command at
the desired starting address. The read mode of the device/addressed partition is automatically
changed to Read Status Register mode.

Polling SR7 determines write-buffer availability (0 = not available, 1 = available). If the write
buffer is not available, re-issue the setup command and check SR7; repeat until SR7 = 1.

Next, issue the word count at the desired starting address. The word count represents the total
number of words to be written into the write buffer, minus one. This value can range from 00h (one
word) to a maximum of 1Fh (32 words). Exceeding the allowable range causes an abort.

Following the word count, the write buffer is filled with user-data. Subsequent bus-write cycles
provide addresses and data, up to the word count. All user-data addresses must lie between
<starting address> and <starting address + word count>, otherwise the WSM continues to run as
normal but, user may advertently change the content in unexpected address locations.

Note: User-data is programmed into the flash array at the address issued when filling the write buffer.

After all user-data is written into the write buffer, issue the confirm command. If a command other
than the confirm command is issued to the device, a command sequence error occurs and the
operation aborts.

After issuing the confirm command, write-buffer contents are programmed into the flash memory
array. The Status Register indicates a busy status (SR7 = 0) during array programming.

Note: Issuing the Read Array command to the device while it is actively programming or erasing causes
subsequent reads from the device to output invalid data. Valid array data is output only after the
program or erase operation has finished.

Upon completion of array programming, the Status Register indicates ready (SR7 = 1). A full
Status Register check should be performed to check for any programming errors, then cleared by
using the Clear Status Register command.

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Additional buffered programming operations can be initiated by issuing another setup command,
and repeating the buffered programming bus-cycle sequence. However, any errors in the Status
Register must first be cleared before another buffered programming operation can be initiated.

9.4 Block Erase Operations


Erasing a block changes ‘zeros’ to ‘ones’. To change ones to zeros, a program operation must be
performed (see Section 9.3, “Programming Operations”). Erasing is performed on a block basis -
an entire block is erased each time an erase command sequence is issued. Once a block is fully
erased, all addressable locations within that block read as logical ones (FFFFh). Only one block-
erase operation can occur at a time, and is not permitted during a program suspend.

To perform a block-erase operation, issue the Block Erase command sequence at the desired block
address. Table 25 shows the two-cycle Block Erase command sequence.

Table 25. Block-Erase Command Bus-Cycle


Setup Write Cycle Confirm Write Cycle
Command
Address Bus Data Bus Address Bus Data Bus

Block Erase Device Address 0020h Block Address 00D0h

Note: A block-erase operation requires the addressed block to be unlocked, and a valid voltage applied to
VPEN throughout the block-erase operation. Otherwise, the operation will abort, setting the
appropriate Status Register error bit(s).

The Erase Confirm command latches the address of the block to be erased. The addressed block is
preconditioned (programmed to all zeros), erased, and then verified. The read mode of the device is
automatically changed to Read Status Register mode, and remains in effect until another read-mode
command is issued.

During a block-erase operation, STS and the Status Register indicates a busy status (SR7 = 0).
Upon completion, STS and the Status Register indicates a ready status (SR7 = 1). The Status
Register should be checked for any errors, then cleared. If any errors did occur, subsequent erase
commands to the device are ignored unless the Status Register is cleared.

The only valid commands during a block erase operation are Read Array, Read Device
Information, CFI Query, and Erase Suspend. After the block-erase operation has completed, any
valid command can be issued.

Note: Issuing the Read Array command to the device while it is actively erasing causes subsequent reads
from the device to output invalid data. Valid array data is output only after the block-erase
operation has finished.

Standby power levels are not be realized until the block-erase operation has finished. Also,
asserting RP# aborts the block-erase operation, and array contents at the addressed location are
indeterminate. The addressed block should be erased before programming within the block is
attempted.

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9.5 Suspend and Resume


An erase or programming operation can be suspended to perform other operations, and then
subsequently resumed. Table 26 shows the Suspend and Resume command bus-cycles.

Note: All erase and programming operations require the addressed block to remain unlocked with a valid
voltage applied to VPEN throughout the suspend operation. Otherwise, the block-erase or
programming operation will abort, setting the appropriate Status Register error bit(s). Also,
asserting RP# aborts suspended block-erase and programming operations, rendering array contents
at the addressed location(s) indeterminate.

Table 26. Suspend and Resume Command Bus-Cycles


Setup Write Cycle Confirm Write Cycle
Command
Address Bus Data Bus Address Bus Data Bus

Suspend Device Address 00B0h --- ---


Resume Device Address 00D0h --- ---

To suspend an on-going erase or program operation, issue the Suspend command to any device
address. The program or erase operation suspends at pre-determined points during the operation
after a delay of tSUSP. Suspend is achieved when STS (in RY/BY# mode) goes high, SR[7,6] = 1
(erase-suspend) or SR[7,2] = 1 (program-suspend).

Note: Issuing the Suspend command does not change the read mode of the device. The device will be in
Read Status Register mode from when the erase or program command was first issued, unless the
read mode was changed prior to issuing the Suspend command.

Not all commands are allowed when the device is suspended. Table 27 shows which device
commands are allowed during Program Suspend or Erase Suspend.

Table 27. Valid Commands During Suspend (Sheet 1 of 2)


Device Command Program Suspend Erase Suspend

STS Configuration Allowed Allowed


Read Array Allowed Allowed
Read Status Register Allowed Allowed
Clear Status Register Allowed Allowed
Read Device Information Allowed Allowed
CFI Query Allowed Allowed
Word Program Not Allowed Allowed
Buffered Program Not Allowed Allowed
Block Erase Not Allowed Not Allowed
Program Suspend Not Allowed Allowed
Erase Suspend Not Allowed Not Allowed
Program/Erase Resume Allowed Allowed

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Table 27. Valid Commands During Suspend (Sheet 2 of 2)


Device Command Program Suspend Erase Suspend

Lock Block Not Allowed Not Allowed


Unlock Block Not Allowed Not Allowed
Program OTP Register Not Allowed Not Allowed

During Suspend, array-read operations are not allowed in blocks being erased or programmed.

A block-erase under program-suspend is not allowed. However, word-program under erase-


suspend is allowed, and can be suspended. This results in a simultaneous erase-suspend/ program-
suspend condition, indicated by SR[7,6,2] = 1.

To resume a suspended program or erase operation, issue the Resume command to any device
address. The read mode of the device is automatically changed to Read Status Register. The
operation continues where it left off, STS (in RY/BY# mode) goes low, and the respective Status
Register bits are cleared.

When the Resume command is issued during a simultaneous erase-suspend/ program-suspend


condition, the programming operation is resumed first. Upon completion of the programming
operation, the Status Register should be checked for any errors, and cleared. The resume command
must be issued again to complete the erase operation. Upon completion of the erase operation, the
Status Register should be checked for any errors, and cleared.

9.6 Status Signal (STS)


The STATUS (STS) signal can be configured to different states using the STS Configuration
command. Once the STS signal has been configured, it remains in that configuration until another
Configuration command is issued or RP# is asserted low. Initially, the STS signal defaults to RY/
BY# operation where RY/BY# low indicates that the WSM is busy. RY/BY# high indicates that the
state machine is ready for a new operation or suspended. Table 29 displays possible STS
configurations.

Table 28. STS Configuration Register


Setup Write Cycle Confirm Write Cycle
Command
Address Bus Data Bus Address Bus Data Bus
1 2
STS Configuration Device Address 00B8h Device Address Register Data

NOTES:
1. In case of 256 Mb device (2x128), the command sequence must be repeated for each die at its base address
2. In case of 256 Mb device (2x128), keep the second cycle to the same address. (ie. Do not toggle A24 for the
second cycle)

To reconfigure the STATUS (STS) signal to other modes, the Configuration command is given
followed by the desired configuration code. The three alternate configurations are all pulse mode
for use as a system interrupt as described in the following paragraphs. For these configurations, bit
0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse.
Supplying the 0x00 configuration code with the Configuration command resets the STS signal to

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the default RY/BY# level mode. The Configuration command may only be given when the device
is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in
SR.4 and SR.5 being set.

Note: STS Pulse mode is not supported in the Clear Lock Bits and Set Lock Bit commands

Table 29. STS Configuration Coding Definitions


D7 D6 D5 D4 D3 D2 D1 D0

Pulse on Pulse on
Program Erase
Reserved
Complete Complete
(1) (1)

D[1:0] = STS Configuration Codes Notes

00 = default, level mode; Controls HOLD to a memory controller to prevent accessing a flash
device ready indication memory subsystem while any flash device's WSM is busy.
Generates a system interrupt pulse when any flash device in an array
01 = pulse on Erase Complete has completed a block erase. Helpful for reformatting blocks after file
system free space reclamation or “cleanup.”
10 = pulse on Program Complete Not supported on this device.
Generates system interrupts to trigger servicing of flash arrays when
11 = pulse on Erase or Program either erase or program operations are completed, when a common
Complete
interrupt service routine is desired.
NOTES:
1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 250 ns.
2. An invalid configuration code will result in both SR4 and SR5 being set.
3. Reserved bits are invalid should be ignored.

9.7 Security and Protection


Intel® Embedded Flash Memory (J3 v. D) device offer both hardware and software security
features. Block lock operations, PRs and VPEN allow users to implement various levels of data
protection.

9.7.1 Normal Block Locking


J3 v. D has the unique capability of Flexible Block Locking (locked blocks remain locked upon
reset or power cycle): All blocks are unlocked at the factory. Blocks can be locked individually by
issuing the Set Block Lock Bit command sequence to any address within a block. Once locked,
blocks remain locked when power is removed, or when the device is reset.

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All locked blocks are unlocked simultaneously by issuing the Clear Block Lock Bits command
sequence to any device address. Locked blocks cannot be erased or programmed. Table 30
summarizes the command bus-cycles.

Table 30. Block Locking Command Bus-Cycles


Setup Write Cycle Confirm Write Cycle
Command
Address Bus Data Bus Address Bus Data Bus

Set Block Lock Bit Block Address 0060h Block Address 0001h
Clear Block Lock Bits Device Address 0060h Device Address 00D0h

After issuing the Set Block Lock Bit setup command or Clear Block Lock Bits setup command, the
device’s read mode is automatically changed to Read Status Register mode. After issuing the
confirm command, completion of the operation is indicated by STS (in RY/BY# mode) going high
and SR7 = 1.

Blocks cannot be locked or unlocked while programming or erasing, or while the device is
suspended. Reliable block lock and unlock operations occur only when VCC and VPEN are valid.
When VPEN ≤ V PENLK, block lock-bits cannot be changed.

When the set lock-bit operation is complete, SR4 should be checked for any error. When the clear
lock-bit operation is complete, SR5 should be checked for any error. Errors bits must be cleared
using the Clear Status Register command.

Block lock-bit status can be determined by first issuing the Read Device Information command,
and then reading from <block base address> + 02h. DQ0 indicates the lock status of the addressed
block (0 = unlocked, 1 = locked).

9.7.2 Configurable Block Locking


One of the unique new features on the J3 v. D, non-existent on the previous generations of this
product family, is the ability to protect and/or secure the user’s system by offering multiple level of
securities: Non-Volatile Temporary; Non-Volatile Semi-Permanently or Non-Volatile Permanently.
For additional information and collateral request, please contact your filed representative.

9.7.3 OTP Protection Registers


J3 v. D includes a 128-bit Protection Register (PR) that can be used to increase the security of a
system design. For example, the number contained in the PR can be used to “match” the flash
component with other system components such as the CPU or ASIC, hence preventing device
substitution.

The 128-bits of the PR are divided into two 64-bit segments:


• One segment is programmed at the Intel factory with a unique unalterable 64-bit number.
• The other segment is left blank for customer designers to program as desired. Once the
customer segment is programmed, it can be locked to prevent further programming.

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9.7.4 Reading the OTP Protection Register


The Protection Register is read in Identification Read mode. The device is switched to this mode by
issuing the Read Identifier command (0090h). Once in this mode, read cycles from addresses
shown in Table 31 or Table 32 retrieve the specified information. To return to Read Array mode,
write the Read Array command (00FFh).

9.7.5 Programming the OTP Protection Register


Protection Register bits are programmed using the two-cycle Protection Program command. The
64-bit number is programmed 16 bits at a time for word-wide configuration and eight bits at a time
for byte-wide configuration. First write the Protection Program Setup command, 00C0h. The next
write to the device will latch in address and data and program the specified location. The allowable
addresses are shown in Table 31, “Word-Wide Protection Register Addressing” on page 49 or
Table 32, “Byte-Wide Protection Register Addressing” on page 50. See Figure 24, “Protection
Register Programming Flowchart” on page 61. Any attempt to address Protection Program
commands outside the defined PR address space will result in a Status Register error (SR.4 will be
set). Attempting to program a locked PR segment will result in a Status Register error (SR.4 and
SR.1 will be set).

9.7.6 Locking the OTP Protection Register


The user-programmable segment of the Protection Register is lockable by programming Bit 1 of
the Protection Lock Register (PLR) to 0. Bit 0 of this location is programmed to 0 at the Intel
factory to protect the unique device number. Bit 1 is set using the Protection Program command to
program “0xFFFD” to the PLR. After these bits have been programmed, no further changes can be
made to the values stored in the Protection Register. Protection Program commands to a locked
section will result in a Status Register error (SR.4 and SR.1 will be set). PR lockout state is not
reversible.
Figure 15. Protection Register Memory Map

A[24:1]: 256 Mbit A[22:1]: 64 Mbit


Word
Address A[23:1]: 128 Mbit A[21:1]: 32 Mbit

0x88
64-bit Segment
(User-Programmable)
0x85
128-Bit Protection Register 0
0x84
64-bit Segment
(Factory-Programmed)
0x81
Lock Register 0
0x80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NOTE: A0 is not used in x16 mode when accessing the protection register map. See Table 31 for x16
addressing. If x8 mode A0 is used, see Table 32 for x8 addressing.

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Table 31. Word-Wide Protection Register Addressing


Word Use A8 A7 A6 A5 A4 A3 A2 A1

LOCK Both 1 0 0 0 0 0 0 0
0 Factory 1 0 0 0 0 0 0 1
1 Factory 1 0 0 0 0 0 1 0
2 Factory 1 0 0 0 0 0 1 1
3 Factory 1 0 0 0 0 1 0 0
4 User 1 0 0 0 0 1 0 1
5 User 1 0 0 0 0 1 1 0
6 User 1 0 0 0 0 1 1 1
7 User 1 0 0 0 1 0 0 0
NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register
(i.e., A[MAX:9] = 0.)

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Table 32. Byte-Wide Protection Register Addressing


Byte Use A8 A7 A6 A5 A4 A3 A2 A1 A0

LOCK Both 1 0 0 0 0 0 0 0 0
LOCK Both 1 0 0 0 0 0 0 0 1
0 Factory 1 0 0 0 0 0 0 1 0
1 Factory 1 0 0 0 0 0 0 1 1
2 Factory 1 0 0 0 0 0 1 0 0
3 Factory 1 0 0 0 0 0 1 0 1
4 Factory 1 0 0 0 0 0 1 1 0
5 Factory 1 0 0 0 0 0 1 1 1
6 Factory 1 0 0 0 0 1 0 0 0
7 Factory 1 0 0 0 0 1 0 0 1
8 User 1 0 0 0 0 1 0 1 0
9 User 1 0 0 0 0 1 0 1 1
A User 1 0 0 0 0 1 1 0 0
B User 1 0 0 0 0 1 1 0 1
C User 1 0 0 0 0 1 1 1 0
D User 1 0 0 0 0 1 1 1 1
E User 1 0 0 0 1 0 0 0 0
F User 1 0 0 0 1 0 0 0 1
NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register,
i.e., A[MAX:9] = 0.

9.7.7 VPP/ VPEN Protection


When it’s necessary to protect the entire array, global protection can be achieved using a hardware
mechanism. using VPP or VPEN. Whenever a valid voltage is present on VPP or VPEN, blocks
within the main flash array can be erased or programmed. By grounding VPP or VPEN, blocks
within the main array cannot be altered – attempts to program or erase blocks will fail resulting in
the setting of the appropriate error bit in the Status Register. By holding VPP or VPEN low,
absolute write protection of all blocks in the array can be achieved.

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Appendix A Device Command Codes


For a complete definition on device operations refer to Section 8.4, “Device Commands” on
page 36. The list of all applicable commands are included here one more time for the conveninece.

Table 33. Command Bus Operations for J3 v. D


Setup Write Cycle Confirm Write Cycle
Command
Address Bus Data Bus Address Bus Data Bus

Program Enhanced Configuration Register Register Data 0060h Register Data 0004h
Registers

Program OTP Register Device Address 00C0h Register Offset Register Data
Clear Status Register Device Address 0050h --- ---
Program STS Configuration Register Device Address 00B8h --- ---
Read Array Device Address 00FFh --- ---
Read Modes

Read Status Register Device Address 0070h --- ---


Read Identifier Codes (Read Device Information) Device Address 0090h --- ---
CFI Query Device Address 0098h --- ---
0040h/
Program and Erase

Word/Byte Program Device Address Device Address Array Data


0010h
Buffered Program Word Address 00E8h Device Address 00D0h
Block Erase Device Address 0020h Block Address 00D0h
Program/Erase Suspend Device Address 00B0h --- ---
Program/Erase Resume Device Address 00D0h --- ---
Lock Block Block Address 0060h Block Address 0001h
Security

Unlock Block Block Address 0060h Block Address 00D0h

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Appendix B J3 v. D ID Codes

Table 34. Read Identifier Codes


Code Address Data

32-Mbit 00001 0016


Device Code 64-Mbit 00001 0017
128-Mbit 00001 0018

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Appendix C Flow Charts

C.1 Write to Buffer

Figure 16. Write to Buffer Flowchart

Start

Setup
- Write 0xE8
- Block Address

Check Buffer Status


- Perform read operation
- Read Ready Status on signal SR7

No
SR7 = 1?

Yes

Word Count
- Address = block address
- Data = word count minus 1
(Valid range = 0x00 to0x1F)

Load Buffer
- Fill write buffer up to word count
- Address = within buffer range
- Data = user data

Confirm
- Write 0xD0
- Block address

Read Status
Register (SR)

No
SR7 = 1?

Yes

Full Status Register


Check
(if desired)

End

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C.2 Status Register


Figure 17. Status Register Flowchart

Start

Command Cycle
- Issue Status Register Command
- Address = any dev ice address
- Data = 0x70

Data Cycle
- Read Status Register SR[7:0]

No
SR7 = '1'

Y es

- Set/Reset Y es Erase Suspend


SR6 = '1'
by WSM See Suspend/Resume Flowchart

No

Y es Program Suspend
SR2 = '1'
See Suspend/Resume Flowchart

No

Y es Y es Error
SR5 = '1' SR4 = '1'
Command Sequence

No No

Error
Erase Failure

Y es Error
SR4 = '1'
Program Failure

No
- Set by WSM
- Reset by user
- See Clear Status
Register Y es Error
Command SR3 = '1'
V PEN < VPENLK

No

Y es Error
SR1 = '1'
Block Locked

No

End

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C.3 Byte/Word Programming


Figure 18. Byte/Word Program Flowchart

Start Bus
Command Comments
Operation

Write 40H, Setup Byte/ Data = 40H


Write
Word Program Addr = Location to Be Programmed
Address
Byte/Word Data = Data to Be Programmed
Write
Program Addr = Location to Be Programmed
Write Data and
Address Read
Status Register Data
(Note 1)

Check SR.7
Read Status
Standby 1 = WSM Ready
Register 0 = WSM Busy

1. Toggling OE# (low to high to low) updates the status register. This
0 can be done in place of issuing the Read Status Register command.
SR.7 = Repeat for subsequent programming operations.

1 SR full status check can be done after each program operation, or


after a sequence of programming operations.
Full Status
Check if Desired Write FFH after the last program operation to place device in read
array mode.

Byte/Word
Program Complete

FULL STATUS CHECK PROCEDURE


Bus
Read Status Command Comments
Operation
Register Data
Check SR.3
(See Above)
Standby 1 = Programming to Voltage Error
Detect
1
Check SR.1
SR.3 = Voltage Range Error 1 = Device Protect Detect
Standby RP# = V IH, Block Lock-Bit Is Set
0 Only required for systems
1 implemeting lock-bit configuration.

SR.1 = Device Protect Error Standby


Check SR.4
1 = Programming Error
0 Toggling OE# (low to high to low) updates the status register. This can
1 be done in place of issuing the Read Status Register command.
Repeat for subsequent programming operations.
SR.4 = Programming Error
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register
0 command in cases where multiple locations are programmed before
Byte/Word full status is checked.
Program If an error is detected, clear the status register before attempting retry
Successful or other error recovery.

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C.4 Program Suspend/Resume


Figure 19. Program Suspend/Resume Flowchart

Bus
Start Command Comments
Operation

Program Data = B0H


Write
Suspend Addr = X
Write B0H
Status Register Data
Read
Addr = X

Check SR.7
Standby 1 - WSM Ready
Read Status Register
0 = WSM Busy

Check SR.6
Standby 1 = Programming Suspended
0 0 = Programming Completed
SR.7 =
Data = FFH
Write Read Array
Addr = X
1
Read array locations other
0 Read
than that being programmed.
SR.2 = Programming Completed
Program Data = D0H
Write
Resume Addr = X
1

Write FFH

Read Data Array

No
Done Reading

Yes

Write D0H Write FFH

Programming Resumed Read Array Data

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C.5 Block Erase


Figure 20. Block Erase Flowchart

Bus
Start Command Comments
Operation
Data = 20H
Write Erase Block
Addr = Block Address
Erase Data = D0H
Write (Note 1)
Issue Single Block Erase Confirm Addr = Block Address
Command 20H, Block Status register data
Address With the device enabled,
Read
OE# low updates SR
Addr = X
Check SR.7
Standby 1 = WSM Ready
Write Confirm D0H 0 = WSM Busy
Block Address
1. The Erase Confirm byte must follow Erase Setup.
This device does not support erase queuing. Please see
Application note AP-646 For software erase queuing
compatibility.
Read
Status Register Full status check can be done after all erase and write
sequences complete. Write FFH after the last operation to
No reset the device to read array mode.

Suspend
Erase Loop
0 Yes
SR.7 = Suspend Erase

Full Status
Check if Desired

Erase Flash
Block(s) Complete

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C.6 Block Erase Suspend/Resume


Figure 21. Block Erase Suspend/Resume Flowchart

Bus
Start Command Comments
Operation

Data = B0H
Write Erase Suspend
Addr = X
Write B0H
Status Register Data
Read
Addr = X

Check SR.7
Standby 1 - WSM Ready
Read Status Register
0 = WSM Busy

Check SR.6
Standby 1 = Block Erase Suspended
0 0 = Block Erase Completed
SR.7 =
Data = D0H
Write Erase Resume
Addr = X
1

0
SR.6 = Block Erase Completed

1
Read Program
Read or Program?

Read Array Program


No
Data Loop

Done?

Yes

Write D0H Write FFH

Block Erase Resumed Read Array Data

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C.7 Block Locking


Figure 22. Set Block Lock-Bit Flowchart

Start Bus
Command Comments
Operation

Write 60H, Set Block Lock-Bit Data = 60H


Write
Block Address Setup Addr =Block Address

Set Block Lock-Bit Data = 01H


Write
Write 01H, Confirm Addr = Block Address
Block Address
Read Status Register Data

Read Status Register Check SR.7


Standby 1 = WSM Ready
0 = WSM Busy

0 Repeat for subsequent lock-bit operations.


SR.7 =
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations.
1
Full Status Write FFH after the last lock-bit set operation to place device in read
array mode.
Check if Desired

Set Lock-Bit Complete

FULL STATUS CHECK PROCEDURE

Read Status Register Bus


Command Comments
Data (See Above) Operation

Check SR.3
1 Standby 1 = Programming Voltage Error
Detect
SR.3 = Voltage Range Error
Check SR.4, 5
0 Standby Both 1 = Command Sequence
Error
1
Command Sequence
SR.4,5 = Standby
Check SR.4
Error 1 = Set Lock-Bit Error
0
SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register
1 command, in cases where multiple lock-bits are set before full status is
SR.4 = Set Lock-Bit Error checked.

0 If an error is detected, clear the status register before attempting retry


or other error recovery.
Set Lock-Bit
Successful

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C.8 Unlock Block


Figure 23. Clear Lock-Bit Flowchart

Start Bus
Command Comments
Operation

Clear Block Data = 60H


Write 60H Write
Lock-Bits Setup Addr = X

Clear Block or Data = D0H


Write
Lock-Bits Confirm Addr = X
Write D0H
Read Status Register Data

Read Status Register Check SR.7


Standby 1 = WSM Ready
0 = WSM Busy

0 Write FFH after the clear lock-bits operation to place device in read
SR.7 = array mode.

1
Full Status
Check if Desired

Clear Block Lock-Bits


Complete

FULL STATUS CHECK PROCEDURE


Bus
Read Status Register Command Comments
Operation
Data (See Above)
Check SR.3
Standby 1 = Programming Voltage Error
1 Detect
SR.3 = Voltage Range Error Check SR.4, 5
Standby Both 1 = Command Sequence
0 Error
1
Command Sequence Standby
Check SR.5
SR.4,5 = 1 = Clear Block Lock-Bits Error
Error
0 SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register
1 command.
Clear Block Lock-Bits
SR.5 = If an error is detected, clear the status register before attempting retry
Error
or other error recovery.
0
Clear Block Lock-Bits
Successful

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C.9 OTP Protection Register Programming


Figure 24. Protection Register Programming Flowchart

Start Bus Operation Command Comments

Protection Program
Write Data = C0H
Write C0H Setup
(Protection Reg.
Data = Data to Program
Program Setup) Write Protection Program
Addr = Location to Program

Status Register Data Toggle


Write Protect. Register Read CE# or OE# to Update Status
Address/Data Register Data

Check SR.7
Standby 1 = WSM Ready
Read Status Register 0 = WSM Busy

Protection Program operations can only be addressed within the protection


register address space. Addresses outside the defined space will return an
No error.
SR.7 = 1?
Repeat for subsequent programming operations.
Yes
SR Full Status Check can be done after each program or after a sequence of
Full Status program operations.
Check if Desired
Write FFH after the last program operation to reset device to read array mode.

Program Complete

FULL STATUS CHECK PROCEDURE

Read Status Register Bus Operation Command Comments


Data (See Above)
Standby SR.1 SR.3 SR.4
0 1 1 V PEN Low
1, 1
SR.3, SR.4 = VPEN Range Error Standby 0 0 1 Prot. Reg.
Prog. Error

1 0 1 Register
0,1 Standby Locked:
Protection Register Aborted
SR.1, SR.4 =
Programming Error
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
1,1 Attempted Program to
SR.1, SR.4 = Locked Register - SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases of multiple protection register program operations before full status is
Aborted checked.

If an error is detected, clear the status register before attempting retry or other
Program Successful error recovery.

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Appendix D Common Flash Interface


The Common Flash Interface(CFI) specification outlines device and host system software
interrogation handshake which allows specific vendor-specified software algorithms to be used for
entire families of devices. This allows device independent, JEDEC ID-independent, and forward-
and backward-compatible software support for the specified flash device families. It allows flash
vendors to standardize their existing interfaces for long-term compatibility.

This appendix defines the data structure or “database” returned by the Common Flash Interface
(CFI) Query command. System software should parse this structure to gain critical information
such as block size, density, x8/x16, and electrical specifications. Once this information has been
obtained, the software will know which command sets to use to enable flash writes, block erases,
and otherwise control the flash component. The Query is part of an overall specification for
multiple command set and control interface descriptions called Common Flash Interface, or CFI.

D.1 Query Structure Output


The Query “database” allows system software to gain information for controlling the flash
component. This section describes the device’s CFI-compliant interface that allows the host system
to access Query data.

Query data are always presented on the lowest-order data outputs (D[7:0]) only. The numerical
offset value is the address relative to the maximum bus width supported by the device. On this
family of devices, the Query table device starting address is a 10h, which is a word address for x16
devices.

For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R” in ASCII,
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H
data on upper bytes. Thus, the device outputs ASCII “Q” in the low byte (D[7:0]) and 00h in the
high byte (D[15:8]).

At Query addresses containing two or more bytes of information, the least significant data byte is
presented at the lower address, and the most significant data byte is presented at the higher address.

In all of the following tables, addresses and data are represented in hexadecimal notation, so the
“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always
“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is
shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.

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Table 35. Summary of Query Structure Output as a Function of Device and Mode
Query data with maximum Query data with byte
Device Query start location in device bus width addressing addressing
Type/ maximum device bus
Mode width addresses Hex Hex ASCII Hex Hex ASCII
Offset Code Value Offset Code Value
x16 device 10h 10: 0051 “Q” 20: 51 “Q”
x16 mode 11: 0052 “R” 21: 00 “Null”
12: 0059 “Y” 22: 52 “R”
x16 device 20: 51 “Q”
x8 mode N/A(1) N/A(1) 21: 51 “Q”
22: 52 “R”
NOTE:
1. The system must drive the lowest order addresses to access all the device's array data when the device is
configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the
system, is "Not Applicable" for x8-configured devices.

Table 36. Example of Query Structure Output of a x16- and x8-Capable Device
Word Addressing Byte Addressing
Offset Hex Code Value Offset Hex Code Value
A15–A0 D15–D0 A7–A 0 D7–D0
0010h 0051 “Q” 20h 51 “Q”
0011h 0052 “R” 21h 51 “Q”
0012h 0059 “Y” 22h 52 “R”
0013h P_IDLO PrVendor 23h 52 “R”
0014h P_IDHI ID # 24h 59 “Y”
0015h PLO PrVendor 25h 59 “Y”
0016h PHI TblAdr 26h P_IDLO PrVendor
0017h A_IDLO AltVendor 27h P_IDLO ID #
0018h A_IDHI ID # 28h P_IDHI ID #
... ... ... ... ... ...

D.2 Query Structure Overview


The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or “database.” The structure sub-sections and address locations are summarized
below. See AP-646 Common Flash Interface (CFI) and Command Sets (order number 292204) for
a full description of CFI.

The following sections describe the Query structure sub-sections in detail.

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Table 37. Query Structure


Offset Sub-Section Name Description Notes
00h Manufacturer Code 1
01h Device Code 1
(BA+2)h(2) Block Status Register Block-Specific Information 1,2
04-0Fh Reserved Reserved for Vendor-Specific Information 1
10h CFI Query Identification String Reserved for Vendor-Specific Information 1
1Bh System Interface Information Command Set ID and Vendor Data Offset 1
27h Device Geometry Definition Flash Device Layout 1
Primary Intel-Specific Extended Vendor-Defined Additional Information
P(3) 1,3
Query Table Specific to the Primary Vendor Algorithm
NOTES:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset
address as a function of device bus width and mode.
2. BA = Block Address beginning location (i.e., 02000h is block 2’s beginning location when the
block size is 128 Kbyte).
3. Offset 15 defines “P” which points to the Primary Intel-Specific Extended Query Table.

D.3 Block Status Register


The Block Status Register indicates whether an erase operation completed successfully or whether
a given block is locked or can be accessed for flash program/erase operations.

Table 38. Block Status Register


Offset Length Description Address Value
(1)
(BA+2)h 1 Block Lock Status Register BA+2: --00 or --01
BSR.0 Block Lock Status
0 = Unlocked BA+2: (bit 0): 0 or 1
1 = Locked
BSR 1–15: Reserved for Future Use BA+2: (bit 1–15): 0
NOTE:
1. BA = The beginning location of a Block Address (i.e., 008000h is block 1’s (64-KB block) beginning location
in word mode).

D.4 CFI Query Identification String


The CFI Query Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and supported
vendor-specified command set(s).

Table 39. CFI Identification (Sheet 1 of 2)


Hex
Offset Length Description Add. Value
Code
10 --51 “Q”
10h 3 Query-unique ASCII string “QRY” 11: --52 “R”
12: --59 “Y”
13h 2 Primary vendor command set and control interface ID code. 13: --01
16-bit ID code for vendor-specified algorithms 14: --00
15h 2 Extended Query Table primary algorithm address 15: --31
16: --00
17h 2 Alternate vendor command set and control interface ID code. 17: --00

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Table 39. CFI Identification (Sheet 2 of 2)


Hex
Offset Length Description Add. Value
Code
0000h means no second vendor-specified algorithm exists 18: --00
19h 2 Secondary algorithm Extended Query Table address. 19: --00
0000h means none exists 1A: --00

D.5 System Interface Information


The following device information can optimize system interface software.

Table 40. System Interface Information


Hex
Offset Length Description Add. Value
Code
VCC logic supply minimum program/erase voltage
1Bh 1 bits 0–3 BCD 100 mV 1B: --27 2.7 V
bits 4–7 BCD volts
VCC logic supply maximum program/erase voltage
1Ch 1 bits 0–3 BCD 100 mV 1C: --36 3.6 V
bits 4–7 BCD volts
VPP [programming] supply minimum program/erase voltage
1Dh 1 bits 0–3 BCD 100 mV 1D: --00 0.0 V
bits 4–7 HEX volts
VPP [programming] supply maximum program/erase voltage
1Eh 1 bits 0–3 BCD 100 mV 1E: --00 0.0 V
bits 4–7 HEX volts
1Fh 1 “n” such that typical single word program time-out = 2n µs 1F: --06 64 µs
20h 1 “n” such that typical max. buffer write time-out = 2n µs 20: --07 128 µs
21h 1 “n” such that typical block erase time-out = 2n ms 21: --0A 1s
22h 1 “n” such that typical full chip erase time-out = 2n ms 22: --00 NA
“n” such that maximum word program time-out = 2n times
23h 1 23: --02 256 µs
typical
24h 1 “n” such that maximum buffer write time-out = 2n times typical 24: --03 1024 µs
25h 1 “n” such that maximum block erase time-out = 2n times typical 25: --02 4s
26h 1 “n” such that maximum chip erase time-out = 2n times typical 26: --00 NA

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D.6 Device Geometry Definition


This field provides critical details of the flash device geometry.

Table 41. Device Geometry Definition


Code See Table
Offset Length Description
Below
27h 1 “n” such that device size = 2n in number of bytes 27:
x8/
28h 2 Flash device interface: x8 async x16 async x8/x16 async 28: --02
x16
28:00,29:00 28:01,29:00 28:02,29:00 29: --00
2Ah 2 “n” such that maximum number of bytes in write buffer = 2n 2A: --05 32
2B: --00
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions with one or
2Ch 1 2C: --01 1
more contiguous same-size erase blocks
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
Erase Block Region 1 Information 2D:
bits 0–15 = y, y+1 = number of identical-size erase blocks 2E:
2Dh 4
bits 16–31 = z, region erase block(s) size are z x 256 bytes 2F:
30:

Device Geometry Definition

Address 32 Mbit 64 Mbit 128 Mbit


27: --16 --17 --18
28: --02 --02 --02
29: --00 --00 --00
2A: --05 --05 --05
2B: --00 --00 --00
2C: --01 --01 --01
2D: --1F --3F --7F
2E: --00 --00 --00
2F: --00 --00 --00
30: --02 --02 --02

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D.7 Primary-Vendor Specific Extended Query Table


Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query
table specifies this and other similar information.

Table 42. Primary Vendor-Specific Extended Query


Offset (1) Description Hex
Length Add. Value
P = 31h (Optional Flash Features and Commands) Code
(P+0)h 3 Primary extended query table 31: --50 “P”
(P+1)h Unique ASCII string “PRI” 32: --52 “R”
(P+2)h 33: --49 “I”
(P+3)h 1 Major version number, ASCII 34: --31 “1”
(P+4)h 1 Minor version number, ASCII 35: --31 “1”
Optional feature and command support (1=yes, 0=no) 36: --CE
bits 9–31 are reserved; undefined bits are “0.” If bit 31 is 37: --00
“1” then another 31 bit field of optional features follows at 38: --00
the end of the bit-30 field. 39: --00
bit 0 Chip erase supported bit 0 = 0 No
(P+5)h bit 1 Suspend erase supported bit 1 = 1 Yes
(P+6)h
4 bit 2 Suspend program supported bit 2 = 1 Yes
(P+7)h
(P+8)h bit 3 Legacy lock/unlock supported bit 3 = 1(1) Yes(1)
bit 4 Queued erase supported bit 4 = 0 No
bit 5 Instant Individual block locking supported bit 5 = 0 No
bit 6 Protection bits supported bit 6 = 1 Yes
bit 7 Page-mode read supported bit 7 = 1 Yes
bit 8 Synchronous read supported bit 8 = 0 No
Supported functions after suspend: read Array, Status,
Query
3A: --01
(P+9)h 1 Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
bit 0 Program supported after erase suspend bit 0 = 1 Yes
Block Status Register mask 3B: --01
(P+A)h bits 2–15 are Reserved; undefined bits are “0” 3C: --00
2
(P+B)h bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes
bit 1 Block Lock-Down Bit Status active bit 1 = 0 No
VCC logic supply highest performance program/erase
voltage
(P+C)h 1 3D: --33 3.3 V
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
VPP optimum program/erase supply voltage
(P+D)h 1 bits 0–3 BCD value in 100 mV 3E: --00 0.0 V
bits 4–7 HEX value in volts
NOTE:
1. Future devices may not support the described “Legacy Lock/Unlock” function. Thus bit 3 would have a
value of “0.”

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Table 43. Protection Register Information


Offset(1) Description Hex
Length Add. Value
P = 31h (Optional Flash Features and Commands) Code
Number of Protection register fields in JEDEC ID space.
(P+E)h 1 3F: --01 01
“00h,” indicates that 256 protection bytes are available
Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) protection register bytes. Some are pre-programmed
40: --80 80h
with device-unique serial numbers. Others are user-
(P+F)h programmable. Bits 0-15 point to the protection register lock 41: --00 00h
(P+10)h byte, the section’s first byte. The following bytes are factory
4 42: --03 8bytes
(P+11)h pre-programmed and user-programmable.
(P+12)h 43: --03 8bytes
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bits 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = “n” such that 2n = factory pre-programmed bytes
bits 24-31 = “n” such that 2n = user-programmable bytes
NOTE:
1. The variable P is a pointer which is defined at CFI offset 15h.

Table 44. Burst Read Information


Offset(1) Description Hex
Length Add. Value
P = 31h (Optional Flash Features and Commands) Code
Page Mode Read capability
bits 0–7 = “n” such that 2n HEX value represents the number
(P+13)h 1 of read-page bytes. See offset 28h for device word width to 44: --03 8 byte
determine page-mode data output width. 00h indicates no
read page buffer.
Number of synchronous mode read configuration fields that
(P+14)h 1 45: --00 0
follow. 00h indicates no burst capability.
(P+15)h Reserved for future use 46:
NOTE:
1. The variable P is a pointer which is defined at CFI offset 15h.

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Appendix E Additional Information

Order Number Document/Tool

Intel® StrataFlash™ Memory (J3); 28F128J3, 28F640J3, 28F320J3


298130
Specification Update
298136 Intel® Persistent Storage Manager (IPSM) User’s Guide Software Manual
297833 Intel® Flash Data Integrator (FDI) User’s Guide Software Manual
290606 5 Volt Intel® StrataFlash™ MemoryI28F320J5 and 28F640J5 datasheet
292204 AP-646 Common Flash Interface (CFI) and Command Sets
253418 Intel® Wireless Communications and Computing Package User’s Guide
1. Call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers
should contact their local Intel or distribution sales office.
2. Visit the Intel home page http://www.intel.com for technical documentation and tools.
3. For the most current information on Intel® Embedded Flash Memory (J3 v. D), visit http://
developer.intel.com/design/flash/isf.

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Appendix F Ordering Information

Figure 25. Decoder:Intel® Embedded Flash Memory (J3 v. D) Family

P C2 8 F 3 2 0 J 3 D - 7 5
Package
Access Speed
TE= 56-Lead TSOP (J3C, 803)
75 ns
JS = Pb-Free 56-TSOP
RC = 64-Ball Easy BGA
D = Intel® 0.13
PC = 64-Ball Pb-Free Easy BGA micron lithography

Voltage (Vcc/VPEN)
Product line designator 3 = 3 V/3 V
For all Intel® Flash Products
Product Family
J = Intel® Embedded Flash Memory

Device Density
128 = x8/x16 (128 Mbit)
640 = x8/x16 (64 Mbit)
320 = x8/x16 (32 Mbit)

Table 45. Order Information: Intel® Embedded Flash Memory (J3 v. D) Family
56-Lead TSOP 64-Ball Easy BGA

TE28F128J3D-75 RC28F128J3D-75
TE28F640J3D-75 RC28F640J3D-75
TE28F320J3D-75 RC28F320J3D-75
JS28F128J3D-75 PC28F128J3D-75
JS28F640J3D-75 PC28F640J3D-75
JS28F320J3D-75 PC28F320J3D-75

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1.0 Introduction ............................................................................................................. 6


1.1 Nomenclature .................................................................................................. 6
1.2 Acronyms ........................................................................................................ 6
1.3 Conventions .................................................................................................... 6
2.0 Functional Overview ............................................................................................8
2.1 Block Diagram ............................................................................................... 10
2.2 Memory Map ................................................................................................. 11
3.0 Package Information ......................................................................................... 12
3.1 56-Lead TSOP Package ............................................................................... 12
3.2 Easy BGA Package....................................................................................... 13
4.0 Ballouts and Signal Descriptions................................................................. 15
4.1 Easy BGA Ballout (32/64/128 Mbit)............................................................... 15
4.2 56-Lead TSOP Package Pinout (32/64/128 Mbit) ......................................... 16
4.3 Signal Descriptions........................................................................................ 17
5.0 Maximum Ratings and Operating Conditions ......................................... 19
5.1 Absolute Maximum Ratings........................................................................... 19
5.2 Operating Conditions..................................................................................... 19
5.3 Power Up/Down ............................................................................................ 20
5.3.1 Power-Up/Down Characteristics ...................................................... 20
5.3.2 Power Supply Decoupling ................................................................ 20
5.4 Reset ............................................................................................................. 20
6.0 Electrical Characteristics ................................................................................ 21
6.1 DC Current Specifications ............................................................................. 21
6.2 DC Voltage specifications ............................................................................. 22
6.3 Capacitance .................................................................................................. 23
7.0 AC Characteristics ............................................................................................. 24
7.1 Read Specifications....................................................................................... 25
7.2 Write Specifications....................................................................................... 28
7.3 Program, Erase, Block-Lock Specifications .................................................. 30
7.4 Reset Specifications ...................................................................................... 31
7.5 AC Test Conditions ....................................................................................... 32
8.0 Bus Interface......................................................................................................... 33
8.1 Bus Reads..................................................................................................... 34
8.1.1 Asynchronous Page Mode Read...................................................... 34
8.1.1.1 Enhanced Configuration Register (ECR) ............................ 34
8.1.2 Output Disable.................................................................................. 35
8.2 Bus Writes ..................................................................................................... 35
8.3 Standby ......................................................................................................... 36
8.3.1 Reset/Power-Down .......................................................................... 36
8.4 Device Commands ........................................................................................ 36
9.0 Flash Operations.................................................................................................38
9.1 Status Register.............................................................................................. 38
9.1.1 Clearing the Status Register ............................................................ 39

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9.2 Read Operations ............................................................................................39


9.2.1 Read Array ........................................................................................39
9.2.2 Read Status Register ........................................................................40
9.2.3 Read Device Information...................................................................40
9.2.4 CFI Query..........................................................................................41
9.3 Programming Operations ...............................................................................41
9.3.1 Single-Word/Byte Programming........................................................41
9.3.2 Buffered Programming ......................................................................42
9.4 Block Erase Operations .................................................................................43
9.5 Suspend and Resume....................................................................................44
9.6 Status Signal (STS)........................................................................................45
9.7 Security and Protection ..................................................................................46
9.7.1 Normal Block Locking .......................................................................46
9.7.2 Configurable Block Locking...............................................................47
9.7.3 OTP Protection Registers .................................................................47
9.7.4 Reading the OTP Protection Register ...............................................48
9.7.5 Programming the OTP Protection Register.......................................48
9.7.6 Locking the OTP Protection Register ................................................48
9.7.7 VPP/ VPEN Protection ......................................................................50
Appendix A Device Command Codes ................................................................................. 51
Appendix B J3 v. D ID Codes .................................................................................................. 52
Appendix C Flow Charts ........................................................................................................... 53
C.1 Write to Buffer ................................................................................................53
C.2 Status Register...............................................................................................54
C.3 Byte/Word Programming ................................................................................55
C.4 Program Suspend/Resume ............................................................................56
C.5 Block Erase ....................................................................................................57
C.6 Block Erase Suspend/Resume ......................................................................58
C.7 Block Locking .................................................................................................59
C.8 Unlock Block ..................................................................................................60
C.9 OTP Protection Register Programming..........................................................61
Appendix D Common Flash Interface ................................................................................. 62
D.2 Query Structure Overview ..............................................................................63
D.3 Block Status Register .....................................................................................64
D.4 CFI Query Identification String .......................................................................64
D.5 System Interface Information .........................................................................65
D.6 Device Geometry Definition ...........................................................................66
D.7 Primary-Vendor Specific Extended Query Table ...........................................67
Appendix E Additional Information ...................................................................................... 69
Appendix F Ordering Information ......................................................................................... 70

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