Vidya vikas Institute of Engineering and Technology, Mysuru

Information Science and Engineering Lateral Entry Students 21IS33 CIE (theory) Marks 2022-23
Marks Allotted 20 20 20 20(A) 10(B) 30(A+B)
Sl. No USN Average Average of
STUDENT NAME IA-1 IA-2 IA-3 Total
(IA-1,IA-2, IA-3) Assignments
1 4VM22IS APOORVA G C 15 17 17 16 7 23
2 4VM22IS DANESHWARI HALBHARI 10 9 17 12 9 21
3 4VM22IS DARSHAN H A 10 12 17 13 8 21
4 4VM22IS GAGAN T M 13 10 17 13 7 20
5 4VM22IS JNANA Y T 11 15 19 15 8 23
6 4VM22IS MAHESH CHANDRU C 11 13 18 14 8 22
7 4VM22IS MANIKANT VIJAYKUMAR4 HOLLI 13 9 17 13 8 21
8 4VM22IS MANOJ N R 5 14 17 12 8 20
9 4VM22IS ROHITH Y 10 14 19 14 8 22
10 4VM22IS SHIVARAJA PATEEL V S 13 17 18 16 8 24
11 4VM22IS SUNIL KUMAR D 15 14 16 15 7 22
12 4VM22IS THILAK G 9 15 18 14 9 23
13 4VM22IS UDAY M B 11 13 17 14 8 22
14 4VM22IS VENU GOPAL K S 15 13 17 15 8 23
15 4VM22IS VINOD KUMAR H M 11 12 17 13 8 21
16 4VM22IS YASHWANTHAKUMAR S 9 10 17 12 7 19
 VIDYA VIKAS INSTITUTE OF ENGINEERING AND TECHNOLOGY,MYSOR
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
CO ATTAINMENT CIE, 2022-2023 (ODD SEMESTER)

Course Outcome Statements

CO Numer Statement
C201.1 CO1: Design and analyze application of analog circuits usi
and op-amp.
C201.2 CO2: Explain the basic principles of A/D and D/A convers
C201.3 CO3: Simplify digital circuits using Karnaugh Map, and Qu
C201.4 CO4: Explain Gates and flip flops and make us in designin
C201.5 CO5: Develop simple HDL programs

CIE I IA
II IA

CO's CO3 CO3 CO2 CO2 CO3 CO3

CO4 CO4
Final
PO's PO2 PO2 PO2 PO2 PO2 PO2 Tota mar PO2 PO2
l
ks

Questions Q1 Q2 Q3 Q4 Q5 Q6 Q1 Q2

Marks Allotted 10 10 10 10 10 10 30 20 10 10
Sl. No USN STUDENT NAME
1 4VM22IS APOORVA G C 7 9 6 22 14.7 9

2 4VM22IS DANESHWARI HALBHARI 3 4 8 15 10 5

3 4VM22IS DARSHAN H A 5 5 5 15 10 10 6
4 4VM22IS GAGAN T M 9 7 3 19 12.7 10
5 4VM22IS JNANA Y T 5 6 4 5 16 10.7 9

6 4VM22IS MAHESH CHANDRU C 6 5 6 4 16 10.7 8

7 4VM22IS MANIKANT VIJAYKUMAR4 HOLLI 7 8 4 19 12.7 5
8 4VM22IS MANOJ N R 4 3 3 7 4.67 10
9 4VM22IS ROHITH Y 6 3 6 15 10 9

10 4VM22IS SHIVARAJA PATEEL V S 7 8 5 20 13.3 9

11 4VM22IS SUNIL KUMAR D 7 9 7 23 15.3 7

12 4VM22IS THILAK G 9 5 3 14 9.33 8

13 4VM22IS UDAY M B 3 7 6 16 10.7 6

14 4VM22IS VENU GOPAL K S 9 6 7 22 14.7 6

15 4VM22IS VINOD KUMAR H M 6 6 3 7 16 10.7 10

16 4VM22IS YASHWANTHAKUMAR S 5 4 4 13 8.67 6

17 4VM22IS YOGESHWARAYA B S
ND TECHNOLOGY,MYSORE
NICATION ENGINEERING
ODD SEMESTER)

ent S
tion of analog circuits using photo devices, timer IC, power supply and regulator IC
s of A/D and D/A conversion circuits and develop the same.
ng Karnaugh Map, and Quine-McClusky Methods
and make us in designing different data processing circuits, registers and counters
ms

III IA
II IA CO1 C05
CO4 CO4 CO4 CO4 CO4 CO4 CO4 CO4 CO4 CO4 Average (IA-1,IA-
Final 2, IA-3)
PO2 PO2 PO2 PO2 Tota mar PO3 PO3 PO3 PO3 PO2 PO2 Tota Final marks PO2 PO2
l l
ks
Q3 Q4 Q5 Q6 Q1 Q2 Q3 Q4 Q5 Q6 Assg-1 Assg-2

10 10 10 10 30 20 10 10 10 10 10 10 30 20 20(A) 10 10

9 8 26 17 7 8 10 25 16.6666666667 16 7 8
5 3 13 8.67 7 9 10 26 17.3333333333 12 10 8
8 18 12 7 9 10 26 17.3333333333 13 7 10
5 15 10 7 9 10 26 17.3333333333 13 7 8
9 4 22 15 8 10 10 28 18.6666666667 15 8 10
8 4 20 13 8 9 10 27 18 14 7 9
5 4 14 9.33 8 8 10 26 17.3333333333 13 7 8
6 5 21 14 8 8 9 25 16.6666666667 12 8 8
6 6 21 14 9 9 10 28 18.6666666667 14 7 8
10 7 26 17 8 9 10 27 18 16 8 7
7 7 21 14 6 8 10 24 16 15 8 6
7 7 22 15 9 8 10 27 18 14 9 9
7 7 20 13 7 8 10 25 16.6666666667 14 8 9
6 7 19 13 8 8 10 26 17.3333333333 15 8 10
4 4 18 12 8 8 7 23 15.3333333333 13 8 8
4 5 15 10 7 8 10 25 16.6666666667 12 8 7
CO4
Average
of
Assgnme total
PO2 nt

Assg-3

10(B)
10 30(A+B)

7 7 23.6
8 9 20.666667
7 8 21.111111
6 7 20.333333
7 8 23
8 8 22
9 8 21.111111
8 8 19.777778
8 8 21.888889
8 8 23.888889
7 7 22.111111
8 9 22.666667
7 8 21.555556
7 8 23.222222
7 8 20.333333
7 7 19.111111