STA508

40V 4.5A QUAD POWER HALF BRIDGE

1 FEATURES Figure 1. Package

■ MULTIPOWER BCD TECHNOLOGY
■ MINIMUM INPUT OUTPUT PULSE WIDTH
DISTORTION PowerSO36
■ 200mΩ RdsON COMPLEMENTARY DMOS
OUTPUT STAGE
Table 1. Order Codes
■ CMOS COMPATIBLE LOGIC INPUTS
Part Number Package
■ THERMAL PROTECTION
STA508 PowerSO36
■ THERMAL WARNING OUTPUT
■ UNDER VOLTAGE PROTECTION
The device is particularly designed to make the out-
2 DESCRIPTION put stage of a stereo All-Digital High Efficiency
(DDX™) amplifier capable to deliver 80 + 80W @
STA508 is a monolithic quad half bridge stage in Mul- THD = 10% at Vcc 35V output power on 8Ω load.
tipower BCD Technology. The device can be used as
In single BTL configuration is also capable to deliver
dual bridge or reconfigured, by connecting CONFIG
pin to Vdd pin, as single bridge with double current a peak of 160W @THD = 10% at VCC = 35V on 4Ω
capability, and as half bridge (Binary mode) with half load (t ≤1sec). The input pins have threshold propor-
current capability. tional to Ibias pin voltage.

Figure 2. Block Diagram

VCC1A +VCC

15
IN1A 29 M3 C30 C55
IN1A 1µF 1000µF
17 L18 22µH
VL 23
+3.3V OUT1A
CONFIG 24 16 C20
100nF
OUT1A
PWRDN PWRDN 25 M2 C52
14 GND1A 330pF R98 C99
PROTECTIONS 6 100nF
R57 R59 FAULT 27 & C23 8Ω
10K 10K LOGIC
26 12 VCC1B 470nF
R63 R100 C101
TRI-STATE
C58 M5 C31 20 6 100nF
100nF 11 1µF
C21
TH_WAR 28 OUT1B 100nF
TH_WAR 10
IN1B 30 OUT1B L19 22µH
IN1B
M4
VDD 21 13 GND1B
VDD 22
VSS 33 REGULATORS
7 VCC2A
VSS 34
M17 C32
C58 C53 1µF
100nF 100nF VCCSIGN 8 L113 22µH
35
OUT2A
C60 9 C110
100nF VCCSIGN 100nF
36 OUT2A
M15 C109
IN2A 6 GND2A 330pF R103 C107
IN2A 31 6 100nF
GND-Reg C108 8Ω
20 4 VCC2B 470nF
R104 R102
GND-Clean C106
C33 20 6
19 M16 100nF
3 1µF
C111
OUT2B 100nF
IN2B 2
IN2B 32
OUT2B L112 22µH
GNDSUB M14
1 5 GND2B

D00AU1148B

REV. 2
June 2004 1/10
STA508

Table 2. Pin Description

N° Pin Description

1 GND-SUB Substrate Ground

2;3 OUT2B Output Half Bridge 2B

4 VCC 2B Positive Supply

5 GND2B Negative Supply

6 GND2A Negative Supply

7 VCC 2A Positive Supply

8;9 OUT2A Output Half Bridge 2A

10 ; 11 OUT1B Output Half Bridge 1B

12 VCC1B Positive Supply

13 GND1B Negative Supply

14 GND1A Negative Supply

15 VCC1A Positive Supply

16 ; 17 OUT1A Output Half Bridge 1A

18 NC Not Connected

19 GND-clean Logical Ground

20 GND-Reg Ground for Regulator Vdd

21 ; 22 Vdd 5V Regulator Referred to Ground

23 VL High Logical State Setting Voltage

24 CONFIG Configuration pin

25 PWRDN Stand-by pin

26 TRI-STATE Hi-Z pin

27 FAULT Fault pin Advisor

28 TH-WAR Thermal Warning Advisor

29 IN1A Input of Half Bridge 1A

30 IN1B Input of Half Bridge 1B

31 IN2A Input of Half Bridge 2A

32 IN2B Input of Half Bridge 2B

33 ; 34 VSS 5V Regulator Referred to +VCC

35 ; 36 VCC Sign Signal Positive Supply

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 STA508

Table 3. FUNCTIONAL PIN STATUS

PIN NAME Logical value IC -STATUS
FAULT 0 Fault detected (Short circuit, or Thermal ..)

FAULT (*) 1 Normal Operation

TRI-STATE 0 All powers in Hi-Z state

TRI-STATE 1 Normal operation
PWRDN 0 Low absorpion
PWRDN 1 Normal operation
THWAR 0 Temperature of the IC =130°C

THWAR(*) 1 Normal operation

CONFIG 0 Normal Operation

CONFIG(**) 1 OUT1A = OUT1B ; OUT2A=OUT2B

(IF IN1A = IN1B; IN2A = IN2B)
(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
(**): To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)

Figure 3. PIN CONNECTION

VCCSign 36 1 GND-SUB
VCCSign 35 2 OUT2B
VSS 34 3 OUT2B
VSS 33 4 VCC2B
IN2B 32 5 GND2B
IN2A 31 6 GND2A
IN1B 30 7 VCC2A
IN1A 29 8 OUT2A
TH_WAR 28 9 OUT2A
FAULT 27 10 OUT1B
TRI-STATE 26 11 OUT1B
PWRDN 25 12 VCC1B
CONFIG 24 13 GND1B
VL 23 14 GND1A
VDD 22 15 VCC1A
VDD 21 16 OUT1A
GND-Reg 20 17 OUT1A
GND-Clean 19 18 N.C.

D01AU1273

Table 4. THERMAL DATA

Symbol Description Value Unit

Rth j-case Thermal Resistance Junction-case max 1.5 °C/W

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STA508

Table 5. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VCE DC Supply Voltage (Pin 4,7,12,15) 40 V

Vmax Maximum Voltage on pins 23 to 32 5.5 V

Ptot Power Dissipation (Tcase = 70°C) 50 W

Top Operating Temperature Range 0 to 70 °C

Tstg, Tj Storage and Junction Temperature -40 to 150 °C

Table 6. ELECTRICAL CHARACTERISTCS (VL = 3.3V; VCC = 30V; Tamb = 25°C ; fsw =384 unless
otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit

RdsON Power Pchannel/Nchannel Id=1A 200 270 mΩ

MOSFET RdsON

Idss Power Pchannel/Nchannel VCC =35V 50 µA

leakage Idss

gN Power Pchannel RdsON Id=1A 95 %

Matching

gP Power Nchannel RdsON Id=1A 95 %

Matching

Dt_s Low current Dead Time (static) see test circuit no.1; see fig. 4 10 20 ns

Dt_d High current Dead Time (dinamic) L=22µH; C = 470nF; RL = 8 Ω 50 ns

Id=3.5A; see fig. 3

td ON Turn-on delay time Resistive load 100 ns

td OFF Turn-off delay time Resistive load 100 ns

tr Rise time Resistive load; as fig.4 25 ns

tf Fall time Resistive load; as fig. 4 25 ns

VCC Supply voltage operating voltage 9 36 V

VIN-High High level input voltage VL/2 V

+300mV

VIN-Low Low level input voltage VL/2 - V

300mV

IIN-High High level Input current Pin Voltage = VL 1 µA

IIN-Low Low level input current Pin Voltage = 0.3V 1 µA

IPWRDN-H High level PWRDN pin input VL = 3.3V 35 µA

current

VL Low logical state voltage VL (pin VL = 3.3V 0.8 V

PWRDN, TRISTATE) (note 1)

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 STA508

Table 6. ELECTRICAL CHARACTERISTCS (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

VH High logical state voltage VH (pin VL = 3.3V 1.7 V

PWRDN, TRISTATE) (note 1)

IVCC- Supply CURRENT from Vcc in PWRDN = 0 3 mA

PWRDN Power Down

IFAULT Output Current pins

FAULT -TH-WARN when Vpin = 3.3V 1 mA
FAULT CONDITIONS

IVCC-hiz Supply Current from Vcc in Tri- VCC = 30V; Tri-state = 0 22 mA

state

IVCC Supply Current from Vcc in VCC =30V; 50 mA

operation Input Pulse width = 50% Duty;
both channel switching) Switching Frequency = 384KHz;
No LC filters;

IVCC-q Isc (short circuit current limit) 4.5 6 9 A

(note 2)

VOUT-SH Undervoltage protection threshold 7 V

VOV Output minimum pulse width No Load 70 150 ns

Table 7.
Notes: 1. The following table explains the VLow, VHigh variation with Ibias

VL VLow min VHigh max Unit

2.7 0.7 1.5 V

3.3 0.8 1.7 V

5 0.85 1.85 V

Note 2: See relevant Application Note AN1994

Table 8. LOGIC TRUTH TABLE (see fig. 5)

OUTPUT
TRI-STATE INxA INxB Q1 Q2 Q3 Q4
MODE

0 x x OFF OFF OFF OFF Hi-Z

1 0 0 OFF OFF ON ON DUMP

1 0 1 OFF ON ON OFF NEGATIVE

1 1 0 ON OFF OFF ON POSITIVE

1 1 1 ON ON OFF OFF Not used

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STA508

Figure 4. Test Circuit.

OUTxY
Vcc

(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc

(1/4)Vcc
+Vcc

t
Duty cycle = 50% DTr DTf
M58
OUTxY R 8Ω
INxY

M57 +
-
V67 =
vdc = Vcc/2
gnd
D03AU1458

Figure 5.

+VCC

Q1 Q2
OUTxA OUTxB
INxA INxB

Q3 Q4

GND
D00AU1134

Figure 6.

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

+VCC

Duty cycle=A Duty cycle=B

DTout(A)

M58 Q1 Q2 M64
DTin(A) DTout(B) DTin(B)
OUTA Rload=8Ω OUTB
INA INB
L67 22µ L68 22µ
Iout=4A Iout=4A
M57 Q3 C69 C70 Q4 M63
470nF C71 470nF 470nF

Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure D03AU1517

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 STA508

Figure 7. Typical Single BTL Configuration

VL
+3.3V 23 18 N.C.
100nF 10µH
GND-Clean 17
19 OUT1A
16 100nF
GND-Reg OUT1A FILM
20
10K 100nF 11
OUT1B 22Ω 6.2 100nF
X7R VDD 10 X7R
1/2W 1/2W
21 OUT1B
VDD 470nF 4Ω
22 OUT2A FILM
CONFIG 9 6.2
24 OUT2A 330pF 100nF
1/2W
8 X7R
TH_WAR
TH_WAR 28 OUT2B 100nF
3 FILM
PWRDN OUT2B
nPWRDN 25 2
10µH
10K FAULT
27 VCC1A
15 32V
26
TRI-STATE 1µF 2200µF
100nF X7R 63V
IN1A VCC1B
29 12
IN1B
IN1A 30
IN2A VCC2A
31 7 32V
IN2B
IN1B 32 1µF
X7R
VSS VCC2B
33 4
VSS
34 GND1A
100nF 14
X7R VCCSIGN GND1B
35 13

100nF VCCSIGN GND2A

X7R 36 6
Add. GNDSUB GND2B
1 5
D03AU1514

Figure 8. Typical Quad Half Bridge Configuration

VCC1P +VCC

15
IN1A 29 M3 R61 C21
IN1A 5K C31 820µF 2200µF
17 L11 22µH
VL 23
+3.3V OUTPL
CONFIG 24 16 R41 C71
20 100nF
OUTPL C91 4Ω
PWRDN PWRDN 25 M2 1µF
14 PGND1P R51 C81 R62
PROTECTIONS C41 100nF
6 5K
R57 R59 FAULT 27 & 330pF
10K 10K LOGIC
26 12 VCC1N
TRI-STATE
C58 M5 C51 C61
100nF 11 1µF 100nF
R63
TH_WAR 28 OUTNL 5K C32 820µF
TH_WAR 10 L12 22µH
IN1B 30 OUTNL
IN1B R42 C72
M4 20 100nF
VDD 21 13 PGND1N C92 4Ω
1µF
VDD 22 R52 C82 R64
C42 100nF
6 5K
VSS 33 REGULATORS 330pF
7 VCC2P
VSS 34
M17 R65
C58 C53 C33 820µF
L13 22µH 5K
100nF 100nF VCCSIGN 8
35
OUTPR
C60 9 R43 C73
100nF VCCSIGN 20 100nF
36 OUTPR C93 4Ω
M15 1µF
IN2A 6 PGND2P R53 C83 R66
IN2A 31 C43 100nF
6 5K
330pF
GND-Reg
20 4 VCC2N
GND-Clean
19 M16 C52 C62
3 1µF 100nF
R67
OUTNR 5K C34 820µF
IN2B 2 L14 22µH
IN2B 32
OUTNR
R44 C74
GNDSUB M14 20 100nF
1 5 PGND2N C94 4Ω
1µF
R54 C84 R68
C44 100nF
6 5K
330pF
D03AU1474

For more information refer to the application notes AN1456 and AN1661

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STA508

Figure 9. Power SO36 (SLUG UP) Mechanical Data & Package Dimensions

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX. OUTLINE AND
A 3.25 3.43 0.128 0.135
MECHANICAL DATA
A2 3.1 3.2 0.122 0.126
A4 0.8 1 0.031 0.039
A5 0.2 0.008
a1 0.030 -0.040 0.0011 -0.0015
b 0.22 0.38 0.008 0.015
c 0.23 0.32 0.009 0.012
D 15.8 16 0.622 0.630
D1 9.4 9.8 0.37 0.38
D2 1 0.039
E 13.9 14.5 0.547 0.57
E1 10.9 11.1 0.429 0.437
E2 2.9 0.114
E3 5.8 6.2 0.228 0.244
E4 2.9 3.2 0.114 1.259
e 0.65 0.026
e3 11.05 0.435
G 0 0.075 0 0.003
H 15.5 15.9 0.61 0.625
h 1.1 0.043
L 0.8 1.1 0.031 0.043
N 10˚ (max)
s 8˚ (max)
(1) “D and E1” do not include mold flash or protusions.
PowerSO36 (SLUG UP)
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.

7183931 C

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 STA508

Table 9. Revision History

Date Revision Description of Changes

September 1994 1 First Issue

June 2004 2 Note 2: See relevant Application Note AN1994

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STA508

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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