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    Lab3 Verilog FAM - NBC

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    Muhammad Haroon
    This document outlines the instructions and tasks for a lab on introduction to Verilog and gate-level modeling. The lab has four parts: pre-lab tasks, four main lab tasks, and post-lab questions. The pre-lab tasks involve reading about Verilog and answering questions. The main lab tasks involve writing Verilog code to model a full adder at gate level and behavioral level, modifying a test bench, deriving logic expressions, and comparing the two modeling approaches. Students are expected to complete the tasks and questions in a lab report to submit for grading.

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    © All Rights Reserved
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    Lab3 Verilog FAM - NBC

    Uploaded by

    Muhammad Haroon
    19 views6 pages
    This document outlines the instructions and tasks for a lab on introduction to Verilog and gate-level modeling. The lab has four parts: pre-lab tasks, four main lab tasks, and post-lab questions. The pre-lab tasks involve reading about Verilog and answering questions. The main lab tasks involve writing Verilog code to model a full adder at gate level and behavioral level, modifying a test bench, deriving logic expressions, and comparing the two modeling approaches. Students are expected to complete the tasks and questions in a lab report to submit for grading.

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    This document outlines the instructions and tasks for a lab on introduction to Verilog and gate-level modeling. The lab has four parts: pre-lab tasks, four main lab tasks, and post-lab questions. The pre-lab tasks involve reading about Verilog and answering questions. The main lab tasks involve writing Verilog code to model a full adder at gate level and behavioral level, modifying a test bench, deriving logic expressions, and comparing the two modeling approaches. Students are expected to complete the tasks and questions in a lab report to submit for grading.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    19 views6 pages

    Lab3 Verilog FAM - NBC

    Uploaded by

    Muhammad Haroon
    This document outlines the instructions and tasks for a lab on introduction to Verilog and gate-level modeling. The lab has four parts: pre-lab tasks, four main lab tasks, and post-lab questions. The pre-lab tasks involve reading about Verilog and answering questions. The main lab tasks involve writing Verilog code to model a full adder at gate level and behavioral level, modifying a test bench, deriving logic expressions, and comparing the two modeling approaches. Students are expected to complete the tasks and questions in a lab report to submit for grading.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 6

    National University of Sciences & Technology (NUST)

    Balochistan Campus (NBC), Quetta


    Department of Computer Science

    Faculty Member: Engr Muhammad Abid Hussain Date: ___________


    .
    Semester: __2nd_______________ Section: __________ .
    EE221 – Digital Logic Design
    Assessment Rubrics for Lab No # 3 Introduction to Verilog (CLO4, P3) Grp No.

    S. No. Student Name Reg. No. Total Marks


    S1
    S2
    S3
    S4

    Method: Instructor evaluates each student based on the task demo, viva and behavioral observation
    during the lab and report submitted.

    Lab2: Introduction to Verilog, Gate-level/Behavioral Modeling and Hardware


    Implementation of Basic Logic Circuit

    This Lab has been divided into two parts.

    In first part you will be introduced to Verilog and Gate-Level Modeling.


    The next part is the hardware implementation of a Boolean function given to you.

    Objectives:

     Understand HDL and compare it with normal programming languages.


     Simulate Basic Gates using Verilog with ModelSim
     Write stimulus using Verilog
     Derive algebraic expression for a Boolean function from the given schematics.
     Hardware Implementation of Logic Circuit

    EE-221: Digital Logic Design Page 1


    National University of Sciences & Technology (NUST)
    Balochistan Campus (NBC), Quetta
    Department of Computer Science

    Lab Instructions

     This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session.
     The lab report will be uploaded on LMS three days before scheduled lab date. The students will
    get hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it
    with teacher/lab engineer for necessary evaluation. Alternately each group to upload completed
    lab report on LMS for grading.
     The students failing to submit Pre-Lab will not be allowed to perform Lab work.
     The students will start lab task and demonstrate design steps separately for step-wise
    evaluation( course instructor/lab engineer will sign each step after ascertaining functional
    verification)
     Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will
    simplify trouble-shooting process.
     After the lab, students are expected to unwire the circuit and deposit back components before
    leaving.
     The students will complete lab task and submit complete report to Lab Engineer before leaving
    lab. Verilog tutorial part is non-printable and for reference only.
     There are related questions at the end of this activity. Give complete answers.

    EE-221: Digital Logic Design Page 2


    National University of Sciences & Technology (NUST)
    Balochistan Campus (NBC), Quetta
    Department of Computer Science

    Pre-Lab Task: (To be done before coming to the lab) (2 marks)


    1. Read the manual Getting Started with Verilog and answer the following questions.
    a) HDL stands for

    b) Two standard versions of HDL are

    c) Give the different levels of abstraction in Verilog HDL

    EE-221: Digital Logic Design Page 3


    National University of Sciences & Technology (NUST)
    Balochistan Campus (NBC), Quetta
    Department of Computer Science

    Lab Tasks: (8 marks)


    Lab Task 1: (2 marks)

    Write the Verilog Code using Gate Level modeling for the following circuit. List the code for design as well
    as stimulus below:

    EE-221: Digital Logic Design Page 4


    National University of Sciences & Technology (NUST)
    Balochistan Campus (NBC), Quetta
    Department of Computer Science

    Lab Task 2 (2 marks)

    Modify the test bench to print the results of the simulation using the Verilog $monitor statement. The output
    should look like this

    t = 10, A = 0, B = 0, SUM = 0 CARRY = 0 and so on.

    EE-221: Digital Logic Design Page 5


    National University of Sciences & Technology (NUST)
    Balochistan Campus (NBC), Quetta
    Department of Computer Science

    Lab Task 3: (2 marks)

    Label each gate output in the above circuit and derive algebraic expressions for SUM and Carry Out. Fill in
    the following truth table and determine the function performed by the circuit.

    Truth Table:

    x y Sum Carry Out

    Lab Task 4: (2 marks)

    After determining the function performed by the circuit given in Lab Task 1, write the Verilog description of
    the circuit at dataflow. Comment on the two different modeling levels you used to model the same circuit.
    (Paste snapshots of the codes and stimuluses below)

    Deliverables:

    Compile a single word document by filling in the solution part and submitting this Word file to the MS Team.
    This lab grading policy is as follows: The lab is graded between 0 to 10 marks. The submitted solution can get a
    maximum of 5 marks. At the end of each lab or in the next lab, there will be a viva related to the tasks. The viva has a
    weightage of 5 marks. Insert the solution/answer in this document. You must show the implementation of the tasks in
    the designing tool, along with your complete Word document to get your work graded. You must also submit this
    Word document to the MS Team. In case of any problems with submissions on the MS Team, submit your Lab
    Manual by emailing them to Engr. Muhammad Abid Hussain [email protected]

    EE-221: Digital Logic Design Page 6

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