Experiments of HDL Programming Lab: Numbers and Display With ISE Design Suite 14.7 Experiment
Experiments of HDL Programming Lab: Numbers and Display With ISE Design Suite 14.7 Experiment
Experiments of HDL Programming Lab: Numbers and Display With ISE Design Suite 14.7 Experiment
Experiment (1) Numbers and Display with ISE Design Suite 14.7
Experiment (1): Numbers and Display with ISE Design Suite 14.7
A. Select a New Project option directly or select File then New Project. The New
Project Wizard appears. Enter the name and the location (directory path) for your
project then Next.
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College of Electronics Engineering
Control Engineering Department
HDL Laboratory
B. Enter type of the device and other design information for the project then select
Next then Finish
C. Right click on the selected device, to add one New Source to your project then
Select VHDL Module as the source type in the New Source dialog box. Enter the
file name and location then Next.
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College of Electronics Engineering
Control Engineering Department
HDL Laboratory
A. Describe the ports in your project. Enter: port name, direction, and bus, then
select Next, Finish.
B. Now, write a VHDL code between begin and end then save.
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College of Electronics Engineering
Control Engineering Department
HDL Laboratory
4. Design Simulation :
A. After check the syntax for the VHDL code and there is no error, check simulation of
your program by selection the option of simulation and other options which are appear in
the figure below.
B. To display the input and output waveforms, enter the input signal value as shown in
below figures:
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College of Electronics Engineering
Control Engineering Department
HDL Laboratory
5. Design Implementation
Change the selection from simulation into implementation option, then follow
the steps as shown in the below figures.
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College of Electronics Engineering
Control Engineering Department
HDL Laboratory
If you get a message saying that there are three devices found, click OK to continue. The
devices connected to the JTAG chain on the board will be detected and displayed in the
iMPACT window. The Assign New Configuration File dialog box appears. To assign a
configuration file to the xc3s500e device in the JTAG chain, select the test. bit file and click
Open, and select Bypass to skip any remaining devices. Right-click on the xc3s500e device
image, and select Program The Programming Properties dialog box opens. Click OK to
program the device. When programming is complete, the Program Succeeded message is
displayed. Close iMPACT without saving.
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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory
Data flow describes how data moves through the system and the various processing steps. It
uses series of concurrent statements to realize logic. Concurrent statements are evaluated at
the same time; thus, order of these statements doesn’t matter. Data flow is most useful style
when series of Boolean equations can represent logic.
Combinational circuits: are the class of digital concurrent circuit where the output of this
circuit depend only on the circuit input, in the other word a combinational is able to produce
an output simply from knowing what the current input values. in principle, the system
requires no memory and can be implemented using traditional logic gates. Combinational
system may be tables, Logical expression (Logical operators are:( AND, OR, NAND, NOT,
NOR, XOR) , arithmetic expression (addition +, subtraction -, multiplication *, division
/) and conditional expression
Combinational
Input Output
Logic
For example
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
end and_test;
begin
end Behavioral;
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College of Electronics Engineering
Control Engineering Department
HDL Laboratory
Procedure:
Part I: The purpose of this part is to learn how to use the logical unit
A
X1
X3 Z
C
X2
B
Part II: The purpose of this part is hardware implementation of multiplexer (2:1) circuit
using conditional concurrent signal assignment.
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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory
In digital circuit theory, sequential logic is a type of logic circuit whose output depends not
only on the present input but also on the history of the input. This is in contrast to
combinational logic, whose output is a function of, and only of, the present input. In other
words, sequential logic has storage (memory) while combinational logic does not. Sequential
logic is therefore used to construct some types of computer memory, other types of delay and
storage elements, and finite state machines. Most practical computer circuits are a mixture of
combinational and sequential logic
A process must end with the keywords END PROCESS. The statements are only used in
sequential code are if statements, case statements, loop, and variables. The execution of
statements continues sequentially till the last statement in the process. After execution of the
last statement, the control is again passed to the beginning of the process.
For Example
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ; D Q
END flipflop ;
ARCHITECTURE Behavior_1 OF flipflop IS
BEGIN Clock
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior_1 ;
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College of Electronics Engineering
Control Engineering Department
HDL Laboratory
Procedure :
Part I: The purpose of this part is hardware implementation of 8 bit Register with
asynchronous reset circuit as shown in figure below.
Clock
reg
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Part II: The purpose of this part is hardware implementation of 4 bit up Counter with a
synchronous reset circuit as shown in figure below.
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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory
A structural description can best be compared to a schematic block diagram that can be
described by the components and the interconnections. VHDL provides a formal way to do
this by
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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory
Procedure:
Part I: The purpose of this part is hardware implementation of multiplexer (4:1) circuit by
using multiplexer (2:1) as shown in figure below.
S0 S1
W0
W1
W2
MUX 4.1
W3
Part II: The purpose of this part is hardware implementation of the decoder 4to16 using
decoder 2to4
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