Experiments of HDL Programming Lab: Numbers and Display With ISE Design Suite 14.7 Experiment

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Experiments of HDL Programming Lab

Experiment (1) Numbers and Display with ISE Design Suite 14.7

Experiment (2) Data Flow Modeling of Combinational Logic Circuit

Experiment (3) Behavioral Modeling of Sequential Logic Circuit

Experiment (4) Structural Modeling of logic circuit


University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory

Experiment (1): Numbers and Display with ISE Design Suite 14.7

Aims of this lecture are: ISE Design Suite 14.7


 Design and simulation a simple project with VHDL code by using ISE Design Suite 14.7
 Hardware implementation on FPGA kit.
SW1 LED1
Display LED2
LED1
SW2 LED2
Xilinx ISE (Integrated Synthesis Environment):
ISE is a software tool produced by Xilinx for synthesis and analysis of HDL designs,
enabling the developer to synthesize ("compile") their designs, perform timing analysis,
examine RTL diagrams, simulate the design and configure the target device with the
programmer. The last version of ISE in October 2013 version 14.7.
1. Create a New Project:

A. Select a New Project option directly or select File then New Project. The New
Project Wizard appears. Enter the name and the location (directory path) for your
project then Next.

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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory

B. Enter type of the device and other design information for the project then select
Next then Finish

C. Right click on the selected device, to add one New Source to your project then
Select VHDL Module as the source type in the New Source dialog box. Enter the
file name and location then Next.

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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory

A. Describe the ports in your project. Enter: port name, direction, and bus, then
select Next, Finish.

B. Now, write a VHDL code between begin and end then save.

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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory

3. Checking the Syntax of design


When the source files are complete, the next step is to check the syntax of the design.
Syntax errors can be extract “+” of the Synthesize-XST process, Double-click the
Check Syntax process as showed in previous figure.

4. Design Simulation :
A. After check the syntax for the VHDL code and there is no error, check simulation of
your program by selection the option of simulation and other options which are appear in
the figure below.

B. To display the input and output waveforms, enter the input signal value as shown in
below figures:

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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory

5. Design Implementation
Change the selection from simulation into implementation option, then follow
the steps as shown in the below figures.

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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory

6. Download Design to the Spartan™-3E Demo Board


This is the last step in the design verification process. This section provides simple
instructions for downloading the design to the Spartan-3E Starter Kit demo board.
Double-click on the Boundary Scan then right click and choose Add Xilinx Device.
After appear the FPGA device, right click and choose program option. As shown in the
below figures.

If you get a message saying that there are three devices found, click OK to continue. The
devices connected to the JTAG chain on the board will be detected and displayed in the
iMPACT window. The Assign New Configuration File dialog box appears. To assign a
configuration file to the xc3s500e device in the JTAG chain, select the test. bit file and click
Open, and select Bypass to skip any remaining devices. Right-click on the xc3s500e device
image, and select Program The Programming Properties dialog box opens. Click OK to
program the device. When programming is complete, the Program Succeeded message is
displayed. Close iMPACT without saving.
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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory

Experiment (2): Data Flow Modeling of Combinational Logic Circuit

Data flow describes how data moves through the system and the various processing steps. It
uses series of concurrent statements to realize logic. Concurrent statements are evaluated at
the same time; thus, order of these statements doesn’t matter. Data flow is most useful style
when series of Boolean equations can represent logic.

Concurrent signal assignment.(<=)


Conditional concurrent signal assignment (when-else)
Selected concurrent signal assignment. (with-select-when)

Combinational circuits: are the class of digital concurrent circuit where the output of this
circuit depend only on the circuit input, in the other word a combinational is able to produce
an output simply from knowing what the current input values. in principle, the system
requires no memory and can be implemented using traditional logic gates. Combinational
system may be tables, Logical expression (Logical operators are:( AND, OR, NAND, NOT,
NOR, XOR) , arithmetic expression (addition +, subtraction -, multiplication *, division
/) and conditional expression

Combinational
Input Output
Logic

For example
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

Port ( IN1,IN2 : in STD_LOGIC;

OUT1 : out STD_LOGIC);

end and_test;

architecture Behavioral of and_test is

begin

OUT1<= IN1 AND IN2;

end Behavioral;

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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory

Procedure:

Part I: The purpose of this part is to learn how to use the logical unit
A
X1

X3 Z
C

X2
B

1) Design the circuit shown in figure above


2) Create a VHDL code of this circuit.
3) Compile the project(test bentch).
4) Download the compiled circuit FPGA chip, test the functionality of the circuit by toggling
the switch and observing the LED.

Part II: The purpose of this part is hardware implementation of multiplexer (2:1) circuit
using conditional concurrent signal assignment.

1) Design the circuit


2) Create a VHDL code of this circuit.
3) Compile the project(test bentch).
4) Download the compiled circuit FPGA chip, test the
functionality of the circuit by toggling the switch and
observing the LED.

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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory

Experiment (3): Behavioral Modeling of Sequential Logic Circuit

In digital circuit theory, sequential logic is a type of logic circuit whose output depends not
only on the present input but also on the history of the input. This is in contrast to
combinational logic, whose output is a function of, and only of, the present input. In other
words, sequential logic has storage (memory) while combinational logic does not. Sequential
logic is therefore used to construct some types of computer memory, other types of delay and
storage elements, and finite state machines. Most practical computer circuits are a mixture of
combinational and sequential logic

A process is a sequence of instructions


referred to as sequential statements as well as Input Combinational Output
functions and procedures. A process can be Logic
given a unique name using an optional
LABEL. The keyword BEGIN is used to
indicate the start of the process. All statements
Storage
within the process are executed Elements Next
Present
SEQUENTIALLY. Hence, order of statements State State
is important.

A process must end with the keywords END PROCESS. The statements are only used in
sequential code are if statements, case statements, loop, and variables. The execution of
statements continues sequentially till the last statement in the process. After execution of the
last statement, the control is again passed to the beginning of the process.

For Example
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ; D Q
END flipflop ;
ARCHITECTURE Behavior_1 OF flipflop IS
BEGIN Clock
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior_1 ;

9
University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory

Procedure :

Part I: The purpose of this part is hardware implementation of 8 bit Register with
asynchronous reset circuit as shown in figure below.

1) Design the circuit


2) Create a VHDL code of this circuit.
3) Compile the project (test bentch). 8 Resetn 8
4) Down load the compiled circuit FPGA chip, D Q
test the functionality of the circuit by toggling the switch
and observing the LED.

Clock
reg
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Part II: The purpose of this part is hardware implementation of 4 bit up Counter with a
synchronous reset circuit as shown in figure below.

1) Design the circuit


2) Create a VHDL code of this circuit.
3) Compile the project(test bentch).
Enable 4
4) Down load the compiled circuit FPGA chip, Q
test the functionality of the circuit by toggling the switch
and observing the LED. Clock upcount
Resetn

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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory

Experiment (4): Structural Modeling of logic circuits

A digital system is frequently composed of several smaller subsystems. This allows us to


build a large system from simpler or predesigned components. A structural way of modeling
describes a circuit in terms of components and its interconnection. Each component is
supposed to be defined earlier (e.g. in package) and can be described as structural, a
behavioral or dataflow model. At the lowest hierarchy each component is described as a
behavioral model, using the basic logic operators defined in VHDL. In general structural
modeling is very good to describe complex digital systems, though a set of components in a
hierarchical fashion.

A structural description can best be compared to a schematic block diagram that can be
described by the components and the interconnections. VHDL provides a formal way to do
this by

· Declare a list of components being used


· Declare signals which define the nets that interconnect components
· Label multiple instances of the same component so that each instance is
uniquely defined.

Component instantiation (port map)


Component instantiation with generic (generic map, port map)
Generate scheme for component instantiations (for-generate)

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University of Ninevah
College of Electronics Engineering
Control Engineering Department
HDL Laboratory

Procedure:

Part I: The purpose of this part is hardware implementation of multiplexer (4:1) circuit by
using multiplexer (2:1) as shown in figure below.

S0 S1

W0

W1

W2
MUX 4.1
W3

1) Design the circuit using components


2) Create a VHDL code of this circuit.
3) Compile the project(test bentch).
4) Down load the compiled circuit FPGA chip, test the functionality of the circuit by
toggling the switch and observing the LED.

Part II: The purpose of this part is hardware implementation of the decoder 4to16 using
decoder 2to4

1) Design the circuit using components


2) Create a VHDL code of this circuit.
3) Compile the project (test bentch).
4) Down load the compiled circuit FPGA chip, test the functionality of the circuit by
toggling the switch and observing

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