Datasheet PDF

Global LCD Panel Exchange Center www.panelook.
com
PRODUCT SPECIFICATION
□ Tentative Specification
□ Preliminary Specification
■ Approval Specification
MODEL NO.: V400H1

SUFFIX: LHA
Customer:
APPROVED BY SIGNATURE
Name / Title
Note
Please return 1 copy for your confirmation with your

signature and comments.
Approved By Checked By Prepared By
Chao-Chun Chung Josh Chi Joanne Chung
Version 2.0 1 DateΚ

Κ03 Mar 2011
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center www.panelook.com
CONTENTS
1. GENERAL DESCRIPTION ......................................................................................................................................................... 5

1.1 OVERVIEW .......................................................................................................................................................... 5
1.2 FEATURES .......................................................................................................................................................... 5
1.3 APPLICATION ...................................................................................................................................................... 5
1.4 GENERAL SPECIFICATIONS ............................................................................................................................. 5
1.5 MECHANICAL SPECIFICATIONS ....................................................................................................................... 6
2. ABSOLUTE MAXIMUM RATINGS .......................................................................................................................................... 7

2.1 ABSOLUTE RATINGS OF ENVIRONMENT........................................................................................................ 7
2.2 PACKAGE STORAGE.......................................................................................................................................... 8
2.3 ELECTRICAL ABSOLUTE RATINGS .................................................................................................................. 8
2.3.1 TFT LCD MODULE .................................................................................................................................... 8
2.3.2 BACKLIGHT BALANCE BOARD UNIT...................................................................................................... 8
3. ELECTRICAL CHARACTERISTICS ......................................................................................................................................... 9

3.1 TFT LCD MODULE .............................................................................................................................................. 9
3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION......................................................................................... 12
3.2.1 LAMP SPECIFICATION (Ta = 25 ± 2 ºC) ............................................................................................ 12
3.2.2 ELECTRICAL SPECIFICATION............................................................................................................... 12
4.1 TFT LCD MODULE ............................................................................................................................................ 15
5. INPUT TERMINAL PIN ASSIGNMENT................................................................................................................................ 16

5.1 TFT LCD Module Input....................................................................................................................................... 16
5.2 BACKLIGHT UNIT.............................................................................................................................................. 19
5.3 BALANCE BOARD UNIT ................................................................................................................................... 20
5.4 BLOCK DIAGRAM OF INTERFACE .................................................................................................................. 21
5.5 LVDS INTERFACE ............................................................................................................................................. 23
5.6 COLOR DATA INPUT ASSIGNMENT ................................................................................................................ 24
The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of the color
versus data input. ..................................................................................................................................................... 24
6. INTERFACE TIMING................................................................................................................................................................ 25
6.1 INPUT SIGNAL TIMING SPECIFICATIONS ...................................................................................................... 25
7. OPTICAL CHARACTERISTICS............................................................................................................................................... 29
7.1 TEST CONDITIONS........................................................................................................................................... 29
Κ03 Mar 2011
7.2 OPTICAL SPECIFICATIONS ............................................................................................................................. 30
PRECAUTIONS.............................................................................................................................................................................. 35
8.1 ASSEMBLY AND HANDLING PRECAUTIONS ................................................................................................. 35
8.2 SAFETY PRECAUTIONS .................................................................................................................................. 35
9. DEFINITION OF LABELS......................................................................................................................................................... 36
9.1 CMI MODULE LABEL ........................................................................................................................................ 36
10. PACKAGING............................................................................................................................................................................ 37
10.1 PACKAGING SPECIFICATIONS ..................................................................................................................... 37
10.2 PACKAGING METHOD.................................................................................................................................... 38
11. MECHANICAL CHARACTERISTIC .................................................................................................................................... 40
Appendix – TWO Wire BUS INTRODUCTION ........................................................................................................................ 43

A.1 PIN ASSIGNMENT ............................................................................................................................................ 43
A.2 I2C BUS APPLICATION NOTE ......................................................................................................................... 43
A.3 TWO WIRE BUS DEVICE ADDRESS ............................................................................................................... 43

Κ03 Mar 2011
REVISION HISTORY
Version Date Page(New) Section Description
Ver. 2.0 Mar. 03, 2011 All All The approval specification was first issued.

Κ03 Mar 2011
1. GENERAL DESCRIPTION
1.1 OVERVIEW
V400H1-LHA is a 40” TFT Liquid Crystal Display module with 12-CCFL Backlight unit and 4ch-LVDS interface.
This module supports 1920 x 1080 Full HDTV format and can display true 1.07G (8-bit+Hi-FRC) colors. The
balance board module for backlight is built-in.
1.2 FEATURES
Ё High brightness (500 nits)
Ё High contrast ratio (6000:1)
Ё Fast response time (Gray to gray average 5.5 ms)
Ё High color saturation (NTSC 72%)
Ё Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё DE (Data Enable) only mode
Ё LVDS (Low Voltage Differential Signaling) interface
Ё Optimized response time for 120 Hz frame rate
Ё Ultra wide viewing angle : Super MVA technology
Ё Viewing Angle : 160(H)/150(V) (CR>10) TN Technology
Ё RoHs compliance
1.3 APPLICATION
Ё Standard Living Room TVs
Ё Public Display Application
Ё Home Theater Application
Ё MFM Application
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 885.6(H) x 498.15 (V) (40” diagonal) mm

(1)
Bezel Opening Area 891.7 (H) x 504.8 (V) mm
Driver Element a-si TFT active matrix - -
Pixel Number 1920 x R.G.B. x 1080 pixel -

Pixel Pitch(Sub Pixel) 0.15375 (H) x 0.46125 (V) mm -
Pixel Arrangement RGB vertical stripe - -
Display Colors 1.07G color -
Display Operation Mode Transmissive mode / Normally Black - -
Surface Treatment Anti-Glare coating (Haze 11%) - (2)
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMI reserves the rights to change this feature.

Κ03 Mar 2011
1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note
Horizontal (H) 951 952 953 mm (1)
Vertical (V) 550 551 552 mm (1)

Module Size
Depth (D) 49 50 51 mm (2)
Depth (D) 56.3 57.3 58.3 mm (3)
Weight - 9439.5 - g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth is between bezel to T-CON cover.
Note (3) Module Depth is between bezel to Balance board cover.

Κ03 Mar 2011
2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Value
Item Symbol Unit Note
Min. Max.
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 50 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature
of display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.

Κ03 Mar 2011
2.2 PACKAGE STORAGE

When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
store the module with temperature from 0 to 35 к at normal humidity without condensation.
(b) The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Value
Min. Max.
Power Supply Voltage VCC -0.3 13.5 V

(1)
Logic Input Voltage VIN -0.3 3.6 V
2.3.2 BACKLIGHT BALANCE BOARD UNIT
Value
Min. Max.
Lamp Voltage V Ё 3000 VRMS Lamp Voltage

IP Board Supply
IP Board Supply Voltage High / Low 195 (Low) 390 (High) Vrms
Voltage
Control Signal Level Ё -0.3 15 V Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Control and Internal PWM Control.

Κ03 Mar 2011
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol Unit Note
Min. Typ. Max.
Power Supply Voltage VCC 10.8 12 13.2 V (1)
Rush Current IRUSH Ё Ё 4.25 A (2)
White Pattern Ё 15.12 18.24
Power consumption Black Pattern PT Ё 7.08 8.4 W (3)
Horizontal Stripe Ё 15.12 18.24
White Pattern Ё Ё 1.26 1.52 A
Power Supply Current Black Pattern Ё Ё 0.59 0.70 A (3)
Horizontal Stripe Ё Ё 1.26 1.52 A

Differential Input High
VLVTH +100 Ё Ё mV
Threshold Voltage
Differential Input Low
VLVTL Ё Ё -100 mV
Threshold Voltage
LVDS
Common Input Voltage VCM 1.0 1.2 1.4 V (4)
interface
Differential input voltage
|VID| 200 Ё 600 mV
(single-end)
Terminating Resistor RT Ё 100 Ё ohm
Input High Threshold Voltage VIH 2.7 Ё 3.3 V

CMIS
interface
Input Low Threshold Voltage VIL 0 Ё 0.7 V
Note (1) The module should be always operated within the above ranges.
Note (2) Measurement condition:

Κ03 Mar 2011
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
GND
470us
Note (3) The specified power supply current and power consumption are under the conditions at Vcc = 12 V,
Ta = 25 ± 2 ºC, fv = 120 Hz, whereas a power dissipation check pattern below is displayed.

Κ03 Mar 2011
a. White Pattern b. Black Pattern
Active Area Active Area
c. Horizontal Pattern
Note (4) The LVDS input characteristics are as follows :

Κ03 Mar 2011
3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION

3.2.1 LAMP SPECIFICATION (Ta = 25 ± 2 ºC)
Value
Min. Typ. Max.
Lamp Input Voltage VW - 840 - VRMS IL=14.5mA
Lamp Current IL 3 14.5 15 mARMS
- - 1320 VRMS (1) , Ta = 0 ºC

Lamp Turn On Voltage VS
- - 1190 VRMS (1) , Ta = 25 ºC
Operating Frequency FO 30 - 80 KHz (2)
Lamp Life Time LBL 50,000 - - Hrs (3)
3.2.2 ELECTRICAL SPECIFICATION

(Ta = 25 ± 2 ºC)
Value
Min. Typ. Max.
Input High Voltage High 380 390 400 Vrms (6)
Input Low Voltage Low 190 195 200 V
Protection Circuit Supply 11 13 15
Vcc V
Voltage
No Dimming
Power Consumption PIP - 145 150 W
(IPB input)
Measure TBB
Input Current ITB 0.372 0.385 Arms
HIGH(390V)
Oscillating Frequency FW 43 45 47 kHz

Individual Lamp Current IL 13.5 14.5 15.5 mA (5)
Connector High CNTPRT Vcc-0.5 - Vcc V Normal Operation

Detection Low CNTPRT - - 1 V Input Connector Open
All Lamp Open High LD Vcc-0.5 - Vcc V Normal Operation

Detection Low LD - - 1 V All Lamp Open
One Lamp High OVP 1.25 - - V Normal Operation
Open Detection Low OVP 0 - 0.8 V One Lamp Open
Dimming frequency FB 140 150 160 Hz
Minimum Duty Ratio DMIN 12 15 18 % Note.8
Striking time tsriking 1 - 2 sec
Shutdown time Tsd 1 1.5 2 sec
Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring
master and slave board.:
Κ03 Mar 2011
Note (2) The lamp starting voltage VS should be applied to the lamp for more than 1 second after startup.
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference, the
lamp frequency should be detached from the horizontal synchronous frequency and its harmonics as
far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and
the effective discharge length is longer than 80% of its original length (Effective discharge length is
defined as an area that has equal to or more than 70% brightness compared to the brightness at
the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25
̈́2к and IL = 13.5~15.5 mArms.
Note (5) Lamp current is measured master board by utilizing high frequency current meters as shown below:
Note (6) Input voltage Hv based on spec. +-7% tolerance.
Note (7) Asymmetric ratio must be from 90% to 110% (0.9<Ip/ Irms@T/2XЅ2 <1.1)
Note (8) The minimum dimming under 3% operation should cause shutdown by protection circuit.
T
Ip
I-p

Κ03 Mar 2011
HV (Blue +(-))
A 1
HV (White +(-))
A 2
HV (Blue +(-))
A 1
HV (White +(-))
A 2
HV (Blue +(-))
A 1
HV (White +(-))
A 2
Balance LCD Module
Board HV (Blue +(-))
A 1
HV (White +(-))
A 2
HV (Blue +(-))
A 1
HV (White +(-))
A 2
HV (Blue +(-))
A 1
HV (White +(-))
A 2

Κ03 Mar 2011
4. BLOCK DIAGRAM OF INTERFACE

4.1 TFT LCD MODULE
CH1_0(+/-)
CH1_1(+/-)
CH1_2(+/-)
TFT LCD PANEL
SCAN DRIVER IC
CH1_3(+/-)
(FP7S082HA1R1200,JAE
CH1_4(+/-) (1920x3x1080)
CH1_CLK(+/-)
CH2_0(+/-)
CH2_1(+/-)
CH2_2(+/-) TIMING CONTROLLER
CH2_3(+/-)
INPUT CONNECTOR
CH2_4(+/-)
CH2_CLK(+/-)
CH3_0(+/-)
CH3_1(+/-) DATA DRIVER IC
CH3_2(+/-)
CH3_3(+/-)
Taiwan(‫؀‬᨜౰़ሽ՗) or
CH3_4(+/-)
CH3_CLK(+/-) DC/DC CONVERTER &
CH4_0(+/-)
CH4_1(+/-) REFERENCE VOLTAGE
CH4_2(+/-)
CH4_3(+/-) GENERATOR
CH4_4(+/-)
CH4_CLK(+/-)
SELLVDS
SDA
SCL
Vcc
GND
20037WR-H1224567(Yeon-Ho )
High
Low
IP BOARD
Gnd BALANCE BACKLIGHT
OVP
CNT_PRT UNIT
12V
LD BOARD

Κ03 Mar 2011
5. INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD Module Input
CNF1 Connector Pin Assignment (FP7S082HA1R1200,JAE Taiwan(‫؀‬᨜౰़ሽ՗) or equivalent)
Pin Name Description Note
1 VCC +12V power supply
6 N.C. No Connection (1)
7 GND Ground
8 GND Ground
9 GND Ground
10 CH1[0]- First pixel Negative LVDS differential data input. Pair 0
11 CH1[0]+ First pixel Positive LVDS differential data input. Pair 0
16 GND Ground
17 CH1CLK- First pixel Negative LVDS differential clock input.
18 CH1CLK+ First pixel Positive LVDS differential clock input.
19 GND Ground
24 GND Ground
25 CH3[0]- Third pixel Negative LVDS differential data input. Pair 0
26 CH3[0]+ Third pixel Positive LVDS differential data input. Pair 0

Κ03 Mar 2011
31 GND Ground
32 CH3CLK- Third pixel Negative LVDS differential clock input.
33 CH3CLK+ Third pixel Positive LVDS differential clock input.
34 GND Ground
39 GND Ground
40 SCL I2C Bus
43 WP Write Protection for EEPROM
44 SDA I2C Bus
45 LVDS_SEL LVDS Data Format Selection (2)
52 GND Ground
53 CH4[4]+ Fourth pixel Positive LVDS differential data input. Pair 4
54 CH4[4]- Fourth pixel Negative LVDS differential data input. Pair 4
57 GND Ground
58 CH4CLK+ Fourth pixel Positive LVDS differential clock input.
59 CH4CLK- Fourth pixel Negative LVDS differential clock input.
60 GND Ground

Κ03 Mar 2011
67 GND Ground
68 CH2[4]+ Second pixel Positive LVDS differential data input. Pair 4
69 CH2[4]- Second pixel Negative LVDS differential data input. Pair 4
72 GND Ground
73 CH2CLK+ Second pixel Positive LVDS differential clock input.
74 CH2CLK- Second pixel Negative LVDS differential clock input.
75 GND Ground
82 GND Ground
Note (1) Reserved for internal use. Please leave it open.

Note (2) High=connect to +3.3V: VESA Format Ι Low= connect to GND or Open: JEIDA Format.
Note (3) Interface optional pin has internal scheme as following diagram. Customer should keep the interface
voltage level requirement as below.

Κ03 Mar 2011
System Board Panel Board
1K ohm IC
Interface Voltage Level >20K ohm

VH > 3.0V
VL < 0.7V
Note (4) LVDS 4-port Data Mapping

Port Channel of LVDS Data Stream
1st Port First Pixel 1, 5, 9, ……1913, 1917
2nd Port Second Pixel 2, 6, 10, ….1914, 1918
3rd Port Third Pixel 3, 7, 11, ….1915, 1919
4th Port Fourth Pixel 4, 8, 12, ….1916, 1920
5.2 BACKLIGHT UNIT

The pin configuration for the housing and the leader wire is shown in the table below.
Pin Name Description Wire Color

1 HV High Voltage White
2 HV High Voltage Pink
1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)

Κ03 Mar 2011
5.3 BALANCE BOARD UNIT

CN1(Header): 20037WR-H1224567(Yeon-Ho )
Pin № Signal name Feature
1 HIGH (FET) Pulse 390V (Drive, Primary)
2 No pin NC
3 LOW (FET) Blocking (195Vdc, Primary)

NC
4 No pin
NC
5 No pin
6 No Pin NC
7 No Pin NC
8 GND Ground ( Secondary)
9 OVP One Lamp Open Protection

Open Input Connector Protection
10 CNT_PRT
(Normal 12V, Active Low)
11 12V VCC
All Lamp Open Protection
12 LD
(Normal 12V, Active Low)
Ampower: CN2-CN7: CP042EP1MFB-LF (CviLux)

Hansol: CN11-CN16: 130001WR-02H (YEONHO)
Pin No. Symbol Description
1 CCFL HOT CCFL High voltage
2 CCFL HOT CCFL High voltage

Κ03 Mar 2011
5.4 BLOCK DIAGRAM OF INTERFACE
ARx0 + 51Ω RxOUT

100pF
ARx0 -
AR0 – AR9
51Ω
AG0 – AG9
ARx1 + 51Ω
100pF AB0 – AB9
ARx1 -
DE
51Ω
ARx2 + 51Ω
100pF
ARx2 -
51Ω
ARx3 + 51Ω
100pF
ARx3 -
51Ω
ARx4 + 51Ω
100pF
ARx4 -
51Ω
ACLK + 51Ω
100pF
PLL
ACLK -
51Ω
BRx0 + 51Ω
100pF
BRx0 -
51Ω BR0 – BR9
BRx1 + 51Ω
BG0 – BG9
100pF BB0 – BB9

BRx1 -
51Ω DCLK
BRx2 + 51Ω
100pF
BRx2 -
51Ω
BRx3 + 51Ω
100pF
BRx3 -
51Ω
BRx4 + 51Ω DCLK

100pF
BRx4 - Timing
51Ω Controller
BCLK + 51Ω
100pF
PLL LVDS Receiver
BCLK - (MASTER)
51Ω
LVDS INPUT

Κ03 Mar 2011
AR0~AR9: First pixel R data

AG0~AG9: First pixel G data
AB0~AB9: First pixel B data
BR0~BR9: Second pixel R data
BG0~BG9: Second pixel G data
BB0~BB9: Second pixel B data
DE: Data enable signal
DCLK: Data clock signal
The third and fourth pixel are followed the same rules.
CR0~CR9: Third pixel R data
CG0~CG9: Third pixel G data
CB0~CB9: Third pixel B data
DR0~DR9: Fourth pixel R data
DG0~DG9: Fourth pixel G data
DB0~DB9: Fourth pixel B data
Note (1) A ~ D channel are first, second, third and fourth pixel respectively.
Note (2) The system must have the transmitter to drive the module.
Note (3) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.

Κ03 Mar 2011
5.5 LVDS INTERFACE

VESA Format : SELLVDS = H
JEIDA Format : SELLVDS = L or Open
Current Cycle
VESA Format
AR 0P
AR0 AG0 AR5 AR4 AR3 AR2 AR1 AR0 AG0
AR 0N
AR 1P
AG1 AB1 AB0 AG5 AG4 AG3 AG2 AG1 AB1
AR 1N
AR 2P
AB2 DE VS HS AB5 AB4 AB3 AB2 DE
AR 2N
AR 3P
AR6 REV AB7 AB6 AG7 AG6 AR7 AR6 REV
AR 3N
AR 4P
AR 4N
JEIDA Format
AR 0P
AR4 AG4 AR9 AR8 AR7 AR6 AR5 AR4 AG4
AR 0N
AR 1P
AG5 AB5 AB4 AG9 AG8 AG7 AG6 AG5 AB5
AR 1N
AR 2P
AB6 DE VS HS AB9 AB8 AB7 AB6 DE
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)

AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)
AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
RSV : Reserved

Κ03 Mar 2011
5.6 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of the color
versus data input.
Data Signal
Color Red Green Blue
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
Basic Blue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Colors Cyan 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Magenta 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Red (0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red (1) 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red (2) 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Gray : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
Scale : : : : : : : : : : : : : : : : : : : ; : : : : : : : : :
Of Red (1021) 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red Red (1022) 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red (1023) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green (0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Green (2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
Gray : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
Scale : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
Of Green (1021) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0
Green Green (1022) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
Green (1023) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
Blue (0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Blue (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Blue (2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Gray : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
Scale : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
Of Blue (1021) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1
Blue Blue (1022) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0
Blue (1023) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Note (1) 0: Low Level Voltage, 1: High Level Voltage

Κ03 Mar 2011
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
(Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note

Fclkin
Frequency 60 74.25 80 MHz (1)(5)
(=1/TC)
Input cycle to
LVDS Trcl Ё Ё 200 ps (3)
cycle jitter
Receiver Spread spectrum
Clock Fclkin_mod Fclkin-2% Ё Fclkin+2% MHz
modulation range
(4)
Spread spectrum
FSSM Ё Ё 200 KHz
modulation frequency
LVDS Setup Time Tlvsu 600 Ё Ё ps
Receiver (5)
Data Hold Time Tlvhd 600 Ё Ё ps
Fr5 Ё 100 Ё Hz
Frame Rate (1)
Fr6 Ё 120 Ё Hz
Vertical
Active Total Tv 1115 1125 1135 Th Tv=Tvd+Tvb
Display
Term Display Tvd 1080 1080 1080 Th (2)
Blank Tvb 35 45 55 Th (2)
Total Th 540 550 575 Tc Th=Thd+Thb

Horizontal
Active
Display Thd 480 480 480 Tc (2)
Display
Term
Blank Thb 60 70 95 Tc (2)
Note (1) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low
logic level. Otherwise, this module would operate abnormally.
Note (2ʼʳ ʳ ˣ˿˸˴̆˸ʳ̀˴˾˸ʳ̆̈̅˸ʳ̇˻˸ʳ̅˴́˺˸ʳ̂˹ʳ̃˼̋˸˿ʳ˶˿̂˶˾ʳ˻˴̆ʳ˹̂˿˿̂̊ʳ̇˻˸ʳ˵˸˿̂̊ʳ˸̄̈˴̇˼̂́ˍʳ ʳ ʳ
˙˶˿˾˼́ʻ̀˴̋ʼʳ Њʳ ˙̅ˉʳ Ѽʳ ˧̉ʳ Ѽʳ ˧˻ʳ
˙̅ˈʳ Ѽʳ ˧̉ʳ Ѽʳ ˧˻ʳ Њʳ ˙˶˿˾˼́ʻ̀˼́ʼʳ
ʳ

Κ03 Mar 2011
INPUT SIGNAL TIMING DIAGRAM

Tv
Tvd
Tvb
DE
Th
DCLK
Tc
Thd
Thb
DE
DATA Valid Display Data (480 clocks)
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI

Κ03 Mar 2011
Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
LVDS RECEIVER INTERFACE TIMING DIAGRAM
Tc
RXCLK+/-
RXn+/-
Tlvsu
Tlvhd
1T 3T 5T 7T 9T 11T 13T
14 14 14 14 14 14 14

Κ03 Mar 2011
6.2 POWER ON/OFF SEQUENCE

(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram
below.
0.9VCC
0.9VCC
0.1VCC 0.1Vcc
0V
ЉT1Љ10ms
0.5Љ T1 T3
ЉT2Љ50ms
0Љ
ЉT3Љ50ms
0Љ
500ms ЉT4 T2
T4
VALID
LVDS Signals
0V
Power On Power Off
ЉT7ЉT2
0Љ
ЉT8ЉT3
0Љ
T7 T8
Option Signals
(SELLVDS)
Backlight (Recommended) 50% 50%

500msЉ ЉT 5
100msЉT6
T5 T6
Power ON/OFF Sequence
Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.
Note (2) Apply the LED voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. If
T2<0,that maybe cause electrical overstress failure.
Note (4) T4 should be measured after the module has been fully discharged between power off and on period.
Note (5) Interface signal shall not be kept at high impedance when the power is on.

Κ03 Mar 2011
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
o
Ambient Temperature Ta 25±2 C
Ambient Humidity Ha 50±10 %RH
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current IL 14.5 mA

Oscillating Frequency (Balance
FW 45±2 kHz
board)
Vertical Frame Rate Fr 120 Hz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during
measuring in a windless room.

Κ03 Mar 2011
7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in 7.1.
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR 4000 6000 - - (2)

Gray to
Response Time (VA) - 5.5 11 ms (3)
gray
2
Center Luminance of White LC 360 500 - cd/m (4)
White Variation δW - - 1.3 - (6)
Cross Talk CT - - 4 % (5)
Rx 0.635 -
Red
Ry θx=0°, θy =0° 0.325 -
Viewing angle
Gx at normal direction 0.292 -
Green
Gy 0.601 -
Typ. Typ.
-
Color -0.03 +0.03
Bx 0.148 -
Chromaticity
Blue
By 0.049 -
Wx 0.280 -
White
Wy 0.290 -
Color Gamut C.G - 72 - % NTSC
θx+ 80 88 -
Horizontal
θx- CR≥20 (VA) 80 88 -
Viewing
Angle CR≥10 (TN) Deg. (1)
θY+ 80 88 -
Vertical
θY- 80 88 -

Κ03 Mar 2011
Note (1) Definition of Viewing Angle (θx, θy) :

Viewing angles are measured by Conoscope Cono-80 ( or Eldim EZ-Contrast 160R)
Normal
θx =θy = 0º
θy+
θx- = 90º θy-
12 o’clock direction
x-
θy + = 90º
θx−
θx+
6 o’clock
y-
θy- = 90º x+ θx+ = 90º
Note (2) Definition of Contrast Ratio (CR) :

The contrast ratio can be calculated by the following expression.
Surface Luminance of L255
Contrast Ratio (CR) =
Surface Luminance of L0
L255: Luminance of gray level 255
L 0: Luminance of gray level 0
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note
(6).
Note (3) Definition of Gray-to-Gray Switching Time:
100%
90%
Optical
Response
10%
0%
Time
Gray to gray Gray to gray
switching time switching time
The driving signal means the signal of gray level 0, 31, 63, 95, 127, 159, 191, 223 and 255
Gray to gray means the average switching time of gray level 0, 31, 63, 95, 127, 159, 191, 223 and
255 to each other.#!

Κ03 Mar 2011
!
Note (3) Definition of Response Time (TR, TF):
Gray Level 255 Gray Level 255
100%
90%
Optical
Gray Level 0
Response
10%
0%
Time
TR TF
Note (4) Definition of Luminance of White (LC):

Measure the luminance of gray level 255 at center point and 5 points
LC = L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (6).

Κ03 Mar 2011
Note (5) Definition of Cross Talk (CT):

CT = | YB – YA | / YA × 100 (%)
Where:
YA = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)

(0, 0) (0, 0)
YA, U (D/2,W/8) YB, U (D/2,W/8)

(D/4,W/4)
Gray 128
YA, L (D/8,W/2) YA, R (7D/8,W/2) YB, L (D/8,W/2) YB, R (7D/8,W/2)
(3D/4,3W/4)
YA, D (D/2,7W/8)
YB, D (D/2,7W/8)
(D, W)
YA = Luminance of measured location without gray level 255 pattern (cd/m2)

YB = Luminance of measured location with gray level 255 pattern (cd/m2)

(0, 0) (0, 0)
YA, U (D/2,W/8) YB, U (D/2,W/8)

(D/4,W/4)
Gray 128 Gray 255

YA, L (D/8,W/2) YA, R (7D/8,W/2) YB, L (D/8,W/2) YB, R (7D/8,W/2)
(3D/4,3W/4)
YA, D (D/2,7W/8)
YB, D (D/2,7W/8)
(D, W) (D, W)

Κ03 Mar 2011
Note (6) Definition of White Variation (δW):

Measure the luminance of gray level 255 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
Horizontal Line
D/4 D/2 3D/4
W/4 1 2
Vertical Line
W W/2 5 : Test Point
X=1 to 5
3 4
Active Area

Κ03 Mar 2011
PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
[1] Do not apply rough force such as bending or twisting to the module during assembly.
[2] It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
[3] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
[4] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMIS LSI chips.
[5] Bezel of Set can not press or touch the panel surface. It will make light leakage or scrape.
[6] Do not plug in or pull out the I/F connector while the module is in operation.
[7] Do not disassemble the module.
[8] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
[9] Moisture can easily penetrate into LCD module and may cause the damage during operation.
[ 10 ] When storing modules as spares for a long time, the following precaution is necessary.
[ 10.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly
recommended to store the module with temperature from 0 to 35кat normal humidity without
condensation.
[ 10.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or
fluorescent light.
[ 11 ] When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
8.2 SAFETY PRECAUTIONS

[1] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
[2] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
[3] After the module’s end of life, it is not harmful in case of normal operation and storage.

Κ03 Mar 2011
9. DEFINITION OF LABELS
9.1 CMI MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
V400H1 –LHA Rev. XX
CHI MEI
E207943
XXXXXXXYMDLNNNN MADE IN TAIWAN
OPTOELECTRONICS
RoHS GEMN
CM40H12XXXXXLXXLYMDNNNN
(a) Model Name: V400H1-LHA

(b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
(c) Production Locations / Factory ID: IN TAIWAN (GEMN) or IN CHINA (LEOO or CAPG or CANO)
(d) CMI barcode definition:
Serial ID: XX-XX-X-XX-YMD-L-NNNN
Code Meaning Description
XX CMI internal use -
XX Revision Cover all the change
X-XX CMI internal use -
Year, month, day Year: 2001=1, 2002=2, 2003=3, 2004=4…
YMD Month: Jan. ~ Dec.=1, 2, 3, ~, 9, A, B, C
st st
Day: 1 to 31 =1, 2, 3, ~, 9, A, B, C, ~, W, X, Y, exclude I, O, and U
L Product line # Line 1=1, Line 2=2, Line 3=3, …
NNNN Serial number Manufacturing sequence of product
(e) Customer’s barcode definition:
Serial ID: CM-40HHA-X-X-X-XX-L-XX-L-YMD-NNNN
Code Meaning Description
CM Supplier code CMI=CM
40HHA Model number V400H1-LHA=40HHA
X Revision code C1=1, C2=2, ……C9=9
Source driver IC code Century=1, CLL=2, Demos=3, Epson=4, Fujitsu=5, Himax=6,
X
Hitachi=7, Hynix=8, LDI=9, Matsushita=A, NEC=B, Novatec=C,
Gate driver IC code OKI=D, Philips=E, Renasas=F, Samsung=G, Sanyo=H, Sharp=I,
X
TI=J, Topro=K, Toshiba=L, Windbond=M
XX Cell location Tainan, Taiwan=TN
L Cell line # 1~12=0~C
XX Module location Tainan, Taiwan=TN
L Module line # 1~12=0~C
Year, month, day Year: 2001=1, 2002=2, 2003=3, 2004=4…
YMD Month: Jan. ~ Dec.=1, 2, 3, ~, 9, A, B, C
st st
Day: 1 to 31 =1, 2, 3, ~, 9, A, B, C, ~, W, X, Y, exclude I, O, and U
NNNN Serial number By LCD supplier

Κ03 Mar 2011
10. PACKAGING
10.1 PACKAGING SPECIFICATIONS
(1) 5 LCD TV modules / 1 Box
(2) Box dimensions : 1060(L)x378(W)x650(H)mm
(3) Weight : Approx. 44Kg(5 modules per carton)
(4) 5 LCD TV modules / 1 Box
(5) Box dimensions : 1060(L)x378(W)x650(H)mm
(6) Weight :
a. Panel module each pcs: 7.8 kg
b. Panel Packing Box
- Cushion: 1.55 kg (5pcs per box)
- Carton: 2.73 kg
- Panel: 7.8 kg x 5pcs = 39 kg
-Panel Packing Box Total (1 Box) =43.28 kg
c. Total Packing weight
1) For Vessel shipment Pallet (1 Pallet =3 Box or 6 Box)
- Pallet weight: 13.48 kg
- Pallet Cushion: 4.65 kg or 9.3 kg
- Pallet Packing Total = 143.32 kg or 273.16 kg
2) For Air shipment Pallet (1 Pallet =6 Box)
- Pallet weight: 13.48 kg
- Pallet Cushion: 9.3 kg
- Pallet Packing Total =273.16 kg

Κ03 Mar 2011
10.2 PACKAGING METHOD

Figures 10-1 and 10-2 are the packing method
Figure 10-1 packing method

Κ03 Mar 2011
Figure 10-2 packing method

Κ03 Mar 2011
11. MECHANICAL CHARACTERISTIC

Κ03 Mar 2011

Κ03 Mar 2011

Κ03 Mar 2011
Appendix – TWO Wire BUS INTRODUCTION

A.1 PIN ASSIGNMENT
51pins LVDS connector
Pin8: SCL
Pin9: SDA
A.2 I2C BUS APPLICATION NOTE

I2C bus: (The I2C bus must for MEMC only or prevent the I2C bus voltage drop down in initial state)
A.3 TWO WIRE BUS DEVICE ADDRESS

Two wire device address: default is 0x40, 1 byte
Two wire command: the range is 0x00 to 0xFF, 1 byte, see the two wire command table.

Κ03 Mar 2011

Datasheet PDF

Uploaded by

Copyright:

Available Formats

Datasheet PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Datasheet PDF

Uploaded by

Copyright:

Available Formats

Global LCD Panel Exchange Center www.panelook.

MODEL NO.: V400H1

Please return 1 copy for your confirmation with your

Approved By Checked By Prepared By

Chao-Chun Chung Josh Chi Joanne Chung

Version 2.0 1 DateΚ

1. GENERAL DESCRIPTION ......................................................................................................................................................... 5

2. ABSOLUTE MAXIMUM RATINGS .......................................................................................................................................... 7

3. ELECTRICAL CHARACTERISTICS ......................................................................................................................................... 9

5. INPUT TERMINAL PIN ASSIGNMENT................................................................................................................................ 16

7.2 OPTICAL SPECIFICATIONS ............................................................................................................................. 30

11. MECHANICAL CHARACTERISTIC .................................................................................................................................... 40

Appendix – TWO Wire BUS INTRODUCTION ........................................................................................................................ 43

Version 2.0 3 DateΚ

Version 2.0 4 DateΚ

Item Specification Unit Note

Active Area 885.6(H) x 498.15 (V) (40” diagonal) mm

Driver Element a-si TFT active matrix - -

Pixel Number 1920 x R.G.B. x 1080 pixel -

Pixel Arrangement RGB vertical stripe - -

Display Colors 1.07G color -

Display Operation Mode Transmissive mode / Normally Black - -

Surface Treatment Anti-Glare coating (Haze 11%) - (2)

Version 2.0 5 DateΚ

1.5 MECHANICAL SPECIFICATIONS

Horizontal (H) 951 952 953 mm (1)

Vertical (V) 550 551 552 mm (1)

Depth (D) 56.3 57.3 58.3 mm (3)

Version 2.0 6 DateΚ

2. ABSOLUTE MAXIMUM RATINGS

Storage Temperature TST -20 +60 ºC (1)

Operating Ambient Temperature TOP 0 50 ºC (1), (2)

Shock (Non-Operating) SNOP - 50 G (3), (5)

Vibration (Non-Operating) VNOP - 1.0 G (4), (5)

Version 2.0 7 DateΚ

2.2 PACKAGE STORAGE

Power Supply Voltage VCC -0.3 13.5 V

2.3.2 BACKLIGHT BALANCE BOARD UNIT

Lamp Voltage V Ё 3000 VRMS Lamp Voltage

Version 2.0 8 DateΚ

Power Supply Voltage VCC 10.8 12 13.2 V (1)

Rush Current IRUSH Ё Ё 4.25 A (2)

White Pattern Ё 15.12 18.24

Power consumption Black Pattern PT Ё 7.08 8.4 W (3)

Horizontal Stripe Ё 15.12 18.24

White Pattern Ё Ё 1.26 1.52 A

Power Supply Current Black Pattern Ё Ё 0.59 0.70 A (3)

Horizontal Stripe Ё Ё 1.26 1.52 A

Input High Threshold Voltage VIH 2.7 Ё 3.3 V

Version 2.0 9 DateΚ

Vcc rising time is 470us

Version 2.0 10 DateΚ

a. White Pattern b. Black Pattern

Active Area Active Area

Note (4) The LVDS input characteristics are as follows :

Version 2.0 11 DateΚ

3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION

Lamp Input Voltage VW - 840 - VRMS IL=14.5mA

Lamp Current IL 3 14.5 15 mARMS