5. Choose an IEEE 802.

11 wireless local area network (WLAN), review

published articles related to its performance evaluation, and make a list

of the benchmarks used in these articles.

Answer

One example of an IEEE 802.11 wireless local area network (WLAN) is IEEE 802.11n, a standard that was
first published in 2009 and provides higher data rates and improved coverage compared to previous
standards.

Several articles have been published on the performance evaluation of IEEE 802.11n WLANs. Some of
the benchmarks used in these articles include:

Throughput: The rate at which data is transmitted over the network, typically measured in bits per
second (bps) or packets per second (pps).

Data rate: The speed at which data is transmitted over the network, typically measured in megabits per
second (Mbps).

Signal-to-noise ratio (SNR): The ratio of the signal strength to the noise level, which affects the quality of
the wireless signal.

Packet error rate (PER): The percentage of packets that are lost or corrupted during transmission.

Latency: The time it takes for a packet to be transmitted from the sender to the receiver, typically
measured in milliseconds (ms).

Channel utilization: The percentage of time that the wireless channel is in use, which affects the
network's capacity.

Coverage area: The physical area over which the wireless signal can be received, typically measured in
square meters.
Interference: The level of interference caused by other wireless networks or devices, which can affect
the performance of the WLAN.

Mobility: The ability of the network to maintain a stable connection as a user moves around the
coverage area.

These benchmarks were used in different publications to evaluate the performance of IEEE 802.11n
WLANs under different conditions, such as different signal strength, different number of users, and
different types of traffic, in order to understand the capabilities and limitations of the standard.

6. Choose a multiprocessor computer system architecture. Review the

related published articles on its performance evaluation, and make a

list of the used performance metrics.

Answer

One example of a multiprocessor computer system architecture is the Cray XC50 supercomputer. The
Cray XC50 is a distributed memory, multi-node supercomputer that uses a combination of Intel Xeon
processors and NVIDIA GPUs.

Several articles have been published on the performance evaluation of the Cray XC50. Some of the
performance metrics used in these articles include:

Throughput: The rate at which the system processes data, typically measured in operations per second
or floating-point operations per second (FLOPS).

Latency: The time it takes for a request to be processed by the system, typically measured in
microseconds.

Scalability: The ability of the system to maintain or improve performance as the number of processors or
nodes increases.

Energy efficiency: The ratio of computation performance to energy consumption, typically measured in
FLOPS per watt.

Memory bandwidth: The rate at which data can be transferred to or from the system's memory,
typically measured in bytes per second.

I/O performance: The rate at which data can be transferred to or from external storage devices, typically
measured in bytes per second.

Memory capacity: The amount of memory available to the system.

Load balance: The distribution of workload across processors, to ensure that no processor is overworked
or underutilized.

These performance metrics were used in different publications to evaluate the performance of the Cray
XC50 under different workloads and configurations, in order to understand the system's capabilities and
limitations.

7. Select a measurement study of the performance evaluation of a computer

system or a communication network in which hardware monitors are

used in the study. Explain how useful such monitors are for providing

accurate and real measurement about the behavior of the system. Discuss

whether you can replace the hardware monitor by a software monitor,

and give the advantages and disadvantages for doing so.

Answer

One example of a measurement study that uses hardware monitors is "Performance Evaluation of an
InfiniBand Network Using Hardware Counters" by M. E. K. El-Hadidy et al. (2011). In this study, the
authors used hardware counters to measure the performance of an InfiniBand network, which is a high-
speed interconnect technology used in data centers. The hardware counters were used to measure
various performance metrics, such as packet rate, packet size, and packet loss, on the network's
switches and hosts.

Hardware monitors are useful for providing accurate and real measurements about the behavior of a
system because they are directly connected to the system's hardware and can measure various
performance metrics at the hardware level. This can provide a more accurate picture of the system's
behavior, as it eliminates the need to rely on software-based measurements that may be affected by the
system's software and operating system.

While it is possible to replace the hardware monitor with a software monitor, there are advantages and
disadvantages to doing so. The advantage of using a software monitor is that it can be easily
implemented and can provide measurements on a wide range of systems, regardless of the hardware.
However, the disadvantage of using a software monitor is that it can be affected by the system's
software and operating system, which can lead to inaccurate measurements.
In the case of this study, measuring the performance of an InfiniBand network, hardware counters were
essential to measure the packet rate and packet loss with high accuracy. Software-based monitoring
systems may not have been able to provide such accurate measurements, as they would have been
affected by the system's software and operating system.

In conclusion, hardware monitors are useful for providing accurate and real measurements about the
behavior of a system, particularly when it comes to high-speed networks or specialized systems.
However, software monitors can also provide useful measurements, but they may not be as accurate as
hardware monitors. The choice between hardware and software monitors will depend on the
requirements of the measurement study and the system being evaluated.

8. A workstation uses a 500-MHz processor with a claimed 100-MIPS

rating to execute a given program mix. Assume a one-cycle delay for

each memory access.

a. What is the effective cycle per instruction (CPI) of this machine?

b. Suppose that the processor is being upgraded with a 1000-MHz clock.

However, the speed of the memory subsystem remains unchanged,

and consequently, two clock cycles are needed per memory access. If

30% of the instructions require one memory access and another 5%

require two memory accesses per instruction, what is the performance

of the upgraded processor with a compatible instruction set and equal

instruction counts in the given program mix?

a. To calculate the effective CPI of the machine, we need to know the number of clock cycles it takes to
execute each instruction, including memory access time. If each memory access takes one clock cycle,
and 30% of the instructions require one memory access, then the total number of clock cycles spent on
memory access is 0.3 * 1 = 0.3. If 5% of the instructions require two memory accesses, then the total
number of clock cycles spent on memory access is 0.05 * 2 = 0.1. To find the total number of clock cycles
per instruction, we add the clock cycles spent on memory access to the number of clock cycles spent on
instruction execution, which is assumed to be 1. Therefore, the effective CPI of the machine is 1 + 0.3 +
0.1 = 1.4.

b. To calculate the performance of the upgraded processor, we need to know the number of clock cycles
per instruction and the clock frequency of the processor. The clock frequency of the upgraded processor
is 1000 MHz, which is twice as fast as the original processor. However, the memory subsystem remains
unchanged, so each memory access now takes two clock cycles instead of one. If 30% of the instructions
require one memory access, then the total number of clock cycles spent on memory access is 0.3 * 2 =
0.6. If 5% of the instructions require two memory accesses, then the total number of clock cycles spent
on memory access is 0.05 * 4 = 0.2. To find the total number of clock cycles per instruction, we add the
clock cycles spent on memory access to the number of clock cycles spent on instruction execution,
which is assumed to be 1. Therefore, the effective CPI of the upgraded machine is 1 + 0.6 + 0.2 = 1.8.

To calculate the performance of the upgraded processor, we divide the clock frequency of the processor
by the effective CPI. Therefore, the performance of the upgraded processor is 1000 MHz / 1.8 = 555.56
MIPS.

8. A linear pipeline processor has eight stages. It is required to execute a

task that has 600 operands. Find the speedup factor, Sk, assuming that

the CPU runs at 1.5 GHz. Note that the speedup factor of a

liner pipeline processor is defined by the following expression:

Sk=speedup=(time needed by a one-stage pipeline processor to do

a task)/(time needed by k-stage processor to do the same task)=T1/Tk.

Answer

The speedup factor, Sk, of a linear pipeline processor is the ratio of the time needed by a one-stage
pipeline processor to execute a task to the time needed by a k-stage pipeline processor to execute the
same task. To calculate the speedup factor for a processor with 8 stages, we first need to determine the
time needed by a one-stage pipeline processor to execute the task and the time needed by an 8-stage
pipeline processor to execute the same task.

Assuming that the CPU runs at 1.5 GHz, the time needed by a one-stage pipeline processor to execute
the task is the number of operands divided by the CPU clock frequency. Therefore, the time needed by a
one-stage pipeline processor to execute the task is 600 / 1.5 GHz = 0.4 us.

The time needed by an 8-stage pipeline processor to execute the same task is the number of operands
divided by the number of stages, divided by the CPU clock frequency. Therefore, the time needed by an
8-stage pipeline processor to execute the task is (600 / 8) / 1.5 GHz = 0.05 us.

The speedup factor, Sk, is the ratio of the time needed by a one-stage pipeline processor to execute the
task to the time needed by an 8-stage pipeline processor to execute the same task. Therefore, the
speedup factor, Sk, for an 8-stage pipeline processor is:
Sk = T1/Tk = 0.4 us / 0.05 us = 8

Therefore the speedup factor for 8 stages pipeline is 8.

9. A linear pipeline processor has eight stages. It is required to execute a

task that has 600 operands. Find the speedup factor, Sk, assuming that

the CPU runs at 1.5 GHz. Note that the speedup factor of a

liner pipeline processor is defined by the following expression:

Sk=speedup=(time needed by a one-stage pipeline processor to do

a task)/(time needed by k-stage processor to do the same task)=T1/Tk.

Answer

One way to devise an experiment to find out the performance metrics for an IEEE 802.3 LAN would be as
follows:

a. To measure the throughput of the network as a function of the number of nodes in the LAN, we can
use a network traffic generator to send a large amount of data packets to the LAN. We can then
measure the number of packets that are successfully received by the destination node, and divide that
by the time it took to send the packets. We can repeat this process for different numbers of nodes in the
LAN, and plot the results to see how the throughput changes with the number of nodes.

b. To measure the average packet delay as a function of the number of nodes in the LAN, we can use a
network traffic generator to send a large number of packets to the LAN. We can then measure the time
it takes for each packet to be successfully received by the destination node. We can calculate the
average delay for each number of nodes in the LAN, and plot the results to see how the delay changes
with the number of nodes.

c. To measure the throughput-delay relationship, we can use the data obtained from the previous two
steps and plot them on a graph with throughput on the x-axis and delay on the y-axis. This will show us
how the delay changes as the throughput of the network increases.
It's important to note that the experiment should be executed with different loads, packet sizes, and
distances between nodes to have a better understanding of the network behavior under different
conditions.