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    Co 4&5 Questionbank SE23

    Uploaded by

    Rajeshwari R P
    This document contains questions from multiple modules related to computer engineering. It includes questions about data path organization in a processor, control unit designs, arithmetic operations like addition and multiplication using different approaches, pipelining, and parallel processing techniques. The questions are meant to be answered in internal assessment tests for computer science students.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Co 4&5 Questionbank SE23

    Uploaded by

    Rajeshwari R P
    26 views4 pages
    This document contains questions from multiple modules related to computer engineering. It includes questions about data path organization in a processor, control unit designs, arithmetic operations like addition and multiplication using different approaches, pipelining, and parallel processing techniques. The questions are meant to be answered in internal assessment tests for computer science students.

    Original Title

    co4&5questionbankSE23

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    © © All Rights Reserved

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    This document contains questions from multiple modules related to computer engineering. It includes questions about data path organization in a processor, control unit designs, arithmetic operations like addition and multiplication using different approaches, pipelining, and parallel processing techniques. The questions are meant to be answered in internal assessment tests for computer science students.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    26 views4 pages

    Co 4&5 Questionbank SE23

    Uploaded by

    Rajeshwari R P
    This document contains questions from multiple modules related to computer engineering. It includes questions about data path organization in a processor, control unit designs, arithmetic operations like addition and multiplication using different approaches, pipelining, and parallel processing techniques. The questions are meant to be answered in internal assessment tests for computer science students.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 4

    RAO BAHADUR Y.

    MAHABALESWARAPPA ENGINEERING COLLEGE, BELLARY


    DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

    Module 4 imp questios


    Q
    Basic Processing unit QUESTIONS
    No

    Q5 a) Explain the Single Bus Organization for data path inside a processor.
    b) Write the control sequence for the instruction Move R1,R2

    Q6 Explain with diagram the Hard Wired control unit. Compare hardwired and micro programmed
    approach.

    a) Explain the block diagram of complete Processor.


    Q7 b) write the control sequence for the instruction Add (R3), R1 on single bus architecture
    c) Analyze how execution of complete instruction is carried out .

    Explain Hard wired Control unit organization in a processing unit.


    or
    Q8 What is the purpose of Control unit. with neat sketch Explain Hard wired Control unit
    organization in a processing unit.

    What do you mean by micro-instruction? Design Basic Organisation of a micro


    9 programmed control unit with diagram
    Compare Hardwired control and Microprogram control

    10 Discuss the concept of Gating of registers. Also discuss the fetching of word .

    Write the sequence of control steps required for single bus structure for each of
    the following instructions.
    11 (i) Add the contents of memory location NUM to register R1.
    Add the contents of memory location whose address is at memory location NUM to
    register R1.
    RAO BAHADUR Y. MAHABALESWARAPPA ENGINEERING COLLEGE, BELLARY
    DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

    (Arithmetic) unit –Module 4

    Questions Year
    Jan17,19(17s)
    1 Draw 4-bit carry look ahead adder and explain (its operation) June18,17
    2 Explain the generation and propagation functions used in Carry look ahead adder. Also June19
    Comment on the delays in the circuit
    3 Design 16 bit carry look ahead adder using 4-bit adder. Unite the expression for Ci+1. Jan18
    Design and explain the working of 16 bit carry look ahead adder built from 8 bit carry look
    4 ahead adder. Jan19

    5 Design a logic circuit to perform addition/subtraction of ‘n’ bit number X and Y Jan17,18
    Perform the operations on 5-bit signed numbers using 2’s complement system. Also
    indicate whether overflow has occurred.
    June18, 17
    6  (i) (-10)+(-13) (ii) (-10) – (-13) (iii) (-2) + (-9) Jan18
     (ii) (-9) + (-7) (ii) (+7) – (-8)
     (iii) 5+10 (iii) -14 + 11 (iii) -5 + 7 (iv) -10 + -13
    7 With an example, explain the booths algorithm to multiply 2 signed operands (write steps) Jan18,June19
    8 Perform multiplication for 13 and 09 using booth’s algorithm. (explain booth’s process) Jan17,19(17s)
    9 Explain how Sequential Multiplication is carried out with diagram. Illustrate with suitable
    example

    Module -5

    1. Define Pipelining . Explain 4 segment pipelining with necessary diagram.

    2. Explain how vector processing is handled in vector processor with suitable


    diagram

    3. Explain basic idea of Instruction Pipelining

    4. Explain Arithmetic pipelining with respect to floating point operations. Draw


    the flow diagram with example.

    5. Explain Array Processors with suitable example

    6. Define parallel processing. Explain Flyn’s Classification of Computers .

    7. Draw a Space time diagram for six segment pipeline showing the time it takes
    to process 8 tasks
    RAO BAHADUR Y. MAHABALESWARAPPA ENGINEERING COLLEGE, BELLARY
    DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

    INTERNAL ASSESSMENT TEST-II 2017-18 (ODD Sem)

    STAFF NAME:- SEM:- SEC:-

    COURSE NAME:- COURSE CODE:-

    DATE:- TIME:- MAX MARKS:-

    Note: - Answer any five question, each question carries 6 marks

    Q
    QUESTIONS Marks BTL CO PO
    No

    Q1

    OR

    Q2

    Q3

    OR

    Q4

    Q5

    OR

    Q6

    Q7

    OR

    Q8

    Q9

    OR

    Q10

    Blooms Taxonomy (BTL) Course Outcome (CO) Program Outcome (PO)


    RAO BAHADUR Y. MAHABALESWARAPPA ENGINEERING COLLEGE, BELLARY
    DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

    INTERNAL ASSESSMENT TEST-III 2017-18 (ODD Sem)

    STAFF NAME:- SEM:- SEC:-

    COURSE NAME:- COURSE CODE:-

    DATE:- TIME:- MAX MARKS:-

    Note: - Answer any five question, each question carries 6 marks

    Q
    QUESTIONS Marks BTL CO PO
    No

    Q1

    OR

    Q2

    Q3

    OR

    Q4

    Q5

    OR

    Q6

    Q7

    OR

    Q8

    Q9

    OR

    Q10

    Blooms Taxonomy (BTL) Course Outcome (CO) Program Outcome (PO)

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