Amit EDKCON2022
Amit EDKCON2022
Amit EDKCON2022
Abstract— This paper gives a detailed and comprehensive current to off-current ratio (ION/IOFF). Both these parameters
insight for the simulation based investigation of doping have their own significance in defining the capabilities of
induced modulation of the threshold voltage and ION/IOFF ratio the device for various applications. This work helps in
in a silicon based surrounding gate metal oxide semiconductor understanding and explaining that how the doping pattern
field effect transistor (SG-MOSFET). This work explores the
can modulate the threshold voltage and ION/IOFF ratio of the
two important DC characteristics i.e. threshold voltage and
ION/IOFF ratio which are important to investigate the analog device. A low value of threshold voltage[7] is generally
performance of MOSFET. The current study shows that the desirable because it is the minimum gate voltage required to
low doping of source, channel and drain results in low turn-on the device. So, Vt can be considered as an offset
threshold voltage but also, decreases the ION/IOFF ratio. voltage whose value must be low. A low threshold voltage
Interestingly, keeping the drain doping higher than the source indicates lesser overdrive voltage and it is always desirable
doping improves the threshold voltage but degrades the to have less threshold voltage in short channel devices since
ION/IOFF ratio. The maximum change in threshold voltage and these devices operate at low power ratings. On-current to
ION/IOFF ratio is approximately 430 mV and 106 times off-current ratio[8]–[10] signifies the switching
respectively which is obtained when the doping of the source,
characteristics of the device which indicates that how
channel and drain are changed simultaneously by a factor of
1:106. The doping of source, channel and drain can rapidly a device can switch from on-state to off-state or vice
significantly affect the threshold voltage and ION/IOFF ratio in versa. A high ION/IOFF ratio is desirable in digital switching
short channel devices which necessitates the need of doping and a few high frequency applications.
optimization to control both these characteristics.
Fig. 1 shows the effect of biasing on the energy bands of
Keywords— ATLAS TCAD, doping, off-current, on-current, a MOSFET[9] where Fig. 1(a) shows the effect of gate bias
surrounding gate MOSFET, threshold voltage. and Fig. 1(b) shows the effect of drain bias. Increasing the
gate voltage enables channel formation and as a result,
I. INTRODUCTION charge carriers start moving from the source to drain
Field effect transistors have many practical applications because of lowering of the potential hill across the junction.
and advantages which made it popular in the recent Increasing the drain voltage makes the drain junction more
decades[1]–[5]. The latest advancement in technology has reverse biased and hence the bands around the drain
led to the improvement in its device structure and junction moves downward resulting in flow of more charge
fabrication process. SG-MOSFET being the most widely carriers from the source to drain. Many authors have
used variant of MOSFET can be used for numerous discussed the concept of threshold voltage modeling and
important applications[3], [6]. A basic variant of SG- ION/IOFF ratio in the past but the dependency of these two
MOSFET has been considered to study the doping induced parameters on the doping profile have not been discussed
modulation of two important parameters (essential for much in details [11]–[16]. To study the doping induced
analog applications) i.e., threshold voltage (Vt) and on- modulation in a systematic and diagrammatic approach, the
Authorized licensed use limited to: DELHI TECHNICAL UNIV. Downloaded on March 15,2023 at 06:54:17 UTC from IEEE Xplore. Restrictions apply.
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), 26-27 November, 2022, Kolkata, India 76
TABLE I
STRUCTURAL PARAMETERS OF SG-MOSFET
Parameters Value
Channel length 30 nm
Channel radius 10 nm
Work function Φgate
(ϕgate) 4.8eV (WSi2)/5eV(Co)/5.1eV(Au)
1st part 1*1010 cm-3
nd
Channel doping 2 part 1*1010 cm-3
rd
(p-type) 3 part 1*1012 – 1*1018 cm-3
th
4 part 1*1015 – 1*1018 cm-3
st
1 part 1*1012 – 1*1018 cm-3
nd
Source doping 2 part 1*1015 cm-3
rd
(n-type) 3 part 1*1012 – 1*1018 cm-3
Fig. 1. Effect of the (a) gate voltage (VGS) and (b) drain voltage (VDS) on th
4 part 1*1018 cm-3
the energy bands (conduction and valence band) in a conventional st
MOSFET. 1 part 1*1012 – 1*1018 cm-3
nd
Drain doping 2 part 1*1015 – 1*1018 cm-3
paper has been further divided into four subsections with (n-type) rd
3 part 1*1012 – 1*1018 cm-3
each subsection revealing some interesting pattern in the th
4 part 1*1018 cm-3
threshold voltage and ION/IOFF ratio modulated by the
Biasing VGS = (0-1)V VDS=0.5V
doping of the source, channel and drain.
Oxide layer
II. DEVICE DESIGN AND SIMULATION 3 nm
thickness(tox)
Fig. 2(a) and 2(b) shows the 3D (three dimensional) and
Oxide
2D (two dimensional) view of SG-MOSFET respectively. 30 nm
length(Lox)
The whole bar of the semiconductor is made up of silicon
and the gate dielectric used is silicon dioxide (SiO2). Work
function of the gate is 5.1 eV. VDS=1 V
-6 tox=13 nm
10
LG=50nm
NCh=2*1015/cm3
Drain Current (A)
10-7 NS=ND=1021/cm3
10-8
10-9
Fig. 2. (a) 3-D view and, (b) 2-D view of the investigated SG-MOSFET. 10-10 Simulation
Experimental
All the simulations have been performed on the latest
10-11
version of ATLAS TCAD[17]. Different models have been -1.0 -0.5 0.0 0.5 1.0
used to incorporate the various effects in the SG-MOSFET (c) Gate Voltage (VGS: Volts)
such as Lombardi CVT model which is a carrier mobility
Fig. 2. (c) Calibration of SG-MOSFET with the experimental data.
model, SRH model which is a recombination model,
CONMOB model which is a concentration dependent III. RESULTS AND DISCUSSION
mobility model and FLDMOB model which is a field
dependent mobility model. The complex multi-dimensional The impact of varying the doping of source, drain and
differential equations have been solved by using NEWTON channel has a visible effect on threshold voltage and
GUMMEL method in the simulator which is a powerful ION/IOFF ratio. Thus, doping modulates the threshold voltage
Authorized licensed use limited to: DELHI TECHNICAL UNIV. Downloaded on March 15,2023 at 06:54:17 UTC from IEEE Xplore. Restrictions apply.
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), 26-27 November, 2022, Kolkata, India 77
Authorized licensed use limited to: DELHI TECHNICAL UNIV. Downloaded on March 15,2023 at 06:54:17 UTC from IEEE Xplore. Restrictions apply.
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), 26-27 November, 2022, Kolkata, India 78
Fig. 7. (a) Threshold voltage and (b) ION/IOFF ratio at different doping in
SG-MOSFET. Fig. 9. (a) Threshold voltage and (b) ION/IOFF ratio at different doping in
SG-MOSFET.
C. Increasing the source/channel/drain doping at same rate
D. Varying the channel doping
Doping variations in the source, channel and drain
Channel doping (drain and source doping are kept
affects both the threshold voltage and the ION/IOFF ratio[8] in
constant) affects the flow of charge carriers and hence
SG-MOSFET [13], [19] when the source, channel and drain
affects the threshold voltage and ION/IOFF ratio. A reference
doping are increased at an equal rate. The doping of source,
doping has been selected for this subsection: source doping:
drain and channel is kept same but it must not be confused
1018 /cm3, channel doping: 1018 /cm3, drain doping: 1018
with junction-less transistors. Here, source and drain is n-
/cm3. When the doping of the channel is decreased, less gate
type semiconductor whereas the body or substrate is of p-
voltage is required for the channel formation which implies
type semiconductor. Fig. 8 diagrammatically explains the
a reduction in the threshold voltage. This principle is
effect of increasing the doping of source, channel and drain
diagrammatically described in the Fig. 10. Fig. 11(a) and
at an equal rate.
11(b) shows the variation of threshold voltage and ION/IOFF
ratio when the doping of channel is decreased from the
reference doping level in SG-MOSFET.
Authorized licensed use limited to: DELHI TECHNICAL UNIV. Downloaded on March 15,2023 at 06:54:17 UTC from IEEE Xplore. Restrictions apply.
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), 26-27 November, 2022, Kolkata, India 79
Fig. 11. (a) Threshold voltage variation and (b) ION/IOFF ratio at different
doping in the investigated SG-MOSFET.
Fig. 14. Electron density and corresponding current density lines variation
at (a) VDS=0.45V and (b) VDS=0.55V.
Fig. 12. (a) Threshold voltage and (b) ION/IOFF ratio at different gate work
functions (ϕgate=4.8/5/5.1 eV) in SG-MOSFET.
Fig. 13. (a) Threshold voltage and (b) ION/IOFF ratio at different drain
voltage (VDS=0.45/0.5/0.55V) in SG-MOSFET.
Authorized licensed use limited to: DELHI TECHNICAL UNIV. Downloaded on March 15,2023 at 06:54:17 UTC from IEEE Xplore. Restrictions apply.
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), 26-27 November, 2022, Kolkata, India 80
Table II compares the threshold voltage and ION/IOFF [6] A. Das, S. Rewari, B. K. Kanaujia, and R. S. Gupta, “Recent
Technological Advancement in Surrounding Gate MOSFET for
ratio in the SG-MOSFET with the different existing
Biosensing Applications - a Synoptic Study,” Silicon, vol. 14, no. 10,
variants of MOSFET. The threshold voltage is lowest and pp. 5133–5143, 2022.
ION/IOFF ratio is highest for SG-MOSFET (our structure). [7] A. Kranti, S. Haldar, and R. S. Gupta, “Analytical model for
threshold voltage and I-V characteristics of fully depleted short
channel cylindrical/surrounding gate MOSFET,” Microelectron.
TABLE II Eng., vol. 56, no. 3–4, pp. 241–259, 2001.
COMPARISON OF Vt AND ION/IOFF RATIO IN [8] K. Jang, T. Saraya, M. Kobayashi, and T. Hiramoto, “Ion/Ioff ratio
SG MOSFET WITH EXISTING STRUCTURES enhancement and scalability of gate-all-around nanowire negative-
capacitance FET with ferroelectric HfO2,” Solid. State. Electron.,
vol. 136, pp. 60–67, 2017.
Ref A[21] Ref B[22] Our Structure
[9] S.-M. Kang and L. Yusuf, CMOS Digital Integrated Circuits, 3rd ed.
Vt 0.41V 0.64V 0.384V 2003.
[10] S. S. Adel and K. C.Smith, Microelectronics Circuit, 8th ed. Oxford,
ION/IOFF Ref C[23] Ref D[24] Our Structure 2020.
Ratio 8.2*106 8.36*108 2.3535*1010 [11] A. Asenov, “Random dopant induced threshold voltage lowering and
fluctuations in sub-0.1 fjim MOSFET’s: A 3-D ‘atomistic’ simulation
study,” IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2505–
IV. CONCLUSION 2513, 1998.
[12] H. Koura, M. Takamiya, and T. Hiramoto, “Optimum conditions of
This paper focuses on the doping induced modulation of body effect factor and substrate bias in variable threshold voltage
threshold voltage and ION/IOFF ratio in a SG-MOSFET. The MOSFETs,” Jpn. J. Appl. Phys., vol. 39, pp. 2312–2317, 2000.
paper is divided into four subsections to study the effect of [13] T. Mangla, A. Sehgal, M. Saxena, and S. Haldar, “Optimization of
Gate Stack MOSFETs with Quantization Effects,” J. Semicond.
doping on both the DC parameters. A lower threshold
Technol. Sci., vol. 4, no. 3, pp. 228–239, 2004.
voltage is obtained at low doping of source and drain while [14] A. Gnudi, S. Reggiani, E. Gnani, and G. Baccarani, “Analytical
higher ION/IOFF ratio is obtained at the high doping of source model for the threshold voltage variability due to random dopant
and drain. Keeping the drain doping higher than that of fluctuations in junctionless FETs,” IEEE Electron Device Lett., vol.
33, no. 3, pp. 336–338, 2012.
source doping will keep the threshold voltage low but
[15] R. Remmouche, N. Boutaoui, and H. Bouridah, “Compact modeling
slightly degrades the ION/IOFF ratio. Better results for for submicron fully depleted SOI MOSFET’s,” Acta Phys. Pol. A,
ION/IOFF ratio are obtained when channel doping is kept high vol. 121, no. 1, pp. 190–192, 2012.
whereas better results for threshold voltage are obtained [16] K. Beigi and S. A. Hashemi, “Increasing ION/IOFF by embedding a
low doped buried layer in the channel of a dual-material double-gate
when channel doping is kept low. In general, low doping of
junctionless MOSFET,” Int. J. Numer. Model. Electron. Networks,
source, channel and drain will ensure a low threshold Devices Fields, vol. 33, no. 1, pp. 1–15, 2020.
voltage whereas high doping of source, channel and drain [17] ATLAS User’s Manual: Device Simulation Software, Santa Clara,
will ensure a high ION/IOFF ratio in a SG-MOSFET. So, CA, USA, 2018.
[18] S. J. Choi, D. Il Moon, S. Kim, J. P. Duarte, and Y. K. Choi,
optimization in doping is needed to get a low threshold
“Sensitivity of threshold voltage to nanowire width variation in
voltage and a high ION/IOFF ratio. This paper laid down the junctionless transistors,” IEEE Electron Device Lett., vol. 32, no. 2,
basic framework to study the doping induced modulation of pp. 125–127, 2011.
threshold voltage and ION/IOFF ratio in similar short channel [19] R. Mahajan and D. K. Gautam, “Analytical Study of Effect of
Channel Doping on Threshold Voltage of Metal Gate High-k SiGe
devices.
MOSFET,” Silicon, vol. 10, no. 1, pp. 85–90, 2018.
REFERENCES [20] F. Liu et al., “A charge-based model for long-channel cylindrical
surrounding-gate MOSFETs from intrinsic channel to heavily doped
[1] A. Sirohi, C. Sahu, and J. Singh, “Analog/RF Performance body,” IEEE Trans. Electron Devices, vol. 55, no. 8, pp. 2187–2194,
Investigation of Dopingless FET for Ultra-Low Power Applications,” 2008.
IEEE Access, vol. 7, pp. 141810–141816, 2019. [21] K. P. Pradhan, M. R. Kumar, S. K. Mohapatra, and P. K. Sahu,
[2] S. Ahmad, N. Alam, and M. Hasan, “Robust TFET SRAM cell for “Analytical modeling of threshold voltage for Cylindrical Gate All
ultra-low power IoT applications,” In: 2017 Int. Conf. Electron Around (CGAA) MOSFET using center potential,” Ain Shams Eng.
Devices Solid-State Circuits, pp. 1–2, 2017. J., vol. 6, no. 4, pp. 1171–1177, 2015.
[3] A. Jain, S. K. Sharma, and B. Raj, “Design and analysis of high [22] I. K. M. R. Rahman, M. I. Khan, and Q. D. M. Khosru, “Electrostatic
sensitivity photosensor using Cylindrical Surrounding Gate characterization and threshold voltage modeling of inversion type
MOSFET for low power applications,” Eng. Sci. Technol. an Int. J., InGaAs gate-all-around MOSFET,” J. Comput. Electron., vol. 20,
vol. 19, no. 4, pp. 1864–1870, 2016. no. 4, pp. 1504–1512, 2021.
[4] H. Sood, V. M. Srivastava, and G. Singh, “Advanced MOSFET [23] S. Rewari, R. S. Gupta, S. S. Deswal, and V. Nath, “Silicon carbide
technologies for next generation communication systems - based DSG MOSFET for high power, high speed and high frequency
Perspective and challenges: A review,” J. Eng. Sci. Technol. Rev., applications,” In: 2014 IEEE 6th India Int. Conf. Power Electron.,
vol. 11, no. 3, pp. 180–195, 2018. pp. 1–4, 2014.
[5] A. Das, B. K. Kanaujia, V. Nath, S. Rewari, and R. S. Gupta, [24] F. N. A. K. Agha, Y. Hashim, and M. N. Shakib, “Temperature
“Impact of Reverse Gate Oxide Stacking on Gate All around Tunnel Impact on the ION/IOFF Ratio of Gate All around Nanowire TFET,”
FET for High Frequency Analog and RF Applications,” 2020 IEEE In: 2020 IEEE Int. Conf. Semicond. Electron., pp. 1–4, 2020.
17th India Counc. Int. Conf. INDICON 2020, pp. 1–6, 2020.
Authorized licensed use limited to: DELHI TECHNICAL UNIV. Downloaded on March 15,2023 at 06:54:17 UTC from IEEE Xplore. Restrictions apply.