Current Directions in Biomedical Engineering 2016; 2(1): 87–90

Open Access

Andreas Bahr*, Lait Abu Saleh, Dietmar Schroeder and Wolfgang H. Krautschneider

High speed digital interfacing for a neural data

acquisition system
Enabling of live display functionality for a neural recording system

DOI 10.1515/cdbme-2016-0022
1 Introduction
Abstract: Diseases like schizophrenia and genetic epilepsy
are supposed to be caused by disorders in the early de- Disorders in the early development of the brain could lead
velopment of the brain. For the further investigation of to diseases like certain forms of schizophrenia and genetic
these relationships a custom designed application spe- epilepsy [1, 2]. This hypothesis of neural development from
cic integrated circuit (ASIC) was developed that is op- Ben-Ari et al. and Lewis et al. [1, 2] is investigated with
timized for the recording from neonatal mice [Bahr A, the help of genetic mouse disease models. Recent nd-
Abu-Saleh L, Schroeder D, Krautschneider W. 16 Channel ings of Marguet et al. [3] showed that by treatment at a
Neural Recording Integrated Circuit with SPI Interface and critical stage of the brain development the rescue from a
Error Correction Coding. Proc. 9th BIOSTEC 2016. Biode- genetic epilepsy could be possible. To further investigate
vices: Rome, Italy, 2016; 1: 263; Bahr A, Abu-Saleh L, these relationships, the signals from neonatal mice have
Schroeder D, Krautschneider W. Development of a neural to be analysed. A custom designed application specic
recording mixed signal integrated circuit for biomedical integrated circuit (ASIC) was developed that is optimized
signal acquisition. Biomed Eng Biomed Tech Abstracts for recordings in neonatal mice [4–6].
2015; 60(S1): 298–299; Bahr A, Abu-Saleh L, Schroeder D, For the recording of the neural signals from the head
Krautschneider WH. 16 Channel Neural Recording Mixed of the mouse a Neuronexus multichannel electrode [7] is
Signal ASIC. CDNLive EMEA 2015 Conference Proceedings, placed in the cortex of the mouse. The correct placement of
2015.]. To enable the live display of the neural signals the electrodes is essential to enable the neural recording.
a multichannel neural data acquisition system with live Saving the data to a memory and analysing it after the
display functionality is presented. It implements a high recording is not feasible during experiments with living
speed data transmission from the ASIC to a computer with animals. The adjustment of the electrode would take much
a live display functionality. The system has been success- too long and the animal would be stressed longer than
fully implemented and was used in a neural recording of a necessary.
head-xed mouse. To enable the live display of the neural signals, a
neural recording data acquisition system is presented. It
Keywords: high speed digital interfacing; live display
implements a high speed data transmission from the ASIC
of neural data; neural data acquisition system; neural
to a computer with a live display functionality of the neural
recording system.
data. High-speed data acquisition systems based on FPGA
have been presented in [8, 9]. To adopt to the specic needs
of the custom designed ASIC, a custom designed digital
interfacing had to be developed.

*Corresponding author: Andreas Bahr, Institute of Nano- and 2 Material and methods
Medical Electronics, Hamburg University of Technology, D-21073
Hamburg, Eiûendorfer Str. 38, Germany, E-mail: [email protected]
Lait Abu Saleh, Dietmar Schroeder and Wolfgang H.
The neural recording system is designed in such a way that
Krautschneider: Institute of Nano- and Medical Electronics, it adopts to the custom designed integrated circuit and that
Hamburg University of Technology, D-21073 Hamburg, Germany it ts into the environment of the neuroscience. Existing
© 2016 Andreas Bahr et al., licensee De Gruyter.
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivs 4.0 License.
88  A. Bahr et al.: High speed digital interfacing for a neural data acquisition system

interfaces like Neuroscope [10] are integrated to enable an used [10]. Neuroscope is a widely used interface in the
easy handling of the interfaces for the experimenters. The neuroscientic community. A diagram of the data ow on
selection of the eld programmable gate array (FPGA) is the computer is shown in Figure 2.
based on the system requirements and inuenced by the
wide spread existence of the opal Kelly Interface board [11],
that is used by the open source community open ephys [12] 2.2.2 Data acquisition board
or the company Intan [13].
The data acquisition board consists of an FPGA Interface
board (XEM 6010) from the company Opal Kelly [11], a
2.1 Specication and system requirements power supply unit for the integrated circuit and connectors
for interfacing. A block diagram of the data acquisition
The acquisition system interfaces to a custom designed board is shown in Figure 3. The Interface Board consist of
integrated circuit [4, 14]. The circuit with the size of only a Xilinx Spartan 6 FPGA, an SDRAM for buering, a Phase
1.5 × 1.5 mm2 comprises of 16 analog inputs that are sam- Locked Loop (PLL) for clock generation and a USB Micro
pled with 20 kS/s/channel at an ADC resolution of 10 bit. Interface block. The board communicates through a High-
The recording using a single integrated circuit results in a speed USB 2.0 Interface with the computer (data rate up to
data rate of 3.52 Mb/s [4]. 38 Mb/s). The FPGA works at 100 MHz and has sucient
The ASIC implements a four wire serial peripheral speed to handle the required data rate. The board includes
interface (SPI) with an additional signal from the ana- an extra memory of 128 Mb SDRAM.
logue to digital conversion (ADC). This additional end of The Opal Kelly board integrates a communication
conversion (EoC) signal is used as an interrupt to signal library that is provided from the manufacturer. The library
that a new sampled value is available. To handle this takes care of the communication between the FPGA on the
interrupt, a custom SPI master interface is implemented board and a program on the computer by providing end-
on the FPGA that requests the data from the ASIC each time points. By integration of the library into the C++ code and
the interrupt is triggered. the verilog code, data can be transmitted between the com-
puter and the FPGA by handing over the data to endpoints.

2.2 Neural data acquisition system

2.2.3 The control program
A block diagram of the designed neural data acquisition
system is shown in Figure 1. The ASIC communicates with The data acquisition system and the SPI master are
the acquisition board through a SPI interface. For the controlled by the control program, the program is written
communication between the acquisition board and the
computer a USB connection was chosen [14]. The purpose
of the ASIC is the recording of the neural data and the
acquisition board transmits the data to the computer. The Control Writes Binary Reads Neuroscope:
program Data file Data live display
data is shown immediately on screen in a live mode.

Figure 2: Data flow diagram on the computer: the control program

writes the data into a binary le. The data is then simultaneously
2.2.1 Control programm and live display
read from the binary le with the program Neuroscope and
displayed in a live mode.
For the controlling of the neural recording system a con-
trol program was developed that is running on the com-
puter. This program writes the data into a binary .dat le. Power
SDRAM
For the live display of the data the tool Neurosccope is SPI
FPGA
supply

PLL
USB 2.0 Data
SPI Data USB USB micro acquisition
Integrated Computer
circuit acquisition board
(live display) Opal kelly interface board
board

Figure 1: Block diagram of the neural data acqusisition system [14]. Figure 3: Block diagram of the data acquisition board.
 A. Bahr et al.: High speed digital interfacing for a neural data acquisition system  89

Start

Number of words in
FIFO > Threshold?

No
Yes

Request data
and write to Binary file
file

Figure 5: State machine of the SPI master.

Termination
condition?
No
and to read the neural data from the SPI slave and write it
Yes into a buer on the FPGA.
End The SPI master is implemented as a nal state ma-
chine. The state machine is depicted in Figure 5.
Figure 4: Flow chart of the data acquisition phase of the control The ASIC is designed in a way that it can work with
program. a wide range of clock frequencies. The clock is provided
externally to the ADC. The lowest available clock from the
in C++. The program splits into two parts: A system con- PLL is approximately 2 MHz. To generate clock signals
guration phase where the communication system param- in the kilo Hertz range, a congurable frequency clock
eters are initialized and the recording parameters are set generator was implemented. It divides the clock from the
and a data acquisition phase, where the data is requested PLL down by powers of two in the range of 20 to 28 .
from the board and written into a le on the PC-memory For communication the OkLibrary was integrated, this
(hard drive). library provides communication endpoints [11].
In the rst step of the conguration phase the recoding The data is written by the SPI master into a buer. The
parameters of the control program are specied. Then a buer is implemented as a 128 Mb SDRAM FIFO.
connection to the FPGA is established and the FPGA is The ASIC sends data packages of 22 bits to the SPI mas-
programmed by loading the bit le. The SPI and ADC ter, this contains the data of two channels per SPI-block. To
clocks are congured and started. Finally the integrated transmit the data to the PC two packages are put together
circuit is congured to the mode of operation. into a container of 64 bis, to t into multiples of 8. The
In the data acquisition phase the data transfer from packages are saved into a buer on the interface board. As
the FPGA to the PC is controlled by the counter “Availal- soon as 2048 packages of 64 data bits are available, this
beWordsInFIFO”. This counter holds the number of words data set is transmitted to the C++ program on the PC.
that are stored in the buer on the data acquisition board.
The control program continuously checks the size of this
counter. If the value exceeds a threshold the specied 3 Results
number of words is picked up from the FIFO and written
into the .dat le. This process continues until the specied The presented system is successfully implemented and
number of words is recorded. used in a neural recording of an adult mouse. An
For the implementation functions and libraries acute silicon probe (50 µm inter-site spacing) [7] was
from OkLibrary.lib from Opal Kelly and from IntanTech used in a recording in the hippocampus of a urethane-
rhd2000evalboar.lib are used [11, 13]. anaesthetized adult head xed mouse. The neural signals
from the cortex of the mouse were recorded with the data
acquisition system and the data was displayed in the live
2.2.4 FPGA implementation with SPI master view modus during the recording. The system worked at
a data rate of 3.5 Mb/s. The control program writes to
The FPGA implements the SPI master, a buer, a vari- the .dat le and the Neuroscope program reads from the
able frequency clock generator and the communication same le at the same time. Figure 6 shows an example low
endpoints. The task of the SPI master is to write the eld potential (LFP) of a sharp wave-ripple event (SPW-R)
conguration le to the SPI slave on the integrated circuit recorded with the system.
90  A. Bahr et al.: High speed digital interfacing for a neural data acquisition system

A this study. Ethical approval: The research related to ani-

3 mals complies with all the relevant national regulations
4
and institutional policies for the care and use of animals.
5
6
7
Depth (hpc)

8
9
10 References
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Channel Neural Recording Integrated Circuit with SPI Interface

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4 Conclusion
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Acknowledgment: We would like to thank R. Hinsch,
[11] Opal Kelly Incorporated. Opal Kelly XEM6010 User’s
D. Isbrandt and his Team from the DZNE-German Center Manual. Portland: Opal Kelly Incorporated, 2010. url:
for Neurodegenerative Diseases Cologne for the support http://assets00.opalkelly.com/library/ XEM6010-UM.pdf
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[13] Intan Technologies. USB/FPGA Interface: Rhythm. Intan
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2016).
German Research Foundation, Priority Program SPP1665.
[14] Bahr A, Abu-Saleh L, Schroeder D, Krautschneider W.
Conict of interest: Authors state no conict of interest. Integrierter Schaltkreis zur Aufnahme von Biosignalen In:
Material and Methods: Informed consent: Informed con- "Proceedings of the Workshop Biosignal Processing". Berlin,
sent has been obtained from all individuals included in Germany, April 7–8, 2016.