Proceedings of the International MultiConference of Engineers and Computer Scientists 2010 Vol II,

IMECS 2010, March 17 - 19, 2010, Hong Kong

FPGA-Based Multi Protocol Data Acquisition

System with High Speed USB Interface
S. Thanee S. Somkuarnpanit and K. Saetang

AbstractWe have proposed a data acquisition system
with high speed USB interface using FPGA chip as the
main processing unit. Since the FPGA has a number of
modules on chip, which can operate independently, it can
be utilized for the data acquisition system with
multi-channels for the connection to four ADC signals
with four different protocols of Parallel, SPI, I2C and
one-wire protocol. The system is controlled by the
software written in the visual C++. It allows the user to be
able to interface to a PC for data restoration and Figure 1 The overall system diagram.
monitoring. We found that this system can perform data
acquisition with high rate data transfer. Firstly, the PC will check the FPGA for data availability on
the system. After that it will send a set of the instructions to
Index Terms Data acquisition, high-speed USB, FPGA. the FPGA for getting these data from USB port. The data
will be interpreted into separate data bytes for the individual
I. INTRODUCTION
channels. Finally, the data can be shown to the user, and
The data acquisition system is broadly utilized in a saved to the main database at the same time.
number of automatic test and measuring equipments. They
can be used to collect the required data from any peripheral III. PROCESSING UNIT
input devices, such as meters, sensors and etc. via
The processing unit EP1K10TC144-3 from Altera
controlling software [1]. The measured data could be stored
Company is employed for this design. It has 2,880 capacity
in the PC. Their values can be shown numerically whereas
logic elements or about 50,000 gates, 40,960 internal ram bits
their relationship can be displayed graphically as a curve on and 102 input/output ports for connecting to the external
the screen. hardware. It supports the power supply at 3 levels, which are
This paper proposed a design of the data acquisition 5V, 3.3V and 2.5V. The maximum operating frequency is
system using FPGA [2] interfacing to a PC [3]. The system 180 MHz. This design has used VHDL as the language [7, 8]
has capability to receive the digital signals from for writing the code program.
multi-channels sensors with four different ADC protocols. This chip works as the center of the acquisition of the data
from all sensors. Its responsibility is to bridge the signals
II. OVERALL SYSTEM between the ADC inputs to the USB connection, namely, to
The overall system is shown in Figure 1. It presents the send/receive the data with the PC. Figure 2 illustrates the
connection to the four different ADC (analog to digital internal modules within the FPGA chip [6]. These modules
converter) sensors with four different protocols: Parallel, SPI, can be described as below:
I2C and One-Wire. The FPGA collects the individual data A. Parallel Protocol
from all ADC sensors. It processes in the individual
This protocol is the traditional type for most ADCs. It has
protocols. After that it produces a stream of data through the
the advantage of the high speed throughput. This design uses
output USB port [4], which sends these ADC data to the PC.
ADC0820 for the peripheral device. Figure 3 presents the
We have written a specific application program to control
simulation of how the FPGA gets data from this ADC. There
the PC. This program has a function to communicate to the are two main steps in the conversion process:
FPGA so that the PC could prepare itself for the data transfer. The FPGA sends the start signal to activate the ADC
then it will wait for the acknowledge signal.
After finishing the data converting, the ADC will
send the acknowledge signal to the FPGA. Then the
FPGA reads the data from the bus. After that the
Manuscript received December 27, 2009.
S. Thanee is a graduate student in Master Degree in the Faculty of FPGA sends the start signal to activate ADC again for
Engineering at King Mongkuts Institute of Technology, Ladkrabang, getting the data on next read cycle.
Bangkok Thailand. Obviously, this data acquisition is so simple and fast.
S. Somkuarnpanit is now with the Department of Electronics, Faculty of Thus, this protocol should be employed with the high speed
Engineering at King Mongkuts Institute of Technology, Ladkrabang, system.
Bangkok Thailand (e-mail: [email protected]).
K. Saetang is with the Department of Electronics, Faculty of Engineering
at King Mongkuts Institute of Technology, Ladkrabang, Bangkok Thailand
(e-mail: [email protected]).

ISBN: 978-988-18210-4-1 IMECS 2010

ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)
Proceedings of the International MultiConference of Engineers and Computer Scientists 2010 Vol II,
IMECS 2010, March 17 - 19, 2010, Hong Kong

Figure 2 The modules associated in EP1K10TC144-3.

Figure 3 Simulated communication on SPI protocol. Figure 4 The communications on One-wire protocol.

col. In the other hand it has a good point of using only two
B. Serial Peripheral Interface (SPI) Protocol wires in the data communication.
This protocol was developed by Motorola to accomplish
the easy communication, and to reduce the I/O ports. This D. One-Wire Protocol
design utilizes MCP3201 for building the connection with the This protocol employs only one signal line in the data
FPGA. Figure 4 shows the simulation how the FPGA obtains communication. The bus is not active unless all data have not
the data from this ADC. The procedures of this data been transferred. We used the temperature sensor DS1820 as
acquisition are similar to those of the previous protocol. The the input of this One-Wire acquisition data protocol.
FPGA sends the control signal to activate the ADC, and the The protocol separates the data bit by a time slot. It has a
ADC will send the acknowledge signal back. After finishing length between 60-960 s, depending on the user assignment
data conversion, the ADC will send a signal to inform the and the status of the communication between the master and
FPGA to read the data from its output. The difference from the slave devices. There are four statuses in the protocol:
previous protocol is that the FPGA reads the stream of data in Reset: is used to start the communication.
a serial pattern from the MSB to the LSB, instead. Write data 1 to the slave device.
C. Inter-Integrated Circuit (I2C) Protocol Write data 0 to the slave device.
Read data from slave.
The I2C communication is the protocol, which is designed The first step for this protocol is the reset from the FPGA
to reduce the I/O ports. It requires only two signal wires, (the master device). It sends a reset signal to the bus, and
called SCL and SDA. We use PCF8591 as the ADC with the waits for the acknowledge signal from the sensor (slave
I2C for this design. The procedures of this data acquisition are device). After having received the acknowledge signal, the
quite complicated as following steps: FPGA will send the address command to identify the sensor,
The FPGA sends a signal to activate the bus, and to and starts the data conversion.
identify the address of the device. The FPGA waits for the sensors to process the command.
The FPGA defines the write mode, and sends the Then it sends the reset signal and identifies the device address
command to the ADC that it wants to get the data. again. Consequently, it sends the reading command to the
The FPGA defines the read mode, and identify from sensor to read data from the sensor memory one by one from
which channel it want to read. the LSB to the MSB. Finally, it sends the reset signal to the
The FPGA reads the data from I2C bus. bus and waits for the acknowledge signal. To obtain the next
After this point, the data has been finished reading in one data, the FPGA will process the same steps again. Figure 7
cycle time. Figure 5 illustrates the example of the data reading displays the simulation for the procedures of reset,
by this protocol. We can see that one reading cycle of this acknowledge, and writing data of 1100 1100.
protocol takes time more than that of the previous proto-

ISBN: 978-988-18210-4-1 IMECS 2010

ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)
Proceedings of the International MultiConference of Engineers and Computer Scientists 2010 Vol II,
IMECS 2010, March 17 - 19, 2010, Hong Kong

Figure 5 Simulated communication on I2C protocol

Figure 6 Simulated communication on Control Unit and USB Controller

Figure 7 The communications on One-wire protocol.

Figure 8 The FT2232H/FPGA interfacing

E. Control Unit and USB Controller
If there is any data appearing on FIFO buffer, the control driver D2XX.DLL, which allows full accessibility to all the
unit will determine from which channel the data are. chip features. This chip provides an interface between the
Consequently, it will send one-byte data code to the USB port. FPGA and the USB port with 8 bit bidirectional data bus, five
This first data byte informs the application program on PC that control signals and one clock signal. Figure 8 illustrates the
the following data are from which channel. Then it will send a FT2232H/FPGA interfacing.
signal to the USB controller again for sending the data in the Hardware layer: continuously issues the read request in a
FIFO to the USB port byte by byte until the FIFO is empty. "reading worker thread" that will return one or more data, and
This means the end of the data sending procedure in the put the data in a stack from which the data acquisition layer
individual channel. If there are another FIFO channel data can read it.
waiting to be sent out, the FPGA will repeat the same Data acquisition layer: When the data requires some kind
procedures. Figure 6 illustrates the simulation for inter of interpretation, each sensor will have a thread that collects
connection between the control unit and the USB controller. the data, and save them into the PC. When this thread runs, it
moves the data from the queue shared with the hardware layer
IV. THE PC INTERFACING into its own container, and updates the current value shared
The PC interfacing used in this design is the high-speed with the presentation layer.
USB which can transfer the data at the rate of 480 Mbps. The This application is responsible to read data from each
transfer operation is achieved via frames; with the time period protocol and presents them to the user in a style of not only a
of 125 s. Each frame consists of a number of Transactions, numeric value, but also a graphic relationship. Since the
which consists of a number of Packets. These packets include one-wire protocol is used for temperature sensors, it will show
information about the type of the transaction, the address of the data as the discrete number for the temperature. Figure 9
the USB device, and the number of the end points required in displays the operation of application program.
addition to the data and the CRC packets, and a
synchronization packets. V. CONCLUSIONS
The FT2232H chip from FTDI Corp. [5] has been used to From our simulations, we can conclude the advantages
implement this protocol in the design. It is a dual USB to and disadvantages for the individual protocols as shown in
parallel FIFO bi-directional data transfer chip with 4 kilobyte Table1
FIFO Tx and Rx buffer, which handles the entire USB
protocol on the silicon level. The manufacturer provides the

ISBN: 978-988-18210-4-1 IMECS 2010

ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)
Proceedings of the International MultiConference of Engineers and Computer Scientists 2010 Vol II,
IMECS 2010, March 17 - 19, 2010, Hong Kong

Figure 9 Figure 9 The sample displays in the application program

TABLE I. PROPERTY COMPARISON FOR INDIVIDUAL PROTOCOL REFERENCES

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Sample rate (ksp/s) 667 100 11.1 0.00133 Industrial Data Acquisition System, Proc. of Int. Conf. on Inf. and
Sample rate (b/s) 5.34106 1.20106 8.88103 21.28 Comm. Tech, ICTTA 2006, pp. 2589-2594.
Required Wires 12 3 2 1 [2] Jorge Yez, David Quintana, Camilo Quintns, Jos Faria, Juan J.
Acquired solution Easy Easy Complex Complex Rodrguez-Andina,FPGA-based system for the education in data
Power (mW) 75 2 5 7.5 acquisition and signal generation, Proc. of Ind. Elec. Soc. Conf.,
IECON 2005. pp. 2168-2173.
We can see that the parallel protocol is the fastest whereas [3] A. Sagahyroon ,T. Al-khudairi, FPGA Based Acquisition of Sensor
Data Proc. of Int. Conf. on Ind. Tech., ICIT 2004. pp. 1398-1401.
it used the most connection wires. In the other hand, the I2C
[4] M. Popa, M. Marcu, A. S. Popa,A Microcontroller Based Data
or one-wire protocol requires the number of the signal wires Acquisition System with USB Interface, Proc. of Int. Conf. on
for the connection only two and one, respectively, whereas the Elec., Elec. and Comp. Eng., ICEEC 2004 pp. 206-209.
bit rate is much slower than the parallel ADC. We may use [5] FTDI Corporation., www.ftdichip.com, Glasgow, UK,
this for our consideration in using the protocol in most [6] Hamblen J., Furman M., Rapid Prototyping of Digital Systems,
applications. Quartus II Edition, Springer Science Business Media, New York, 2006
Therefore, we could claim that our data acquisition system [7] Douglas L. Perry VHDL Programming By Example, 4 ed.,
is one of the useful solutions for the data acquisition. Having McGraw-Hill, USA, 2002.
contained the input channels with all possible ADC protocols, [8] Pong P. Chu RTL Hardware Design Using VHDL, 1 ed., John Wiley
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Microsoft Visual C++ .NET, 6 ed., Microsoft Press, Washington,
enormous number of the I/O ports in the FPGA, it is feasible 2003.
to add more channels in the future. Eventually, we could
utilize the maximum of 102 I/O ports as the maximum number
for this FPGA.

ISBN: 978-988-18210-4-1 IMECS 2010

ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)