|I||||||III

US005488321A
United States Patent (19) 11 Patent Number: 5,488,321
Johnson 45) Date of Patent: Jan. 30, 1996
54 STATIC HIGH SPEED COMPARATOR 5,077,489 12/1991 Gola ........................................ 307/355
5,223,753 6/1993 Lee .......................................... 307/355
(75) Inventor: Mark G. Johnson, Los Altos, Calif. 5,289,054 2/1994 Lucas ........................................ 327/65
5,362,995 11/1994 Kubo ......................................... 327/65
73) Assignee: Rambus, Inc., Mountain View, Calif. OTHER PUBLICATIONS
21) Appl. No.: 441956 Lance A. Glasser et al., The Design and Analysis of VLSI
Circuits, Chapter 5, Addison-Wesley Publishing Company,
22 Filed: May 16, 1995 Massachusetts, pp. 306–307 (1985).
Related U.S. Application Data Primary Examiner William L. Sikes
Assistant Examiner-Tlep Nguyen
I63) Continuation of Ser. No. 45,324, Apr. 7, 1993, abandoned. Attorney, Agent, or Firm-Blakely, Sokoloff, Taylor & Zaf
al
51) Int. Cl. ........................... H03K 5/22; H03K 5/08
52) U.S. Cl. ....................... 327/66; 327/67; 327/312; 57 ABSTRACT
327/320
(58) Field of Search .................................. 327/63, 64, 65, A comparator circuit comprising a transconductance stage
327/66, 68,375, 563, 72,73, 74, 310, 312, that senses a first and a second input voltage and a transre
314, 319, 320, 323,324,325, 67 sistance stage that senses the current output of the transcon
ductance stage while limiting a voltage swing at the output
(56) References Cited of the transconductance stage. The transresistance stage
generates an output voltage at an output node that indicates
U.S. PATENT DOCUMENTS whether the first or the second input voltage has a greater
magnitude.
4,110,641 8/1978 Payne ...................................... 307/355
4,249,095 2/1981 Hsu ....... 307/355
4,394,587 7/1983 McKenzie ....................... ... 327/66 4 Claims, 7 Drawing Sheets

32
G19 Q20

WSS VVSS

34
U.S. Patent Jan. 30, 1996 Sheet 1 of 7 5,488,321

WDD

WSS

Figure 1 (Prior Art)

of Q13 Q14 to
30

26

32
Q19

34

Figure 2
U.S. Patent Jan. 30, 1996 Sheet 2 of 7 5,488,321
VOD

Q30 Q32

Q19

-~-
34

Figure 3

Figure 4
U.S. Patent Jan. 30, 1996 Sheet 3 of 7 5,488,321
U.S. Patent Jan. 30, 1996 Sheet 4 of 7 5,488,321

IN

TIME
U.S. Patent Jan. 30, 1996 Sheet 5 of 7 5,488,321

C15 O G13 O140 O G16 G63

28 30

'a-ao die 4.'

32
C9 O20

WSS VVSS
U.S. Patent Jan. 30, 1996 Sheet 6 of 7 5,488,321
U.S. Patent Jan. 30, 1996 Sheet 7 of 7 5,488,321

------------------------------
WDD
N
Q15 O G13 G14 to O G16 Q63 soo
28 30

20 22
26 Ga- Q10 Q12 H4
71 72

| 32
GR9 G20

VSS VVSS

34
Q17 G8 O64

v vss VSSW

Figure 9A
 5,488,321
1. 2
STATIC HIGH SPEED COMPARATOR The static comparator 100 senses input voltages at an
input node 10 and an input node 12. If the voltage at the
This is a continuation of application Ser. No. 08/045,324, input node 10 is greater than the voltage at the input node 12,
filed Apr. 7, 1993, now abandoned. a current through the transistor Q1 (I) is greater than a
current through the transistor Q2 (I). The current mirror of
FIELD OF THE INVENTION the static comparator 100 (transistors Q3 and Q4) forces the
current difference (I-I) to an external circuit coupled to an
The present invention pertains to the field of integrated output node 14.
circuit devices. More particularly, this invention relates to a Typically, the output node 14 is coupled to the gates of the
low power consumption high speed static comparator for an 10 input transistors forming a next circuit stage. The input gates
integrated circuit. of the next circuit stage provide a capacitance load to the
static comparator 100. The current supplied by the static
BACKGROUND OF THE INVENTION comparator 100 at the output node 14 (I-12) charges and
discharges the capacitance load provided by the next circuit
A comparator implemented on an integrated circuit can 5 Stage.
perform a variety of useful functions. A comparator senses The static comparator 100 is slow because a relatively
two input voltages and generates an output signal that small bias current as charges and discharges a capacitance
indicates which of the two input voltages has a greater load through a relatively large voltage swing at the output
magnitude. Comparators are commonly employed as sense node 14. The voltage swing at the output node 14 is
amplifiers for static random access memories, dynamic 20
relatively large because the static comparator 100 typically
random access memories, as well as on-chip cache memo has a relatively large gain. The voltage swing at the output
ries for microprocessors. Comparators are also commonly node 14 typically varies between a high level substantially
employed in buffer circuits that couple an integrated circuit equal to the supply voltage VDD, and a low level substan
to an external system. Also, comparators are critical ele tially equal to the voltage at a tail node 18.
ments of analog-to-digital converters and digital-to-analog 25
Converters. The bias current Iasis typically limited to relatively low
A static comparator is a comparator that is always levels to maintain low power consumption for the static
enabled. A static comparator is not timed, controlled, or comparator 100. The propagation delay (At) for the static
activated by clock signals. A static comparator is constantly comparator is relatively large because the voltage swing at
comparing two input voltages. Static comparators may be 30 the output node 14 (Av) is relatively large. The propagation
employed in circuits having no clock signal. Static com delay At is determined by the following equation which
parators may also be employed when the input voltages to governs the charging and discharging of a capacitance load
the comparator change unpredictably, or when the input at the output node 14: I=CXAv/At.
voltages change at times far removed from a clock edge. The propagation delay At of the static comparator 100 can
A high speed static comparator implemented on an inte 35 be reduced by increasing the bias current Is. However, the
grated circuit is typically required to have a short propaga increased bias current Is causes a corresponding increase
tion delay between the input and the output of the compara in power consumption of the static comparator 100. Unfor
tor. A high speed static comparator for an integrated circuit tunately, the increased power consumption in a static com
should also have high gain and low power consumption. parator 100 contributes to overall power consumption in a
Moreover, a high speed static comparator should detect 40 system. In a typical application, an integrated circuit con
differences between two input voltages even when the tains many such static comparators. The excessive power
difference between the input voltages is very slight. consumption of a single static comparator is multiplied
across the integrated circuit, thereby causing unacceptably
The requirements of high gain and low power consump high power consumption for the system.
tion are interrelated by again bandwidth product (GBW). A 45
static comparator implemented on an integrated circuit is SUMMARY AND OBJECTS OF THE
typically modeled as a single pole system having a constant INVENTION
gain bandwidth product. If the gain of the comparator is One object of the present invention is to implement a high
increased, the bandwidth of the comparator must necessarily speed static comparator.
decrease. Moreover, the propagation delay of a comparator 50
is inversely proportional to the bandwidth of the comparator. Another object of the present invention is to implement a
Thus, a static comparator having high gain will necessarily high speed static comparator on an integrated circuit.
have small bandwidth and a large propagation delay Another object of the present invention is to implement a
between the input and the output. high speed static comparator that minimizes power con
FIG. 1 illustrates a typical prior static comparator 100 for 55
sumption.
an integrated circuit. The static comparator 100 is comprised Another object of the present invention is to reduce the
of a differential amplifier and a current mirror load. The power consumption of an integrated circuit that contains one
differential amplifier is comprised of a pair of NMOS or more static comparators.
transistors Q1 and Q2. The current mirror load is comprised A further object of the present invention is to increase the
of a pair of PMOS transistors Q3 and Q4. A bias current 60 bandwidth of a static comparator implemented on an inte
generator 16 generates a bias current (IA) for the transis grated circuit without increasing the bias currents supplied
tors Q1 and Q2. to the static comparator circuit.
In an alternative implementation, the transistors Q1 and Another object of the present invention is to implement a
Q2 are PMOS transistors, and the transistors Q3 and Q4 are high speed static comparator having a transconductance
NMOS transistors. Also, the static comparator 100 could be 65 stage followed by a transresistance stage, wherein the tran
implemented with a differential amplifier comprising a pair sresistance stage clamps the voltage swing at the output of
of NPN bi-polar transistors. the transconductance stage.
 5,488,321
3 4
A further object of the present invention is to implement An NMOS transistor Q10 senses an input voltage at the
a high speed static comparator having a transconductance input node 20 and an NMOS transistor Q12 senses an input
stage followed by a transresistance stage, wherein the voltage at the input node 22. The transistors Q10 and Q12
transconductance stage generates a voltage overshoot at the are configured as a differential input transistor pair.
input to the transresistance stage in order to accelerate The transistor Q10 is coupled to a PMOS transistor Q13,
switching of the transresistance stage. and the transistor Q12 is coupled to a PMOS transistor Q14.
These and other objects of the invention are provided by The transistors Q13 and Q14 are diode load transistors for
a comparator circuit comprising a transconductance stage the differential input pair (transistors Q10 and Q12). The
and a transresistance stage. The transconductance stage gate and the drain of the transistor Q13 are coupled at a node
senses a first input voltage on a first input node and a second 10 28. Similarly, the gate and the drain of the transistor Q14 are
input voltage on a second input node. The transconductance coupled at a node 30.
stage generates a first current into a feedback node. The first The transistors Q13 and Q14 drive a pair of PMOS
current indicates whether the first or the second input transistors Q15 and Q16. The transistors Q15 and Q16 are
voltage has a greater magnitude. coupled to a current mirror circuit comprising a pair of
15 NMOS transistors Q17 and Q18.
The transresistance stage is coupled to the feedback node. An external bias current Is is supplied into a node 26.
The transresistance stage senses the first current while The bias current Is drives a current mirror circuit com
limiting a voltage swing at the feedback node. The transre prising a pair of NMOS transistors Q19 and Q20.
sistance stage generates an output voltage at an output node
that indicates whether the first or the second input voltage The gate to source voltage of the transistor Q13 (Vis)
has a greater magnitude. 20 is substantially equal to the gate to source voltage of the
transistor Q15 (Voss). Also, the gate to source voltage of
Other objects, features and advantages of the present the transistor Q14 (Va) is substantially equal to the gate
invention will be apparent from the accompanying draw to source voltage of the transistor Q16 (Vs). The tran
ings, and from the detailed description that follows below. sistors Q13 through Q16 are fabricated with substantially
25 similar gate width-to-length ratios. As a consequence, a bias
current flowing through the transistors Q15 and Q16 is
BRIEF DESCRIPTION OF THE DRAWINGS substantially equal to a bias current flowing through the
transistors Q13 and Q14.
The present invention is illustrated by way of example The transistors Q15 and Q17 comprise an inverter stage,
and not limitation in the figures of the accompanying 30 and the transistors Q16 and Q18 comprise an inverter stage.
drawings in which like references indicate similar elements, The two inverter stages yield a maximum common mode
and in which: range at the output node 24. As described fully below, a
FIG. 1 illustrates a typical prior static comparator for an subsequent transresistance stage forces the voltage at the
integrated circuit, wherein the static comparator is com output node 24 to approximately WDD12. The maximum
prised of a differential amplifier and a current mirror load; 35
common mode range at the output node 24 yields a relatively
FIG. 2 illustrates a transconductance amplifier that senses large gain for the transconductance amplifier 200 indepen
input voltages at a pair of input nodes, and that generates an dent of the common mode input voltages at the input nodes
20 and 22.
output current at an output node; The transistor Q13 clamps the voltage at the node 28 to a
FIG. 3 illustrates a transconductance amplifier that relatively small voltage swing. Similarly, the transistor Q14
employs a pair of NPN bi-polar transistors to sense input 40 clamps the voltage at the node 30 to a relatively small
voltages at the input nodes; voltage swing, and the transistor Q17 clamps the voltage at
FIG. 4 illustrates a transconductance amplifier that is the the node 34 to a relatively small voltage swing.
complement of the transconductance amplifier of FIG. 2; However, the voltage at the output node 24 is not
FIG. 5 illustrates a transresistance stage that receives an 45
clamped. The output node 24 is pulled up by the current
input current (I) at a feedback node, and that generates an source transistor Q16 and pulled down by the current source
output voltage (Vor) at an output node; transistor Q18. As a consequence, the transconductance
FIG. 6 illustrates the voltage at the feedback node (V) amplifier 200 generates an output current (I) at the
and the voltage at the output node (V) in response to an output node 24 which yields a transconductance gain func
example input current Iv, 50 tion (Iour/VN).
FIG.7 illustrates a high speed static comparator compris FIG. 3 illustrates a transconductance amplifier 220. The
ing a transconductance amplifier coupled to a transresistance transconductance amplifier 220 is similar to the transcon
Stage, ductance amplifier 200 apart from the differential input
FIG. 8 illustrates another high speed static comparator transistors. The transconductance amplifier 220 employs a
that employs a transresistance stage; 55 pair of NPN bi-polar transistors Q30 and Q32 to sense input
FIG. 9A shows another high speed static comparator voltages at the input nodes 20 and 22. The NPN transistors
comprising a transresistance stage with transistors config Q30 and Q32 have higher sensitivity than the NMOS
ured as diodes. transistors Q10 and Q12. As a consequence, the transcon
ductance amplifier 220 responds to smaller input voltage
60 differences when compared with the transconductance
amplifier 200.
DETALED DESCRIPTION
FIG. 4 illustrates a transconductance amplifier 240. The
FIG. 2 illustrates a transconductance amplifier 200. The transconductance amplifier 240 senses input voltages at an
transconductance amplifier 200 senses input voltages at an input node 50 and an input node 52, and generates an output
input node 20 and an input node 22. The transconductance 65 current at an output node 54.
amplifier 200 generates an output current at an output node A PMOS transistor Q40 senses an input voltage at the
24. input node 50 and a PMOS transistor Q42 senses an input
 5,488,321
5 6
voltage at the input node 52. The transistor Q40 is coupled at the feedback node 71 to fall to a low voltage level.
to an NMOS transistor Q43, and the transistor Q42 is Moreover, the transistor Q64 discharges the feedback node
coupled to an NMOS transistor Q44. The transistors Q43 71. When the voltage on the node feedback 71 falls to the
and Q44 are diode load transistors for the differential input switching threshold of the CMOS inverter (transistors Q61
pair (transistors Q40 and Q42). The gate and the drain of the and Q62), the CMOS inverter drives the output node 72 to
transistor Q43 are coupled at a node 58, and the gate and the a high voltage level. The CMOS inverter drives the output
drain of the transistor Q44 are coupled at a node 60. node 72 to a high voltage level after an inverter delay. When
The transistors Q43 and Q44 drive a pair of NMOS the voltage at the output node 72 switches to a high voltage
transistors Q45 and Q46. The transistors Q45 and Q46 are level, the transistor Q64 switches off and the transistor Q63
coupled to a current mirror circuit comprising a pair of 10 switches on. As a consequence, the transistor Q63 sinks the
PMOS transistors Q47 and Q48. An external bias current input currently and clamps the voltage at the feedback node
Iasis supplied into a node 56. The bias current Itas drives 71 from falling to a lower voltage level.
a current mirror circuit comprising a pair of PMOS transis The transresistance stage 300 employs negative feedback.
tors Q49 and Q50. When the input current I falls, the voltage at the feedback
The gate to source voltage of the transistor Q43 (Vis) 15 node 71 falls and causes the voltage at the output node 72 to
is substantially equal to the gate to source voltage of the rise, which causes the voltage at the feedback node 71 to
transistor Q45 (Voss). Also, the gate to source voltage of rise, thereby counteracting the original input current stimu
the transistor Q44 (Visa) is substantially equal to the gate lus. However, the feedback is applied after a delay (corre
to source voltage of the transistor Q46 (Visa). The tran sponding to the CMOS inverter delay) to reduce the phase
sistors Q43 through Q46 are fabricated with substantially 20 margin of the transresistance stage 300 and to generate an
similar gate width-to-length ratios. As a consequence, a bias overshoot at the feedback node 71. The overshoot acceler
current flowing through the transistors Q45 and Q46 is ates the voltage switching at the output node 72.
substantially equal to a bias current flowing through the FIG. 6 illustrates the voltage at the feedback node 71
transistors Q43 and Q44. (V) and the voltage at the output node 72 (V) in
An inverter stage comprising the transistors Q45 and Q47 25 response to an example input current (I).
combined with an inverter stage comprising the transistors Prior to time to the transistor Q64 is clamping the
Q46 and Q48 yield a maximum common mode range at the feedback node 71. At time to the input currently switches
output node 54. As described fully below, a subsequent from positive to negative and the voltage at the feedback
transresistance stage forces the voltage at the output node 54 node 71 begins discharging. At time t, the transistor Q64
to approximately VDD/2. The maximum common mode 30 switches off and the transistor Q63 switches on. The tran
range at the output node 54 yields a relatively large gain for sistor Q63 sinks the negative input current Iw and clamps
the transconductance amplifier 240 independent of the com the voltage at the feedback node 71 from falling to a lower
mon mode input voltages at the input nodes 50 and 52. voltage level.
The transistor Q43 clamps the voltage at the node 58 to a At time t, the input currently switches from negative to
relatively small voltage swing, the transistor Q44 clamps the 35 positive and charges the feedback node 71. At time t, the
voltage at the node 60 to a relatively small voltage swing, transistor Q63 switches off and the transistor Q64 switches
and the transistor Q47 clamps the voltage at the node 64 to on. The transistor Q64 sinks the positive input current Iy
a relatively small voltage swing. The output node 54 is and clamps the voltage at the feedback node 71 from rising
pulled down by the current source transistor Q46 and pulled to a higher voltage level.
up by the current source transistor Q48. As a consequence, 40
The time interval between to and t, and the time interval
the transconductance amplifier 240 generates an output between t and t corresponds to the delay of the CMOS
current at the output node 54, corresponding to a transcon inverter (transistors Q61 and Q62).
ductance gain function. During the switching interval of the input current I, the
FIG. 5 illustrates a transresistance stage 300. The tran 45 feedback node 71 is driven by the sum of the input current
sresistance stage 300 receives an input current 70 (I) and Iy and a current from either the transistor Q63 or the
generates an output voltage (Vor) at an output node 72. transistor Q64. After the delay of the CMOS inverter (tran
The gain function for the transresistance stage 300 (V/ sistors Q61 and Q62), the feedback node 71 is clamped
I) has the units of resistance. when one of the source followers (either the transistor Q63
The transresistance stage 300 is comprised of a CMOS 50 or the transistor Q64) switches off while the other source
inverter and a pair of source followers. The CMOS inverter follower switches on.
is comprised of a PMOS transistor Q61 and an NMOS The voltage excursions at the feedback node 71 are
transistor Q62. The source followers are an NMOS transistor relatively small because the feedback node 71 is clamped.
Q63 and a PMOS transistor Q64. The CMOS inverter (transistors Q61 and Q62) switches
If the input current Iy is positive, the voltage at a 55 relatively quickly because the feedback node 71 is clamped
feedback node 71 begins to rise. When the voltage at the at the switching threshold of the CMOS inverter. The
feedback node 71 reaches the switching threshold of the voltage overshoot at the feedback node 71 causes the CMOS
CMOS inverter (transistors Q61 and Q62), the CMOS inverter to switch even faster.
inverter drives the output node 72 to a low voltage level. FIG. 7 illustrates a high speed static comparator 400. The
However, the CMOS inverter drives the output node 72 to a 60 high speed static comparator 400 comprises a transconduc
low voltage level after an inverter delay. The low voltage tance amplifier coupled to a transresistance stage. The
level at the output node 72 switches on the transistor Q64. transconductance amplifier senses input voltages at the input
As a consequence, the transistor Q64 sinks the input current node 20 and the input node 22, an generates a current at the
I and clamps the feedback node 71 from rising to a higher feedback node 71 into the transresistance stage. The tran
voltage level. 65 sresistance stage senses the current into the feedback node
If the input current Iy is negative, the input current I 71, and generates an output voltage at the output node 72.
discharges the feedback node 71, which causes the voltage The output voltage at the output node 72 indicates which of
 5,488,321
7 8
the input voltages at the input nodes 20 and 22 has a greater a diode load/current mirror circuit coupled between the
magnitude. differential input transistor pair and the feedback
The voltage generated by the transconductance amplifier node, the diode load/current mirror circuit generating
at the feedback node 71 is clamped by the transresistance the first current according to a difference between a
stage. The combination of the transconductor amplifier and current flowing through the first input transistor and
the transresistance stage yields a combination circuit having a current flowing through the second input transistor,
an extremely fast response. The transresistance stage has a wherein the diode load/current mirror circuit com
small phase margin causing an overshoot to accelerate the prises
switching speed at the output node 72. a first load transistor having a drain and a gate
In another embodiment of the high speed static compara 10 coupled to a drain of the first input transistor at a
tor 400, the drain of the transistor Q63 is coupled to the first node, the first load transistor having a source
coupled to a Supply voltage,
output node 72 rather than the VDD node (see FIG. 9A). a second load transistor having a drain and a gate
Also, the drain of the transistor Q64 is coupled to the output coupled to a drain of the second input transistor at
node 72 rather than the VSS node (see FIG. 9A). Such a a second node, the second load transistor having a
configuration increases the amount of capacitance that the 15 source coupled to the supply voltage;
CMOS inverter (transistors Q61 and Q62) drives, and a first inverter transistor having a gate coupled to the
decreases the power consumption of the high speed static first node, a drain coupled to a third node, and a
comparator 400. In such a configuration, the transistors Q63 source coupled to the supply voltage;
and Q64 may be referred to as shunt diodes. a second inverter transistor having a gate coupled to
In another embodiment of the high speed static compara 20 the second node, a drain coupled to the feedback
tor 400, the voltage at the feedback node 71 need only be node, and a source coupled to the supply voltage;
clamped in one direction. For example, the transistor Q63 a first current mirror transistor having a drain and a
clamps the feedback node 71 and the transistor Q64 is gate coupled to the third node, and a source
omitted. Alternatively, the transistor Q64 clamps the feed coupled to a common node;
back node 71 and the transistor Q63 is omitted. 25 a second current mirror transistor having a gate
FIG. 8 illustrates a high speed static comparator 500. The coupled to the third node, a drain coupled to the
feedback node, and a source coupled to the com
high speed static comparator 500 comprises a transconduc mon node,
tance amplifier coupled to a transresistance stage. The a transresistance stage coupled to the feedback node, the
transconductance amplifier senses input voltages at an input 30 transresistance stage sensing the first current while
node 80 and an input node 82, an generates a current at the providing negative feedback that limits a voltage swing
feedback node 71 into the transresistance stage. The tran at the feedback node, the transresistance stage gener
Sresistance stage senses the current into the feedback node ating an output voltage at an output node that indicates
71, and generates an output voltage at the output node 72 whether the first or the second input voltage has a
that indicates which of the input voltages at the input node 35
greater magnitude.
80 and 82 has a greater magnitude. 2. A comparator circuit, comprising:
The voltage generated by the transconductance amplifier a transconductance stage for sensing a first input voltage
at the feedback node 71 is clamped by the transresistance on a first input node and a second input voltage on a
stage. The gate width-to-length ratios of the CMOS inverter second input node, the transconductance stage gener
transistors Q61 and Q62 are adjusted to set the CMOS 40 ating a first current into a feedback node, the first
inverter switching threshold near the center of the common current indicating whether the first or the second input
mode output range of the differential amplifier (transistors voltage has a greater magnitude, the transconductance
Q1 and Q2). stage further comprising
In the foregoing specification, the invention has been a differential input transistor pair comprising a first
described with reference to specific exemplary embodiments input transistor for sensing the first input voltage and
thereof. It will, however, be evident that various modifica
45 a second input transistor for sensing the second input
voltage, the first and second input transistors being
tions and changes may be made thereto without departing bi-polar transistors, the differential input transistor
from the broader spirit and scope of the invention as set forth pair biased by a bias current circuit:
in the appended claims. The specification and drawings are, a diode load/current mirror circuit coupled between the
accordingly, to be regarded in an illustrative rather than a 50 differential input transistor pair and the feedback
restrictive sense. node, the diode load/current mirror circuit generating
What is claimed is: the first current according to a difference between a
1. A comparator circuit, comprising: current flowing through the first input transistor and
a transconductance stage for sensing a first input voltage a current flowing through the second input transistor,
on a first input node and a second input voltage on a 55 wherein the diode load/current mirror circuit com
second input node, the transconductance stage gener prises
ating a first current into a feedback node, the first a first load transistor having a drain and a gate
current indicating whether the first or the second input coupled to a collector of the first input transistor at
voltage has a greater magnitude, the transconductance a first node, the first load transistor having a source
stage further comprising 60 coupled to a supply voltage;
a differential input transistor pair comprising a first a second load transistor having a drain and a gate
input transistor for sensing the first input voltage and coupled to a collector of the second input transis
a second input transistor for sensing the second input tor at a second node, the second load transistor
voltage, the first and second input transistors being having a source coupled to the supply voltage;
metal oxide semiconductor field effect transistors, 65 a first inverter transistor having a gate coupled to the
the differential input transistor pair biased by a bias first node, a drain coupled to a third node, and a
current circuit: source coupled to the supply voltage;
 5,488,321
10
a second inverter transistor having a gate coupled to ating an output voltage at an output node that indicates
the second node, a drain coupled to the feedback whether the first or the second input voltage has a
node, and a source coupled to the supply voltage; greater magnitude, wherein the transresistance stage
a first current mirror transistor having a drain and a comprises:
gate coupled to the third node, and a source 5 an inverter circuit coupled between the feedback node
coupled to a common node, and the output node,
a second current mirror transistor having a gate a first transistor configured to function as a first diode
coupled to the third node, a drain coupled to the coupled between the feedback node and the output
feedback node, and a source coupled to the com- node, the first transistor configured to function as the
mon node, O first diode having a source coupled to the feedback
a transresistance stage coupled to the feedback node, the node and having a gate and a drain each coupled to
transresistance stage sensing the first current while the output node;
providing negative feedback that limits a voltage swing a second transistor configured to function as a second
at the feedback node, the transresistance stage gener- diode coupled between the feedback node and the
ating an output voltage at an output node that indicates 15 output node, the second transistor configured to
whether the first or the second input voltage has a function as the second diode having a source coupled
greater magnitude. to the feedback node and having a gate and a drain
3. A comparator circuit, comprising: each coupled to the output node.
a transconductance stage for sensing a first input voltage 4. The comparator circuit of claim3, wherein the inverter
on a first input node and a second input voltage on a 20 circuit comprises:
second input node, the transconductance stage gener- first transistor coupled between the supply voltage and the
ating a first current into a feedback node, the first output node, the first transistor having a gate coupled to
current indicating whether the first or the second input the feedback node,
voltage has a greater magnitude; second transistor coupled between the common node and
a transresistance stage coupled to the feedback node, the the output node, the second transistor having a gate
transresistance stage sensing the first current while coupled to the feedback node.
providing negative feedback that limits a voltage swing
at the feedback node, the transresistance stage gener- :k k k k cK