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    Ec3352 Set4

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    menakadeviece
    This document outlines the practical end semester examination for the third semester of a B.E/B.Tech program in Digital System Design. It lists 20 examination questions related to digital logic design and implementation. Students will be assessed on their ability to design, analyze and implement digital circuits including half/full adders, decoders, multiplexers, comparators, and various types of registers and counters using logic gates or integrated circuits. The exam is worth a total of 100 marks and will evaluate students on their understanding, circuit design/drawing, calculation abilities, and performance during a viva voce interview.

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    Ec3352 Set4

    Uploaded by

    menakadeviece
    122 views2 pages
    This document outlines the practical end semester examination for the third semester of a B.E/B.Tech program in Digital System Design. It lists 20 examination questions related to digital logic design and implementation. Students will be assessed on their ability to design, analyze and implement digital circuits including half/full adders, decoders, multiplexers, comparators, and various types of registers and counters using logic gates or integrated circuits. The exam is worth a total of 100 marks and will evaluate students on their understanding, circuit design/drawing, calculation abilities, and performance during a viva voce interview.

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    EC3352 SET4

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    This document outlines the practical end semester examination for the third semester of a B.E/B.Tech program in Digital System Design. It lists 20 examination questions related to digital logic design and implementation. Students will be assessed on their ability to design, analyze and implement digital circuits including half/full adders, decoders, multiplexers, comparators, and various types of registers and counters using logic gates or integrated circuits. The exam is worth a total of 100 marks and will evaluate students on their understanding, circuit design/drawing, calculation abilities, and performance during a viva voce interview.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    122 views2 pages

    Ec3352 Set4

    Uploaded by

    menakadeviece
    This document outlines the practical end semester examination for the third semester of a B.E/B.Tech program in Digital System Design. It lists 20 examination questions related to digital logic design and implementation. Students will be assessed on their ability to design, analyze and implement digital circuits including half/full adders, decoders, multiplexers, comparators, and various types of registers and counters using logic gates or integrated circuits. The exam is worth a total of 100 marks and will evaluate students on their understanding, circuit design/drawing, calculation abilities, and performance during a viva voce interview.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    of 2

    B.E / B.Tech.

    PRACTICAL END SEMESTER EXAMINATIONS, NOVEMBER/DECEMBER 2022

    Third Semester

    EC3352 – DIGITAL SYSTEM DESIGN

    (Regulations 2021)

    Time: 3 Hours Answer any one Question Max. Marks 100

    Aim/Principle/Apparatus Tabulation/Circuit/ Calculation Viva-Voce Record Total


    required/Procedure Program/Drawing & Results
    20 30 30 10 10 100

    1. Design and implement half adder and full subtractor with its truth table. (100)

    (i) Design and implement Gray to Binary code conversion. (50)


    2.
    (ii) Verify the truth table of half subtractor using logic gates. (50)

    (i) Design and implement BCD to excess 3 code conversion. (50)


    3.
    (ii) Verify the truth table of Full subtractor using logic gates. (50)

    (i) Design and construct a full adder using suitable logic gates and verify the output. (50)
    4.
    (ii) Design and implement a multiplexer, Verify its operation using logic gates. (50)

    5. Design and construct 2 bit magnitude comparator using logic gates.

    6. Implement the Serial In Serial Out and Parallel In Serial Out shift register.

    7. (i) Design and implement two to four-line decoder using basic gates. (50)

    (ii)Design and construct the counter count the sequence 0, 1, 2, 4, 6, 0…… (50)

    8. (i) Design and Implement a combinational circuit for data selector using basic gates. (50)

    (ii) ) Design and implement a combinational circuit for 1 X 4 demux using basic gates. (50)

    Page 1 of 2
    9. (i) Design and implement Encoder using basic gates. (50)

    (ii) Implement 4-bit adder/ subtractor using IC 7483. (50)

    10. Design a circuit for 5 bit magnitude comparator using logic gates and verify its output.

    11. Design and construct an asynchronous 4-bit BCD up counter using JK flip flop ICs.

    12. Design and implement 3 bit synchronous up/down counter.

    13. (i) Design and implement Decoder using Integrated Circuits. (50)

    (ii) Design and implement 2 bit adder. (50)

    14. Design and implement MOD7 counter using JK flip flop ICs.

    15. Design the 3-bit asynchronous up counter and implement it.

    16. Design and construct a full adder using suitable logic gates and verify the output

    17. Implement the Serial In Parallel Out and Parallel In Parallel Out shift register.

    18. (i) Implement 4-bit binary adder/subtractor.

    (ii) Design and implement BCD adder .

    19. Design and construct a synchronous 3-bit binary down counter using JK flip flop

    20. Design a circuit which converts Excess 3 to BCD code and implement using basic gates.

    INTERNAL EXAMINER EXTERNAL EXAMINER

    Page 2 of 2

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