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    Ece 18ec734 M2S5 SM

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    1GG20EC426 Yuvaraj M
    The document discusses memory architectures used in digital signal processors (DSPs). It describes the Von Neumann and Harvard architectures, explaining that Harvard architecture uses separate memories for instructions and data to increase processing speed. It also discusses using dual data memories to fetch both operands in one clock cycle. On-chip memories are described as faster but requiring a tradeoff between speed and hardware cost. Common DSP addressing modes like immediate, register, direct, and indirect addressing are also summarized.

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    Ece 18ec734 M2S5 SM

    Uploaded by

    1GG20EC426 Yuvaraj M
    132 views7 pages
    The document discusses memory architectures used in digital signal processors (DSPs). It describes the Von Neumann and Harvard architectures, explaining that Harvard architecture uses separate memories for instructions and data to increase processing speed. It also discusses using dual data memories to fetch both operands in one clock cycle. On-chip memories are described as faster but requiring a tradeoff between speed and hardware cost. Common DSP addressing modes like immediate, register, direct, and indirect addressing are also summarized.

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    ECE notes

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    ECE_18EC734_M2S5_SM

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    The document discusses memory architectures used in digital signal processors (DSPs). It describes the Von Neumann and Harvard architectures, explaining that Harvard architecture uses separate memories for instructions and data to increase processing speed. It also discusses using dual data memories to fetch both operands in one clock cycle. On-chip memories are described as faster but requiring a tradeoff between speed and hardware cost. Common DSP addressing modes like immediate, register, direct, and indirect addressing are also summarized.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    132 views7 pages

    Ece 18ec734 M2S5 SM

    Uploaded by

    1GG20EC426 Yuvaraj M
    The document discusses memory architectures used in digital signal processors (DSPs). It describes the Von Neumann and Harvard architectures, explaining that Harvard architecture uses separate memories for instructions and data to increase processing speed. It also discusses using dual data memories to fetch both operands in one clock cycle. On-chip memories are described as faster but requiring a tradeoff between speed and hardware cost. Common DSP addressing modes like immediate, register, direct, and indirect addressing are also summarized.

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    of 7

    MODULE-2_Session5

    2.1 Bus Architecture and Memory


    Conventional microprocessors use Von Neumann architecture for memory
    management wherein the same memory is used to store both the program
    and data (Fig 2.9). Although this architecture is simple, it takes more
    number of processor cycles for the execution of a single instruction as the
    same bus is used for both data and program.

    Fig 2.9 Von Neumann Architecture

    In order to increase the speed of operation, separate memories were used to


    store program and data and a separate set of data and address buses have
    been given to both memories, the architecture called as Harvard
    Architecture. It is as shown in figure 2.10
    Although the usage of separate memories for data and the instruction
    speeds up the processing, it will not completely solve the problem. As
    many of the DSP instructions require more than one operand, use of a
    single data memory leads to the fetch the operands one after the other, thus
    increasing the delay of processing. This problem can be overcome by using
    two separate data memories for storing operands separately, thus in a single
    clock cycle both the operands can be fetched together (Figure 2.11).
    Fig 2.11 Harvard Architecture with Dual Data Memory

    Although the above architecture improves the speed of operation, it


    requires more hardware and interconnections, thus increasing the cost and
    complexity of the system. Therefore there should be a trade off between the
    cost and speed while selecting memory architecture for a DSP.
    2.1.1 On-chip Memories
    In order to have a faster execution of the DSP functions, it is desirable to
    have some memory located on chip. As dedicated buses are used to access
    the memory, on chip memories are faster. Speed and size are the two key
    parameters to be considered with respect to the on-chip memories.
    Speed
    On-chip memories should match the speeds of the ALU operations in
    order to maintain the single cycle instruction execution of the DSP.
    Size
    In a given area of the DSP chip, it is desirable to implement as many DSP
    functions as possible. Thus the area occupied by the on-chip memory
    should be minimum so that there will be a scope for implementing more
    number of DSP functions on- chip.

    2.1.2 Organization of On-chip Memories


    Ideally whole memory required for the implementation of any DSP
    algorithm has to reside on- chip so that the whole processing can be
    completed in a single execution cycle. Although it looks as a better
    solution, it consumes more space on chip, reducing the scope for
    implementing any functional block on-chip, which in turn reduces the
    speed of execution. Hence some other alternatives have to be
    DSP ALGORITHM & ARCHITECTURE MODULE 2

    2.2 Data Addressing Capabilities

    Data accessing capability of a programmable DSP device is configured by


    means of its addressing modes. The summary of the addressing modes
    used in DSP is as shown in the table below.

    2.2.1 Immediate Addressing Mode


    In this addressing mode, data is included in the instruction itself.

    2.2.2 Register Addressing Mode


    In this mode, one of the registers will be holding the data
    and the register has to be specified in the instruction.

    2.2.3 Direct Addressing Mode


    In this addressing mode, instruction holds the memory location of the
    operand.

    2.2.4 Indirect Addressing Mode


    In this addressing mode, the operand is accessed using a
    pointer. A pointer is generally a register, which holds the address
    of the location where the operands resides. Indirect addressing
    mode can be extended to inculcate automatic increment or
    decrement capabilities, which has lead to the following addressing
    modes.
    Recommended Questions:

    1. Explain implementation of 8- tap FIR filter, (i) pipelined


    using MAC units and (ii)
    2. What is the role of a shifter in DSP? Explain the
    implementation of 4-bit shift right barrel shifter, with
    a diagram.
    3. Identify the addressing modes of the operands in each
    of the following instructions & their operations
    i) ADD B ii) ADD #1234h iii) ADD 5678h iv) ADD
    +*addreg
    4. Draw the schematic diagram of the saturation logic and explain the
    same.
    5. Explain how the circular addressing mode and bit reversal addressing
    mode are implemented in
    a DSP.
    6. Explain the purpose of program sequencer.
    7. Give the structure of a 4X4 Braun multiplier,
    Explain its concept. What modification is required
    to carry out multiplication of signed numbers?
    Comment on the speed of the multiplier.
    8. Explain guard bits in a MAC unit of DSP. Consider a
    MAC unit whose inputs are 24-bit numbers. How
    many guard bits should be provided if 512 products
    have to be added in the accumulator to prevent
    overflow condition? What is the overall size of the
    accumulator required?
    9. With a neat block diagram explain ALU of DSP system.
    10. Explain circular buffer addressing mode ii) Parallelism iii) Guard
    bits.
    11. The 256 unsigned numbers, 16 bit each are to be
    summed up in a processor. How many guard bits are
    needed to prevent overflow.
    12. How will you implement an 8X8 multiplier using 4X4 multipliers as
    the building blocks.
    13. Describe the basic features that should be provided in the
    DSP architecture to be used to implement the Nth order
    FIR filter, where x(n) denotes the input sample, y(n) the
    output sample and h(i) denotes ith filter
    coefficient.(Dec.09-Jan.10, 8m)
    14. Explain the issues to be considered in designing and
    implementing a DSP system, with the help of a neat block
    diagram. (May/June10 , 6m)
    15. Briefly explain the major features of programmable DSPs.
    (May/June10, 8m)
    16. Explain the operation used in DSP to increase the
    sampling rate. The sequence x(n)=[0,2,4,6,8] is
    interpolated using interpolation sequence bk =[1/2,1,1/2]
    and the interpolation factor is 2.find the interpolated
    sequence y(m). (May/June10, 8m)
    17. Explain with the help of mathematical equations how
    signed numbers can be multiplied. (Dec.10-Jan.11, 8m)
    18. The sequence x(n) = [3,2,-2,0,7].It is interpolated using
    interpolation sequence bk=[0.5,1,0.5] and the interpolation
    factor of 2. Find the interpolated sequence y(m).(Dec.10-
    Jan.11, 6m)
    19. Why signal sampling is required? Explain the sampling process.
    (Dec.12, 5m)
    20. Define decimation and interpolation process.
    Explain them using block diagrams and
    equations. (Dec.12, 6m).

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