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    4 Bit Incrementer Decrementer

    Uploaded by

    Tabassum Reza
    This document describes the design of a 4-bit incrementer/decrementer circuit. It includes the following key points: 1. The design is implemented in multiple tasks, starting with Verilog modeling and simulation, followed by gate-level schematic and transistor-level circuit design. 2. Layout is created for individual components as well as the top-level design, with placement of the 4-bit circuit and I/O pads. 3. Simulation and analysis is performed on the extracted layout, showing the circuit operates as intended up to 100MHz clock frequency with low power consumption.

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    © All Rights Reserved
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    4 Bit Incrementer Decrementer

    Uploaded by

    Tabassum Reza
    43 views47 pages
    This document describes the design of a 4-bit incrementer/decrementer circuit. It includes the following key points: 1. The design is implemented in multiple tasks, starting with Verilog modeling and simulation, followed by gate-level schematic and transistor-level circuit design. 2. Layout is created for individual components as well as the top-level design, with placement of the 4-bit circuit and I/O pads. 3. Simulation and analysis is performed on the extracted layout, showing the circuit operates as intended up to 100MHz clock frequency with low power consumption.

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    This document describes the design of a 4-bit incrementer/decrementer circuit. It includes the following key points: 1. The design is implemented in multiple tasks, starting with Verilog modeling and simulation, followed by gate-level schematic and transistor-level circuit design. 2. Layout is created for individual components as well as the top-level design, with placement of the 4-bit circuit and I/O pads. 3. Simulation and analysis is performed on the extracted layout, showing the circuit operates as intended up to 100MHz clock frequency with low power consumption.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    43 views47 pages

    4 Bit Incrementer Decrementer

    Uploaded by

    Tabassum Reza
    This document describes the design of a 4-bit incrementer/decrementer circuit. It includes the following key points: 1. The design is implemented in multiple tasks, starting with Verilog modeling and simulation, followed by gate-level schematic and transistor-level circuit design. 2. Layout is created for individual components as well as the top-level design, with placement of the 4-bit circuit and I/O pads. 3. Simulation and analysis is performed on the extracted layout, showing the circuit operates as intended up to 100MHz clock frequency with low power consumption.

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    © All Rights Reserved
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    You are on page 1of 47

    4 BIT

    INCREMENTER/
    DECREMENTER
    Submitted to

    Dr. A.B.M. Harun-Ur-Rashid Gobinda Saha


    Professor Lecturer
    Dept. of EEE, BUET Dept. of EEE, BUET
    OBJECTIVE

     Design a 4 bit Incrementer / Decrementer

     Modular design

     Layout with I/O pads

     Clearing of DRC and LVS

     Generating GDS file


    TASK 1

    Design Specifications:
     4 bit Incrementer / Decrementer

     Synchronous +ve edge clock operation

     Synchronous Reset capability

     Enable option (Cin)

     Sequential addition/subtraction logic

     Cascading option (Cout)


    TASK 1
    VERILOG CODE
    module incdec (clk, reset, incdec, cin, Q, c3);
    input clk, reset, incdec, cin;
    output reg [3:0] Q;
    output reg c3;

    always @(posedge clk)


    if (~reset)
    {c3, Q[3:0]} <= 5'b0 ;
    else if (incdec)
    {c3, Q[3:0]} <= {c3, Q[3:0]} + cin ;
    else
    {c3, Q[3:0]} <= {c3, Q[3:0]} - cin ;

    endmodule
    TASK 1
    VERILOG CODE - TESTBENCH
    module stimulus;
    reg clk, reset, incdec, cin;
    wire cout;
    wire [3:0] Q;
    incdec in1(clk, reset, incdec, cin, Q, cout);

    initial
    begin
    clk = 1'b0;
    forever begin #5 clk = ~clk; end
    end
    initial
    TASK 1
    VERILOG CODE - TESTBENCH
    begin
    $shm_open("shm.db",1); // Opens a waveform database
    $shm_probe("AS"); // Saves all signals to database
    #300 $finish;
    #400 $shm_close(); // Closes the waveform database
    end

    initial // Stimulate the Input Signals


    begin
    cin<=1;
    end
    TASK 1
    VERILOG CODE - TESTBENCH
    initial
    begin
    #0 incdec<=1; #100 incdec<=0;
    end

    initial
    begin
    #0 reset=1; #30 reset=0; #40 reset=1; #250 reset=0;
    #280 reset=1;
    end
    endmodule //stimulus
    TASK 1
    WAVEFORM: FUNCTIONAL VERIFICATION
    TASK 1
    WAVEFORM: FUNCTIONAL VERIFICATION
    TASK 1
    WAVEFORM: ZOOMED
    TASK 2
    GATE LEVEL SCHEMATIC DESIGN
    Incrementer Logic

    Qn  Ci  Qn1
    Ci 1  Ci .Qn1

    Decrementer Logic

    Ci 1  Ci .Qn1
    TASK 2
    GATE LEVEL SCHEMATIC DESIGN

    Pucknell’s
    Design
    TASK 2
    GATE LEVEL SCHEMATIC DESIGN

    Modified
    Design
    TASK 3
    TRANSISTOR LEVEL DESIGN
    Inverter
    Schematic
    TASK 3
    TRANSISTOR LEVEL DESIGN
    Inverter Inverter
    Layout Symbol
    TASK 3
    TRANSISTOR LEVEL DESIGN
    Inverter Simulation Result (Schematic)
    TASK 3
    TRANSISTOR LEVEL DESIGN
    2 Input NAND
    Schematic
    TASK 3
    TRANSISTOR LEVEL DESIGN
    2 Input NAND 2 Input NAND
    Layout Symbol
    TASK 3
    TRANSISTOR LEVEL DESIGN
    2 Input NAND Simulation Result (Schematic)
    TASK 3
    TRANSISTOR LEVEL DESIGN
    2 Input XOR
    Schematic
    TASK 3
    TRANSISTOR LEVEL DESIGN
    2 Input XOR Layout 2 Input XOR
    Symbol
    TASK 3
    TRANSISTOR LEVEL DESIGN
    2 Input XOR Simulation Result (Schematic)
    TASK 3
    TRANSISTOR LEVEL DESIGN
    D Flip Flop Schematic
    TASK 3
    TRANSISTOR LEVEL DESIGN
    D Flip Flop Layout
    TASK 3
    TRANSISTOR LEVEL DESIGN

    D Flip Flop
    Symbol
    TASK 3
    TRANSISTOR LEVEL DESIGN
    D Flip Flop Simulation Result (Schematic)
    TASK 4
    TOP LEVEL LAYOUT PLACEMENT
    1 bit Incrementer/Decrementer Schematic
    TASK 4
    TOP LEVEL LAYOUT PLACEMENT
    1 bit Incrementer/Decrementer Layout
    TASK 4
    TOP LEVEL LAYOUT PLACEMENT

    1 bit
    Incrementer/Decrementer
    Symbol
    TASK 4
    TOP LEVEL LAYOUT PLACEMENT
    4 bit Incrementer/Decrementer Schematic
    TASK 4
    TOP LEVEL LAYOUT PLACEMENT
    4 bit Incrementer/Decrementer Layout
    TASK 4
    TOP LEVEL LAYOUT PLACEMENT

    4 bit
    Incrementer/Decrementer
    Symbol
    TASK 4
    TOP LEVEL LAYOUT PLACEMENT
    4 bit Incrementer/Decrementer Simulation Result
    (Schematic)
    TASK 5
    COMPLETE CHIP LAYOUT
    ESD Protection: Schematic
    TASK 5
    COMPLETE CHIP LAYOUT
     ESD Protection: Layout
    TASK 5
    COMPLETE CHIP LAYOUT
     Bondpad Layout:
    - - 70u x 70u dimension
    - - 3 metal layers and 2 via layers
    - - No slotting
    TASK 5
    COMPLETE CHIP LAYOUT
     Schematic of Final chip with IO pad:
    TASK 5
    COMPLETE CHIP LAYOUT
     Layout of final chip with IO pad:
    TASK 5
    COMPLETE CHIP LAYOUT
     Pin diagram of the final chip:
    TASK 5
    COMPLETE CHIP LAYOUT
     Av_extracted view of the final chip
    TASK 5
    COMPLETE CHIP LAYOUT
     Simulation from av_extracted view: (50 MHz
    clock)
    TASK 5
    COMPLETE CHIP LAYOUT
     Circuit inventory:
    TASK 5
    COMPLETE CHIP LAYOUT
     Delay, rise time and fall time when clock
    frequency is 50 MHz:

    Clock to Q Rise time (ns) Fall time (ns)


    propagation delay
    (ns)

    For Q0 1.4634 3.2 2.53


    TASK 5
    COMPLETE CHIP LAYOUT
     Dependency of power dissipation on clock
    frequency:
    Clock Frequency Average power dissipation Maximum instantaneous power
    (µW) dissipation (µW)

    50 MHz 44.41 959.5

    100 MHz 82.75 1.08033


    TASK 5
    COMPLETE CHIP LAYOUT
     Final Chip Performance
    - - Chip Dimension without I/O Pad:
    - 36.56 µm ×31.09 µm
    - - Final Chip Dimension: 660 µm ×660 µm
    - Average Power Consumption: 44.41 µW
    (at 50 MHz)
    - Frequency Support: up 100 MHz
    SUBMITTED BY:

    Anik Saha (0906001)


    Anupam Golder (0906004)
    THANK YOU

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