Module 3
Module 3
Module 3
Module 3
SYLLABUS:
Delay: Introduction, Transient Response, RC Delay Model, Linear Delay Model, Logical
Efforts of Paths (4.1 to 4.5 of TEXT 2, except subsections 4.3.7, 4.4.5, 4.4.6, 4.5.5 and
4.5.6).
Combinational Circuit Design: Introduction, Circuit families (9.1 to 9.2 of TEXT 2,
except subsection 9.2.4).
Table of Contents
3.1. Introduction: ........................................................................................................................ 2
3.2. Transient Response ............................................................................................................. 3
3.3. RC delay model: ................................................................................................................. 4
3.4. Elmore Delay ...................................................................................................................... 7
3.5. Layout Dependence of Capacitance.................................................................................. 10
3.6. Linear Delay Model .......................................................................................................... 10
3.6.1. Logical Effort ........................................................................................................................... 11
3.6.2. Parasitic Delay ......................................................................................................................... 12
3.6.3. Delay in Multistage Logic Networks........................................................................................ 13
3.7. Circuit Families ................................................................................................................. 15
3.7.1. Static CMOS............................................................................................................................. 15
3.7.1.1. Bubble Pushing: ............................................................................................................... 15
3.7.1.2. Compound Gates: ............................................................................................................ 16
3.7.1.3. Input Ordering Delay Effect: ............................................................................................ 18
3.7.1.4. Asymmetric Gates: ........................................................................................................... 18
3.7.1.5. Skewed Gates: .................................................................................................................. 19
3.7.1.6. P/N Ratios: ....................................................................................................................... 20
3.7.2. Ratioed Circuits ....................................................................................................................... 20
3.7.2.1. Pseudo-Nmos ................................................................................................................... 20
3.7.2.2. Cascode Voltage Switch Logic .......................................................................................... 22
3.7.2.3. Pass-Transistor Circuits .................................................................................................... 22
3.7.2.4. CMOS with Transmission Gates ....................................................................................... 23
3.7.2.5. Complementary Pass Transistor Logic (CPL) .................................................................... 24
3.8. Question Bank ................................................................................................................... 24
“CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo Kang &
T-1.
Yosuf Leblebici, Third Edition, Tata McGraw-Hill.
Delay
3.1. Introduction:
The two most common metrics for a good chip are speed and power. Delay and power are
influenced as much by the wires as by the transistors. Hence simple models are developed
that assist in understanding system performance better.
Definitions
• Propagation delay time, tpd = maximum time from the input crossing 50% to the
output crossing 50%
• Contamination delay time, tcd = minimum time from the input crossing 50% to the
output crossing 50%
• Rise time, tr = time for a waveform to rise from 20% to 80% of its steady-state value
• Fall time, tf = time for a waveform to fall from 80% to 20% of its steady-state value
• Edge rate, trf = (tr + tf )/2
A timing analyzer computes the arrival times, i.e., the latest time at which each node in a
block of logic will switch. The user must specify the arrival time of inputs and the time data
is required at the outputs. The arrival time ai at internal node i depends on the propagation
delay of the gate driving i and the arrival times of the inputs to the gate:
The slack is the difference between the required and arrival times. Positive slack means that
the circuit meets timing. Negative slack means that the circuit is not fast enough.
Arrival time example
Consider finding the step response of an inverter. Typically, the circuit consists of the gate
capacitance of the load along with the diffusion
capacitance of the driver’s own transistors.
Fig 3.1 shows the equivalent circuit diagram in which all
the capacitances are lumped into a single Cout.
Before the voltage step is applied, A = 0. N1 is OFF, P1
is ON, and B = VDD.
After the step, A = 1. N1 turns ON and P1 turns OFF and B drops toward 0.
The rate of change of the voltage VB at node B depends on the output capacitance and on the
current through N1:
Approximating a step input with finite rise/fall time to a ramp we get three phases, as shown
in Table 3.1. When A starts to rise, N1 remains OFF and B remains at VDD. When A reaches
Vtn, N1 turns ON. It fights P1 and starts to gradually pull B down toward an intermediate
value predicted by the DC circuit response. When A gets close enough to VDD, P1 turns OFF
and B falls to 0 unopposed. Thus, we can write the differential equations for VB in each
phase:
• The size of the unit transistor conventionally refers to a transistor with minimum length
and minimum contacted diffusion width.
• A transistor of k times unit width has resistance R/k because it delivers k times as much
current.
Gate and Diffusion Capacitance
Each transistor also has gate and diffusion capacitance. We define C to be the gate
capacitance of a unit transistor. A transistor of k times unit width has capacitance kC.
Diffusion capacitance depends on the size of the source/drain region
Equivalent RC Circuits
Fig 3.2 shows equivalent RC circuit models for
nMOS and pMOS transistors of width k with
contacted diffusion on both source and drain. The
pMOS transistor has approximately twice the
resistance of the nMOS transistor because holes
have lower mobility than electrons
Fig 3.3(a) shows unit inverters composed of a nMOS transistor of unit size and a pMOS
transistor of twice unit width to achieve equal rise and fall resistance. Fig 3.3(b) gives an
equivalent circuit, showing the first inverter driving the second inverter’s gate. If the input A
rises, the nMOS transistor will be ON and the pMOS OFF. Fig 3.3(c) illustrates this case with
the switches removed. The capacitors shorted between two constant supplies are also
removed because they are not charged or discharged. The total capacitance on the output Y is
6C.
Problem: Sketch a 3-input NAND gate with transistor widths chosen to achieve effective rise
and fall resistance equal to that of a unit inverter (R). Annotate the gate with its gate and
diffusion capacitances. Assume all diffusion nodes are contacted. Then sketch equivalent
circuits for the falling output transition and for
the worst-case rising output transition.
terminals shorted together so they are irrelevant to circuit operation. Fig 3.4(c) redraws the
gate with these capacitances deleted and the remaining capacitances lumped to ground. Fig
3.4(d) shows the equivalent circuit for the falling output transition. The output pulls down
through the three series nMOS transistors. Fig 3.4(e) shows the equivalent circuit for the
rising output transition. In the worst case, the upper two inputs are 1 and the bottom one falls
to 0. The output pulls up through a single pMOS transistor. The upper two nMOS transistors
are still on, so the diffusion capacitance between the series nMOS transistors must also be
discharged.
3.4. Elmore Delay
The Elmore delay model estimates the delay from a source switching to one of the leaf nodes
changing as the sum over each node i of the capacitance Ci on the node, multiplied by the
effective resistance Ris on the shared path from the source to the node and the leaf.
Example 1: Compute the Elmore delay for Vout in the 2nd order RC system from Fig 3.5.
SOLUTION: The circuit has a source and two nodes.
At node n1, the capacitance is C1 and the resistance to the
source is R1.
At node Vout, the capacitance is C2 and the resistance to the
source is (R1 + R2). Hence, the Elmore delay is
tpd = R1C1 + (R1 + R2)C2.
Example 2: Estimate tpd for a unit inverter driving m identical unit inverters.
SOLUTION: Fig 3.6 shows an equivalent circuit for the falling
transition. Each load inverter presents 3C units of gate capacitance,
for a total of 3mC.
The output node also sees a capacitance of 3C from the drain
diffusions of the driving inverter. The parasitic capacitance is
independent of the load that the inverter is driving. Hence, the total
capacitance is (3 + 3m)C. The resistance is R, so the Elmore delay is
tpd = (3 + 3m)RC.
The equivalent circuit for the rising transition gives the same results.
Example 5: Estimate tpdf and tpdr for the 3-input NAND gate of Fig 3.4(a) if the output is
loaded with h identical NAND gates.
SOLUTION: Each NAND gate load presents 5
units of capacitance on a given input. Figure 3.9(a)
shows the equivalent circuit including the load for
the falling transition.
Node n1 has capacitance 3C and resistance of R/3
to ground. Node n2 has capacitance 3C and
resistance (R/3 + R/3) to ground. Node Y has
capacitance (9 + 5h)C and resistance (R/3 + R/3 +
R/3) to ground. The Elmore delay for the falling output is the sum of these RC products,
tpdf = (3C)(R/3) + (3C)(R/3 + R/3) + ((9 + 5h)C)(R/3+ R/3 + R/3) = (12 + 5h)RC.
Fig 3.9(b) shows the equivalent circuit for the rising transition. In the worst case, the two
inner inputs are 1 and the outer input falls. Y is pulled up to VDD through a single pMOS
transistor. The ON nMOS transistors contribute parasitic capacitance that slows the transiton.
Node Y has capacitance (9 + 5h)C and resistance R to the VDD supply. Node n2 has
capacitance 3C. The relevant resistance is only R, not (R + R/3), because the output is being
charged only through R. This is what is meant by the resistance on the shared path from the
source (VDD) to the node (n2) and the leaf (Y). Similarly, node n1 has capacitance 3C and
resistance R. Hence, the Elmore delay for the rising output is,
tpdr = (15 + 5h)RC
Example 6: Estimate the contamination delays tcdf and tcdr for the 3-input NAND gate from
Fig 3.4 (a) if the output is loaded with h identical NAND gates.
SOLUTION: The contamination delay is the
fastest that the gate might switch. For the
falling transition, the best case is that the
bottom two nMOS transistors are already ON
when the top one turns ON. In such a case,
the diffusion capacitances on n1 and n2 have
already been discharged and do not contribute
to the delay. Fig 3.10(a) shows the equivalent
circuit and the delay is
tcdf = (9 + 5h)RC.
For the rising transition, the best case is that all three pMOS transistors turn on
simultaneously. The nMOS transistors turn OFF, so n1 and n2 are not connected to the output
and do not contribute to delay. The parallel transistors deliver three times as much current, as
shown in Fig 3.10(b), so the delay is
tcdr = (3 + (5/3)h)RC.
p is the parasitic delay inherent to the gate when no load is attached. f is the effort delay or
stage effort that depends on the complexity and fanout of the gate:
f = gh
The complexity is represented by the logical effort, g. An inverter is defined to have a logical
effort of 1. More complex gates have greater logical efforts, indicating that they take longer
to drive a given fanout. For example, the logical effort of the 3-input NAND gate is 5/3. A
gate driving h identical copies of itself is said to have a fanout or electrical effort of h. If the
load does not contain identical copies of the gate, the electrical effort can be computed as
where Cout is the capacitance of the external load being driven and Cin is the input
capacitance of the gate.
3.6.1. Logical Effort
Logical effort of a gate is defined as the ratio of the input capacitance of the gate to the input
capacitance of an inverter that can deliver the same output current. Equivalently, logical
effort indicates how much worse a gate is at producing
output current as compared to an inverter, given that each
input of the gate may only present as much input
capacitance as the inverter.
Fig 3.13 shows inverter, 3-input NAND, and 3-input NOR
gates with transistor widths chosen to achieve unit
resistance, assuming pMOS transistors have twice the
resistance of nMOS transistors. The inverter presents three
units of input capacitance. The NAND presents five units
of capacitance on each input, so the logical effort is 5/3.
Similarly, the NOR presents seven units of capacitance, so
the logical effort is 7/3.
Table 3.2 lists the logical effort of common gates. The
effort tends to increase with the number of inputs. NAND
gates are better than NOR gates because the series
transistors are nMOS rather than pMOS. Exclusive-OR
gates are particularly costly and have different logical
efforts for different inputs. Multiplexers built from ganged
tristates, have a logical effort of 2 independent of the number of inputs. However, the
parasitic delay does increase with multiplexer size.
Example: Use the linear delay model to estimate the delay of the fanout-of-4 (FO4) inverter
from Example 4.6. Assume the inverter is constructed in a 65 nm process with τ = 3 ps.
SOLUTION: The logical effort of the inverter is g = 1, by definition. The electrical effort is 4
because the load is four gates of equal size. The parasitic delay of an inverter is pinv = 1. The
total delay is d = gh + p = 1 × 4 + 1 = 5 in normalized terms, or tpd = 15 ps in absolute terms.
The path electrical effort H can be given as the ratio of the output capacitance the path must
drive divided by the input capacitance presented by the path.
The path branching effort B is the product of the branching efforts between stages.
The path effort F is defined as the product of the logical, electrical, and branching efforts of
the path.
The path delay D is the sum of the delays of each stage. It can also be written as the sum of
the path effort delay DF and path parasitic delay P:
The path delay is minimized when each stage bears the same effort. If a path has N stages and
each bears the same effort, that effort must be
Thus, the minimum possible delay of an N-stage path with path effort F and path parasitic
delay P is
Example: Estimate the minimum delay of the path from A to B in Fig 3.15 and choose
transistor sizes to achieve this delay. The
initial NAND2 gate may present a load of
8𝞴 of transistor width on the input and the
output load is equivalent to 45𝞴 of transistor
width.
4:1 P/N ratio. If the total input capacitance is 15, the pMOS width must be 12 and the nMOS
width must be 3 to achieve that ratio.
To check that our delay was achieved.
The NAND2 gate delay is d1 = g1h1 + p1 = (4/3) × (10 + 10 + 10)/8 + 2 = 7.
These relations are illustrated graphically in Fig 3.1. A NAND gate is equivalent to an OR of
inverted inputs. A NOR gate is equivalent to an AND of inverted inputs. Switching between
these representations often called bubble pushing.
Fig 3.2 Bubble pushing to convert ANDs and ORs to NANDs and NORs
3.7.1.2. Compound Gates: Static CMOS also efficiently handles compound gates computing
various inverting combinations of AND/OR functions in a
single stage. The function F = AB + CD can be computed
with an AND-OR-INVERT-22 (AOI22) gate and an
inverter, as shown in Fig 3.3.
In general, logical effort of compound gates can be different for different inputs. Fig 3.4
shows how logical efforts can be estimated for the AOI21, AOI22, and a more complex
compound AOI gate. The transistor widths are chosen to give the same drive as a unit
inverter. The logical effort of each input is the ratio of the input capacitance of that input to
the input capacitance of the inverter. The parasitic delay is the ratio of the total diffusion
capacitance on the output node to that of the inverter.
P = 2 + 2 = 4. P = 12/3 + 1 = 5.
𝑓̂ = 𝐹 𝑁 = 3.0 𝑓̂ = 𝐹 𝑁 = 3.2
3.7.1.3. Input Ordering Delay Effect: The logical effort and parasitic delay of different gate
inputs are often different.
Fig 3.5 shows a 2-input NAND gate annotated with
diffusion parasitics. Consider the falling output transition
occurring when one input held a stable 1 value and the
other rises from 0 to 1.
If input B rises last, node x will initially be at VDD – Vt = VDD because it was pulled up
through the nMOS transistor on input A. The Elmore delay is (R/2)(2C) + R(6C) = 7RC
On the other hand, if input A rises last, node x will initially be at 0 V because it was
discharged through the nMOS transistor on input B. No charge must be delivered to node x,
so the Elmore delay is simply R(6C) = 6RC
In general, we define the outer input to be the input closer to the supply rail (e.g., B) and the
inner input to be the input closer to the output (e.g., A). The parasitic delay is smallest when
the inner input switches last because the intermediate nodes have already been discharged.
3.7.1.4. Asymmetric Gates: When one input is less critical than another, the symmetric gates
can be made asymmetric to favor the late input at the expense of the early one. In a series
network, this involves connecting the early input to the outer transistor and making the
transistor wider so that it offers less series resistance when the critical input arrives. In a
parallel network, the early input is connected to a narrower transistor to reduce the parasitic
capacitance.
For example, consider the path in Fig 3.6(a). When reset is
inactive (i.e. reset =0) the path acts as a buffer between A
and Y. When reset is asserted, the path forces the output
low. If reset occurs only under exceptional circumstances,
the circuit can be made asymmetric as shown in Fig 3.6(b).
The pulldown resistance is R/4 + R/(4/3) = R, i.e., the
resistance of a unit inverter. However, the capacitance on
input A is only 10/3(i.e., 4/3 +2), so the logical effort is
10/9. This is better than 4/3, which is normally associated
with a NAND gate. The improvement in logical effort of input A comes at the cost of much
higher effort on the reset input. The pMOS transistor on the reset input is also shrunk to
reduce its diffusion capacitance and parasitic delay at the expense of slower response to reset.
3.7.1.5. Skewed Gates: In some cases, one input transition is more important than the other.
HI-skew gates favor the rising output transition and LO-skew gates favor the falling output
transition. This favoring can be done by decreasing the size of the noncritical transistor. The
logical efforts for the rising (up) and falling (down) transitions are called gu and gd,
respectively, and are the ratio of the input capacitance of the skewed gate to the input
capacitance of an unskewed inverter with equal drive for that transition.
Fig 3.8 shows the catalogs of HI-skew and LO-skew gates with a skew factor of two. Refer
Fig 3.9 for calculation of LO-skew inverter.
3.7.1.6. P/N Ratios: In general, the best P/N ratio for logic gates (i.e., the ratio of pMOS to
nMOS transistor width) giving lowest average delay is the square root of the ratio that gives
equal rise and fall delays. For processes with a mobility ratio of μn/μp = 2, the best ratios are
shown in Fig 3.10.
3.7.2.1. Pseudo-Nmos
Fig 3.11(a) shows a pseudo-nMOS inverter. The static load is built from a single pMOS
transistor that has its gate grounded so it is always ON. The DC transfer characteristics are
derived by finding Vout for which Idsn = |Idsp| for a given Vin, as shown in Fig 3.11(b–c).
The PMOS transistor produces 1/3rd of the current of the reference inverter, and the NMOS
transistor stacks produce 4/3rd of the current of the reference inverter.
For falling transitions, the output current is pull-down current minus the pull-up,
i.e., 4/3 - 1/3 = 1.
For rising transitions, the output current is just the pull-up current, 1/3.
The inverter and NOR gate have an input capacitance of 4/3. The falling logical effort is the
input capacitance divided by that of an inverter with the same output current.
The rising logical effort is 3 times greater, because the current produced on a rising transition
is only 1/3rd that of a falling transition.
For example, the logical effort for a falling transition of the pseudo-nMOS inverter is the
ratio of its input capacitance (4/3) to that of a unit complementary CMOS inverter (3), i.e.,
4/9. gu is three times as great because the current is 1/3 as much.
The parasitic delay is also found by counting output capacitance and comparing it to an
inverter with equal current. For example, the pseudo-nMOS NOR has 10/3 units of diffusion
capacitance as compared to 3 for a unit-sized complementary CMOS inverter, so its parasitic
delay pulling down is 10/9. The pullup current is 1/3 as great, so the parasitic delay pulling
up is 10/3.
9. Explain Cascode Voltage Switch Logic (CVSL). Also realize two input AND/NAND
using CVSL.
10. Explain linear delay model. Compare the logical efforts of the following gates with
the help of schematic diagrams:
i) 2-input NAND gate
ii) 3-input4 NOR gate
11. Explain : i) pseudo nMOS ii) ganged CMOS with necessary circuit examples.
12. Estimate tpdf and tpdr of a 3-input NAND gate if the output is loaded with h identical
gates. Use Elmore delay model.
13. Explain skewed gates with an example.