®

RT5768A

3A, 1MHz, Synchronous Step-Down Converter

General Description Features
The RT5768A is a high efficiency synchronous, step-down  High Efficiency : Up to 95%
DC/DC converter. It's input voltage range from 2.7V to 5.5V  Low RDS(ON) Internal Switches : 69mΩ/49mΩ at VIN
that provides an adjustable regulated output voltage from = 5V
0.6V to VIN while delivering up to 3A of output current.  Fixed Frequency : 1MHz
The internal synchronous low on resistance power  No Schottky Diode Required
switches increase efficiency and eliminate the need for  Internal Compensation
an external Schottky diode. The switching frequency is  0.6V Reference Allows Low Output Voltage
fixed internally at 1MHz. The 100% duty cycle provides  Low Dropout Operation : 100% Duty Cycle
low dropout operation, hence extending battery life in  OCP, UVP, OVP, OTP
portable systems. Current mode operation with internal  RoHS Compliant and Halogen Free
compensation allows the transient response to be
optimized over a wide range of loads and output capacitors. Applications
The RT5768A is available in WDFN-10L 3x3 package.
 Portable Instruments
 Battery Powered Equipment
Ordering Information  Notebook Computers
RT5768A
 Distrib uted Power Systems
Package Type  IP Phones
QW : WDFN-10L 3x3 (W-Type)
 Digital Cameras
Lead Plating System
G : Green (Halogen Free and Pb Free)
Pin Configurations
Note : (TOP VIEW)
Richtek products are :
LX 1 10 PVIN
 RoHS compliant and compatible with the current require- LX 2 9 PVIN
GND

ments of IPC/JEDEC J-STD-020. LX 3 8 SVIN

PGOOD 4 7 NC
 Suitable for use in SnPb or Pb-free soldering processes. EN 5 11 6 FB

WDFN-10L 3x3

Marking Information
8T= : Product Code

8T=YM YMDNN : Date Code

DNN

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1
RT5768A
Typical Application Circuit
RT5768A L
4 PGOOD 1, 2, 3
PGOOD LX VOUT
R1 COUT
100k
9, 10 CFF
VIN PVIN RFB1
CIN 8 SVIN 6
10µF FB
C1 RFB2
1µF
Chip Enable 5
EN
GND
11 (Exposed Pad)

Table 1. Recommended Component Selection

VOUT (V) RFB1 (k) RFB2 (k) CFF (pF) L (H) COUT (F)
3.3 229.5 51 22 2 22 x 2
2.5 161.5 51 22 2 22 x 2
1.8 102 51 22 1.5 22 x 2
1.5 76.5 51 22 1.5 22 x 2
1.2 51 51 22 1.5 22 x 2
1.0 34 51 22 1.5 22 x 2

Functional Pin Description

Pin No. Pin Name Pin Function
1, 2, 3 LX Switch Node. Connect this pin to the inductor.
Power Good Indicator. This pin is an open drain logic output that is pulled
4 PGOOD to ground when the output voltage is less than 90% of the target output
voltage. Hysteresis = 5%.
5 EN Enable Control. Pull high to turn on. Do not float.
Feedback Pin. This pin receives the feedback voltage from a resistive
6 FB
voltage divider connected across the output.
7 NC No Internal Connection.
8 SVIN Signal Input Pin. Decouple this pin to GND with at least 1F ceramic cap.
Power Input Pin. Decouple this pin to GND with at least 4.7F ceramic
9, 10 PVIN
cap.
Ground. The exposed pad must be soldered to a large PCB and
11 (Exposed Pad) GND
connected to GND for maximum power dissipation.

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 RT5768A
Function Block Diagram
EN

EN
ISEN PVIN

PGOOD PGOOD Slope

OSC
Com

VREF
0.6V

Output OC
EA Limit
FB Clamp

Int-SS Driver
LX
0.72V Control
OV Logic
0.54V
PGOOD NISEN
0.4V Zero Current
UV
POR

OTP

SVIN

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RT5768A
Absolute Maximum Ratings (Note 1)
 Supply Input Voltage, PVIN, SVIN --------------------------------------------------------------------------------- −0.3V to 6.5V
 LX Pin
DC ------------------------------------------------------------------------------------------------------------------------- (VIN + 0.3V) to 6.8V
< 20ns ------------------------------------------------------------------------------------------------------------------- −2.5V to 9V
 Other I/O Pin Voltage ------------------------------------------------------------------------------------------------- −0.3V to 6.5V

 Power Dissipation, PD @ TA = 25°C

WDFN-10L 3x3 --------------------------------------------------------------------------------------------------------- 1.429W

 Package Thermal Resistance (Note 2)

WDFN-10L 3x3, θJA --------------------------------------------------------------------------------------------------- 70°C/W

WDFN-10L 3x3, θJC --------------------------------------------------------------------------------------------------- 8.2°C/W
 Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C

 Junction Temperature ------------------------------------------------------------------------------------------------- 150°C

 Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C

 ESD Susceptibility (Note 3)

HBM (Human Body Model) ------------------------------------------------------------------------------------------ 2kV

MM (Machine Model) ------------------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 4)

 Supply Input Voltage, PVIN, SVIN --------------------------------------------------------------------------------- 2.7V to 5.5V
 Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C
 Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics
(VIN = 3.3V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Feedback Reference Voltage VREF 0.594 0.6 0.606 V
Feedback Leakage Current IFB -- 0.1 0.4 A
Active , VFB = 0.7V, Not
-- 110 140
DC Bias Current Switching A
Shutdown -- -- 1
VIN = 2.7V to 5.5V
Output Voltage Line Regulation -- 0.3 -- %/V
IOUT = 0A
Output Voltage Load Regulation IOUT = 0A to 3A 1 -- 1 %
Switch Leakage Current -- -- 1 A
Switching Frequency 0.8 1 1.2 MHz
Switch On Resistance, High RDS(ON)_P VIN = 5V -- 69 -- m
Switch On Resistance, Low RDS(ON)_N VIN = 5V -- 49 -- m
P-MOSFET Current Limit ILIM 4 -- -- A

Under Voltage Lockout VIN Rising 2.2 2.4 2.6

VUVLO V
Threshold VIN Falling 2 2.2 2.4

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 RT5768A
Parameter Symbol Test Conditions Min Typ Max Unit
EN Input Logic-High VIH 1.6 -- --
V
Threshold Voltage Logic-Low VIL -- -- 0.4
EN Pull Low Resistance -- 500 -- k
Over Temperature Protection TSD -- 150 -- C
Over Temperature Protection
-- 20 -- C
Hysteresis
Soft-Start Time tSS 500 -- -- s
VOUT Discharge Resistance -- 100 -- 
VOUT Over Voltage Protection
115 120 130 %
(Latch-Off, Delay Time = 10s)
VOUT Under Voltage Lock Out
57 66 75 %
(Latch-Off)
Measured FB, With Respect to
Power Good 85 90 -- %
VREF
Power Good Hysteresis -- 5 -- %

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

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RT5768A
Typical Operating Characteristics
Efficiency vs. Load Current Efficiency vs. Load Current
100 100
90 VIN = 4.2V 90
VIN = 5V VIN = 3.3V
80 80 VIN = 5V
70 70
Efficiency (%)

Efficiency (%)
60 60
50 50
40 40
30 30
20 20
10 10
VOUT = 3.3V VOUT = 1.8V
0 0
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
Load Current (A) Load Current (A)

Efficiency vs. Load Current Output Voltage vs. Output Current

100 1.820
90
1.815
80 VIN = 3.3V
VIN = 5V 1.810
Output Voltage (V)

70
Efficiency (%)

60 1.805

50 1.800 VIN = 5V
40
1.795
VIN = 3.3V
30
1.790
20
10 1.785
VOUT = 1.05V VOUT = 1.8V
0 1.780
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3

Load Current (A) Output Current (A)

Current Limit vs. Input Voltage Current Limit vs. Temperature

7.0 7.0

6.5 6.5
VIN = 5V
6.0 6.0
Current Limit (A)

Current Limit (A)

5.5 5.5 VIN = 3.3V

5.0 5.0

4.5 4.5

4.0 4.0

3.5 3.5
VOUT = 1.05V VOUT = 1.05V
3.0 3.0
2.5 3 3.5 4 4.5 5 5.5 -50 -25 0 25 50 75 100 125
Input Voltage (V) Temperature (°C)

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 RT5768A

RDS(ON) vs. Temperature Load Transient Response

90
85
80 VOUT
P-MOSFET (50mV/Div)
75
Ω)

70
RDS(ON) (mΩ

65
60
55
50 IOUT
(2A/Div)
45 N-MOSFET
40 VIN = 5V VIN = 5V, VOUT = 1.8V, IOUT = 0.5A to 3A
35
-50 -25 0 25 50 75 100 125 Time (50μs/Div)
Temperature (°C)

Load Transient Response Switching

VOUT VOUT
(50mV/Div) (5mV/Div)

VLX
(5V/Div)

IOUT
(2A/Div)
ILX
(1A/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 1.5A to 3A VIN = 5V, VOUT = 1.8V, IOUT = 1.5A

Time (50μs/Div) Time (500ns/Div)

Switching Over Voltage Protection

VOUT
(5mV/Div)

VLX VOUT
(5V/Div) (1V/Div)

ILX VLX
(2A/Div) (2V/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 3A VIN = 5V, VOUT = 1.8V, IOUT = 1A

Time (500ns/Div) Time (10μs/Div)

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RT5768A

Under Voltage Protection Over Current Protection

VIN = 5V, VOUT = 1.8V VIN = 5V, VOUT = 1.8V

VOUT
(1V/Div)
VOUT
(1V/Div) ILX
(5A/Div)

VLX VLX
(2V/Div) (2V/Div)

Time (5μs/Div) Time (2.5μs/Div)

Power On from VIN Power Off from VIN

VIN VIN
(2V/Div) (2V/Div)

VOUT VOUT
(1V/Div) (1V/Div)

ILX ILX
(2A/Div) (2A/Div)
VOUT = 1.8V, IOUT = 3A VOUT = 1.8V, IOUT = 3A

Time (2.5ms/Div) Time (2.5ms/Div)

Power On from EN Power Off from EN

VEN VEN
(5V/Div) (5V/Div)

VOUT VOUT
(1V/Div) (1V/Div)

ILX ILX
(2A/Div) (2A/Div)
VIN = 5V, VOUT = 1.8V, IOUT = 3A VIN = 5V, VOUT = 1.8V, IOUT = 3A

Time (200μs/Div) Time (40μs/Div)

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 RT5768A
Application Information
The RT5768A is a single-phase buck converter. It provides UVLO Protection
single feedback loop, current mode control with fast The RT5768A has input Under Voltage Lockout protection
transient response. An internal 0.6V reference allows the (UVLO). If the input voltage exceeds the UVLO rising
output voltage to be precisely regulated for low output threshold voltage (2.4V typ.), the converter resets and
voltage applications. A fixed switching frequency (1MHz) prepares the PWM for operation. If the input voltage falls
oscillator and internal compensation are integrated to below the UVLO falling threshold voltage during normal
minimize external component count. Protection features operation, the device will stop switching. The UVLO rising
include over current protection, under voltage protection, and falling threshold voltage has a hysteresis to prevent
over voltage protection and over temperature protection. noise-caused reset.

Output Voltage Setting Inductor Selection

Connect a resistive voltage divider at the FB between VOUT The switching frequency (on-time) and operating point (%
and GND to adjust the output voltage. The output voltage ripple or LIR) determine the inductor value as shown below:
is set according to the following equation :
VOUT   VIN  VOUT 
L=
VOUT = VREF   1 + FB1 
R fSW  LIR  ILOAD(MAX)  VIN
 R FB2 
where VREF is 0.6V (typ.). where LIR is the ratio of the peak-to-peak ripple current to
VOUT the average inductor current.

RFB1 Find a low loss inductor having the lowest possible DC

FB resistance that fits in the allotted dimensions. Ferrite cores
RFB2 are often the best choice, although powdered iron is
GND inexpensive and can work well at 200kHz. The core must
be large enough not to saturate at the peak inductor current
Figure 1. Setting VOUT with a Voltage Divider (IPEAK) :
Chip Enable and Disable
IPEAK = ILOAD(MAX) +  LIR  ILOAD(MAX) 
The EN pin allows for power sequencing between the  2 
controller bias voltage and another voltage rail. The The calculation above serves as a general reference. To
RT5768A remains in shutdown if the EN pin is lower than further improve transient response, the output inductor
400mV. When the EN pin rises above the VEN trip point, can be further reduced. This relation should be considered
the RT5768A begins a new initialization and soft-start cycle. along with the selection of the output capacitor.

Internal Soft-Start Input Capacitor Selection

The RT5768A provides an internal soft-start function to High quality ceramic input decoupling capacitor, such as
prevent large inrush current and output voltage overshoot X5R or X7R, with values greater than 20μF are
when the converter starts up. The soft-start (SS) recommended for the input capacitor. The X5R and X7R
automatically begins once the chip is enabled. During soft- ceramic capacitors are usually selected for power regulator
start, the internal soft-start capacitor becomes charged capacitors because the dielectric material has less
and generates a linear ramping up voltage across the capacitance variation and more temperature stability.
capacitor. This voltage clamps the voltage at the FB pin,
Voltage rating and current rating are the key parameters
causing PWM pulse width to increase slowly and in turn
when selecting an input capacitor. Generally, selecting an
reduce the output surge current. The internal 0.6V
input capacitor with voltage rating 1.5 times greater than
reference takes over the loop control once the internal
the maximum input voltage is a conservatively safe design.
ramping-up voltage becomes higher than 0.6V.
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RT5768A
The input capacitor is used to supply the input RMS during load transient. However, the ceramic capacitor can
current, which can be approximately calculated using the only provide low capacitance value. Therefore, use a mixed
following equation : combination of electrolytic capacitor and ceramic capacitor
VOUT  VOUT  to obtain better transient performance.
IIN_RMS = ILOAD   1
VIN  VIN 
Power Good Output (PGOOD)
The next step is selecting a proper capacitor for RMS
current rating. One good design is using more than one PGOOD is an open-drain type output and requires a pull-
capacitor with low equivalent series resistance (ESR) in up resistor. PGOOD is actively held low in soft-start,
parallel to form a capacitor bank. standby, and shutdown. It is released when the output
voltage rises above 90% of nominal regulation point. The
The input capacitance value determines the input ripple
PGOOD signal goes low if the output is turned off or is
voltage of the regulator. The input voltage ripple can be
10% below its nominal regulation point.
approximately calculated using the following equation :
IOUT(MAX)  0.25 Under Voltage Protection (UVP)
VIN =
CIN  fSW
The output voltage can be continuously monitored for under
For example, if IOUT_MAX = 3A, CIN = 20μF, fSW = 1MHz, voltage. When under voltage protection is enabled, both
the input voltage ripple will be 37.5mV. UGATE and LGATE gate drivers will be forced low if the
output is less than 66% of its set voltage threshold. The
Output Capacitor Selection
UVP will be ignored for at least 3ms (typ.) after start up or
The output capacitor and the inductor form a low pass a rising edge on the EN threshold. Toggle EN threshold or
filter in the buck topology. In steady state condition, the cycle VIN to reset the UVP fault latch and restart the
ripple current flowing into/out of the capacitor results in controller.
ripple voltage. The output voltage ripple (VP-P) can be
calculated by the following equation : Over Voltage Protection (OVP)

VP_P = LIR  ILOAD(MAX)   ESR + 1  The RT5768A is latched once OVP is triggered and can
 8  COUT  fSW  only be released by toggling EN threshold or cycling VIN.
When load transient occurs, the output capacitor supplies There is a 10μs delay built into the over voltage protection
the load current before the controller can respond. circuit to prevent false transition.
Therefore, the ESR will dominate the output voltage sag
Over Current Protection (OCP)
during load transient. The output voltage undershoot (VSAG)
can be calculated by the following equation : The RT5768A provides over current protection by detecting
VSAG = ILOAD  ESR high side MOSFET peak inductor current. If the sensed
peak inductor current is over the current limit threshold
For a given output voltage sag specification, the ESR value
(4A typ.), the OCP will be triggered. When OCP is tripped,
can be determined.
the RT5768A will keep the over current threshold level
Another parameter that has influence on the output voltage until the over current condition is removed.
sag is the equivalent series inductance (ESL). The rapid
change in load current results in di/dt during transient. Thermal Shutdown (OTP)
Therefore, the ESL contributes to part of the voltage sag. The device implements an internal thermal shutdown
Using a capacitor with low ESL can obtain better transient function when the junction temperature exceeds 150°C.
performance. Generally, using several capacitors The thermal shutdown forces the device to stop switching
connected in parallel can have better transient performance when the junction temperature exceeds the thermal
than using a single capacitor for the same total ESR. shutdown threshold. Once the die temperature decreases
Unlike the electrolytic capacitor, the ceramic capacitor has below the hysteresis of 20°C, the device reinstates the
relatively low ESR and can reduce the voltage deviation power up sequence.
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 RT5768A
Thermal Considerations Layout Considerations
For continuous operation, do not exceed absolute Layout is very important in high frequency switching
maximum junction temperature. The maximum power converter design. The PCB can radiate excessive noise
dissipation depends on the thermal resistance of the IC and contribute to converter instability with improper layout.
package, PCB layout, rate of surrounding airflow, and Certain points must be considered before starting a layout
difference between junction and ambient temperature. The using the RT5768A.
maximum power dissipation can be calculated by the Make the traces of the main current paths as short and
following formula : wide as possible.
PD(MAX) = (TJ(MAX) − TA) / θJA Put the input capacitor as close as possible to the device

where TJ(MAX) is the maximum junction temperature, TA is pins (VIN and GND).
the ambient temperature, and θJA is the junction to ambient LX node encounters high frequency voltage swings so it
thermal resistance. should be kept in a small area. Keep sensitive
For recommended operating condition specifications, the components away from the LX node to prevent stray
maximum junction temperature is 125°C. The junction to capacitive noise pick-up.
ambient thermal resistance, θJA, is layout dependent. For Ensure all feedback network connections are short and
WDFN-10L 3x3 packages, the thermal resistance, θJA, is direct. Place the feedback network as close to the chip
70°C/W on a standard JEDEC 51-7 four-layer thermal test as possible.
board. The maximum power dissipation at TA = 25°C can
The GND pin and Exposed Pad should be connected to
be calculated by the following formulas :
a strong ground plane for heat sinking and noise
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for protection.
WDFN-10L 3x3 package
An example of PCB layout guide is shown in Figure 3.
The maximum power dissipation depends on the operating for reference.
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curves in Figure 2 allow the
The output capacitor must Input capacitor must be placed
designer to see the effect of rising ambient temperature be placed near the IC. as close to the IC as possible.
on the maximum power dissipation. COUT
GND
CIN1
2.0 LX 1 10 PVIN
Four-Layer PCB
Maximum Power Dissipation (W)1

VOUT LX 2 9 PVIN CIN2

GND

RPGOOD LX 3 8 SVIN
1.6 PGOOD 4 7 NC R2
VIN EN 5 11 6 FB
VOUT

REN R1
1.2 LX should be connected to
The voltage divider must
inductor by wide and short trace.
be connected as close to
Keep sensitive components
the device as possible.
0.8 away from this trace.

Figure 3. PCB Layout Guide

0.4

0.0
0 25 50 75 100 125
Ambient Temperature (°C)

Figure 2. Derating Curve of Maximum Power Dissipation

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RT5768A
Outline Dimension

D2
D

E E2

SEE DETAIL A
1

e
b 2 1 2 1
A
A3
A1 DETAIL A
Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 2.950 3.050 0.116 0.120
D2 2.300 2.650 0.091 0.104
E 2.950 3.050 0.116 0.120
E2 1.500 1.750 0.059 0.069
e 0.500 0.020
L 0.350 0.450 0.014 0.018

W-Type 10L DFN 3x3 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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