Wei Tung
Wei Tung
Wei Tung
Wei Tung
Strength of Andes RISC-V CPU IPs
RISC-V + ACE
Compact + High Performance + Flexible + Low Power
Cache-Coherent
A25MP AX25MP
27-Series: 45-Series:
1-4 Cores MemBoost MemBoost
Vector Ext. Dual Issue.
JTAG 25-series
25-series
25-series Inst.
Debug Xport PLIC
Memory
Debug BBIIIU
B UU Data
master
master slave
slave
Module master slave Memory
AXI64*2/AHB64,32 AHB64,32
AXI/AHB IP
GPIO APB IP
DMA
I2C AXI/AHB
AE350 PWM/PIT APB Bridge Bus Masters Customer’s or
RTC Bus Matrix Partner’s IP’s
Bus Slaves
Platform SPI
UART
WDT Sys. Mgmt Unit
Taking RISC-V® Mainstream 12
Speedup with DSP ISA on 25-Series
• Real world speed up, using DSP extension
64 bit
PNET (90% of Face detection) 7.57x
x 2x 4x 6x 8x 10x 12x
Taking RISC-V® Mainstream 13
DSP Support
DSP ISA
The basis of RISC-V P-extension draft that Andes contributed.
300 instructions derived and evolved from real use cases (over decades)
Support 32 bits and 64 bits
Support saturation and rounding
Cover SIMD, partial SIMD, bit manipulation and etc.
DSP intrinsic functions
Users can use as C-like functions without bothering to program in assembly
DSP library
>200 functions in 8 categories (basic, complex, controller, filtering, matrix, statistics,
transform, utils)
Some DSP instructions are auto-generated by compiler to facilitate
development
Compatible with CMSIS-DSP library API
By including an API wrapper header file
Microcontroller Software Interface Standard (CMSIS)
Taking RISC-V® Mainstream 14
DSP Library Comparison with CPU A
RV32-P: Speedups over CPU A (with 3% larger code size)
Speedup Basic Cmplx Ctlr Filter Matrix Ststcs Xform Utils ALL
Q AVG 1.80 1.26 1.73 1.31 1.19 2.20 1.08 1.40 1.50
MAX 6.94 1.80 2.17 2.63 1.77 6.75 1.31 2.77 6.94
AVG 1.31 1.33 2.31 1.08 1.42 1.23 1.14 1.24 1.38
F32
MAX 1.42 1.64 2.55 2.09 1.78 1.35 1.39 2.05 2.55
AICE-MINI+
1
A25/AX25 Multi-Core Processor (1/2)
Configurable L2 cache size of 0KiB, 128KiB, 256KiB, 512KiB, 1MiB and 2MiB
S
M Slave Port
(AXI-64)
Periodic
Services
PowerBrake
Clock Throttling
w. Duty Ratio
Core Logic
Idle Logic and
Power Off
Loop SRAM off
Time QuickNap™
Clock Gating
RTL Designs Cache-Intact Fast Core
Power Down, Wakeup
Taking RISC-V® Mainstream 28
AndeSight™: Professional IDE
Eclipse-based, enriched by 15-year effort
FreeRTOS
Task List
FreeRTOS
Event List