The Development of Flexible Integrated Circuits Based On Thin-Film Transistors

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Perspective

https://doi.org/10.1038/s41928-017-0008-6

The development of flexible integrated circuits


based on thin-film transistors
Kris Myny

The use of thin-film transistors in liquid-crystal display applications was commercialized about 30 years ago. The key advan-
tages of thin-film transistor technologies compared with traditional silicon complementary metal–oxide–semiconductor
(CMOS) transistors are their ability to be manufactured on large substrates at low-cost per unit area and at low processing
temperatures, which allows them to be directly integrated onto a variety of flexible substrates. Here, I discuss the potential of
thin-film transistor technologies in the development of low-cost, flexible integrated circuits for applications beyond flat-panel
displays, including the Internet of Things and lightweight wearable electronics. Focusing on the relatively mature thin-film tran-
sistor technologies that are available in semiconductor fabrication plants today, the different technologies are evaluated in
terms of their potential circuit applications and the implications they will have in the design of integrated circuits, from basic
logic gates to more complex digital and analogue systems. I also discuss microprocessors and non-silicon, near-field communi-
cation tags that can communicate with smartphones, and I propose the concept of a Moore’s law for flexible electronics.

T
hin-film transistors (TFTs) are currently the dominant tech- item. Then, when the RFID chip is potentially replaced with a thin-
nology for in-pixel switches and drivers in flat-panel displays. film NFC chip, standard smartphones and tablets equipped with
Trends in consumer electronics demand ever-higher display NFC readers could identify objects and connect them to the cloud.
resolution and brightness, lower power consumption, and new fea- Another advantage of thin-film IC technology is its potential to be
tures and form factors (such as curved and foldable displays). This combined with sensor or signage technology, thereby integrating
drives TFT devices to deliver more complex functions than simply more functionality into the objects, which is discussed in a section
switching. For example, recent bezel-less displays delegate the task on analogue circuits. Finally, I will briefly examine the potential of
of row selection to TFT circuits integrated next to the pixel array. silicon CMOS chip technology to be interfaced directly with TFT
Such driver circuits comprise thousands of switches operating circuitry.
together — previously a job for silicon chips mounted around the
display. TFT technology
Beyond displays, how far can thin-film circuits go in terms of The development and optimization of transistor technologies are
replacing silicon complementary metal–oxide–semiconductor driven by four important figures of merit: area, cost, power and
(CMOS) chips? Fig. 1 illustrates the key advantages of thin-film cir- performance. Power and performance are application-specific
cuits on flexible substrates. The circuits can be fabricated on large parameters that tend to become more demanding as the application
substrates, thereby creating very thin, lightweight and ultra-flexible field evolves. Because TFTs are developed mainly for display-like
electronics1,2. Folding, rolling or crumpling such flexible circuits is applications, the drivers of technological evolution are the demand
possible without destroying the electronic functionality. Because for higher resolution and brightness, which pushes transistors to
of these properties, a flexible TFT-based microprocessor3 (Fig. 1d) increased density and semiconductor performance. This evolution
or thin-film near-field communication (NFC) tag (Fig. 1e) can, for is also beneficial for thin-film IC applications.
example, be integrated imperceptibly into any object. TFT technol- TFT technologies have the potential to be low-cost, owing to
ogies also have considerable potential for fabrication on ultrathin the simple process flow (that is, limited number of lithographi-
stretchable substrates4 that can be made porous to create breathable cal steps, compared with Si CMOS) and material choices. Typical
devices for contact with skin. With these features, thin-film inte- channel lengths for TFT technologies are in the micrometre range.
grated circuits (ICs) could be a game-changer for wearable electron- Currently, thin-film ICs are area-inefficient due to non-optimized
ics. Ultrathin, conformable ICs in the form of a tattoo could be used design flows, including the fact that transistor architectures
to monitor vital body parameters, communicating these parameters have not been optimized for ICs. For example, a CMOS IC  lay-
directly to a patient’s smartphone or a medical database. out  based on  digital standard cells comprises several metal lay-
In this Perspective, I discuss the potential of thin-film circuits on ers dedicated to routing that are on top of the Si CMOS transistor
plastic substrates for the development of Internet of Things (IoT) layers. Standard TFT transistor architectures on the other hand
and wearable applications. First I look at the different TFT tech- have a limited number of metal layers available (Fig. 1f), as addi-
nologies that can be realized on flexible substrates, and then discuss tional metal layers are  not required for backplane applications.
the impact TFT technology will have on circuit design at the level of Interconnecting different standard cells for a TFT-based digital
digital logic gates and very-large-scale integration (VLSI) digital cir- chip can only be realized by the metal layers already present in the
cuits. For the latter, I consider the use of thin-film ICs in the creation TFT stack. Routing on top of such standard cells cannot be maxi-
of low-cost radiofrequency identification (RFID) tags for everyday mized, resulting in non-optimal area consumption for TFT-based
items. Flexible chips may initially be used to simply identify each digital chips.

Imec, Leuven, Belgium. e-mail: kris.myny@imec.be

30 Nature Electronics | VOL 1 | JANUARY 2018 | 30–39 | www.nature.com/natureelectronics

© 2018 Macmillan Publishers Limited, part of Springer Nature. All rights reserved.
Nature Electronics Perspective
a b c
Tactile pixel
Ultrathin foil

Bit line
Drain voltage Word line

d e f Lch (μm) ESL


SiNx
SD M2 SD M2
SiO2
IGZO
Gate M1 SiNx
Barrier
Flexible substrate

Lch (μm) SAL


SD M2 SD M2

Gate M1 SiNx
SiO2
IGZO
Barrier
Flexible substrate

Fig. 1 | Examples of flexible electronics and their applications. a, Illustration of a thin, large-area active-matrix sensor with 12 ×​ 12 tactile pixels.
b, Ultrathin plastic electronic foils are extremely lightweight (3 g m−2); they float to the ground more slowly than a feather and are therefore virtually
unbreakable. Scale bar, 2 cm. c, At a thickness of only 2 μ​m, these devices are ultra-flexible and can be crumpled like a sheet of paper. Scale bar, 1 cm.
d, Photograph of a flexible TFT-based microprocessor. e, Photograph of a flexible TFT-based NFC tag. f, Cross-section of etch stopper layer (ESL) and self-
aligned layer (SAL) amorphous indium–gallium–zinc-oxide (IGZO) transistor configurations. Lch indicates the channel length. There are two metal layers
available: metal 1 (M1) or gate, and metal 2 (M2) or source–drain (SD). SiO2 and SiNx are typically used as dielectric and passivation layers. Credit: panels
a–c reproduced from  ref. 1, Macmillan Publishers Ltd; panel d reproduced from ref. 3, IEEE.

At present, the mainstream TFT technologies available in con- patterned mostly into small islands and the critical layers of the
sumer electronics products are amorphous silicon (a-Si), low-tem- TFT stack can be located near the neutral plane of the full stack by
perature polycrystalline silicon (LTPS) and amorphous metal-oxide matching the substrate and the topstrate or encapsulation. This is
semiconductors (mainly indium–gallium–zinc-oxide, IGZO) fully exemplified by the ultra-flexible organic TFT backplane, which
(Table 1). Metal-oxide TFT is a promising n-type-only technology has a total thickness of just 2 μ​m (ref. 1).
for flexible IC circuits, as it can be manufactured at process temper- This Perspective focuses on the mature technologies that are
atures within the thermal budget of flexible substrates5, while still available in semiconductor fabrication plants (‘fabs’) today. It is
exhibiting a charge carrier mobility close to or above 10 cm2 V–1 s–1, also worth noting a number of encouraging recent developments
in contrast with 0.5–1  cm2  V–1  s–1 for a-Si (refs  6,7). LTPS transis- with carbon nanotubes12–15 and several two-dimensional semicon-
tors require larger process temperatures and a more complex pro- ductors16, such as graphene15,17,18, black phosphorus19 and chalco-
cess flow, resulting in complementary p-type and n-type TFTs with genides20–23, which could provide next-generation flexible TFT IC
larger mobilities (50–100 cm2 V–1 s–1)7,8. In addition, the amorphous technologies, either as novel standalone transistor technologies or
nature of IGZO as a semiconductor5 provides a TFT scaling road- by complementing existing TFTs. Furthermore, a key benefit of
map in which shorter-channel TFTs retain good performance char- some TFT technologies is the possibility to use additive manufac-
acteristics, which is beneficial for both high-resolution displays and turing techniques like printing, which could reduce costs24–29. The
flexible IC applications. In contrast, polycrystalline semiconductors main challenges of printed electronics at the circuit level are vari-
have a negative impact on TFT behaviour depending on the crys- ability (device mismatch), large overlaps (source–drain to gate) due
tal size and channel length. IGZO TFTs with channels as short as to layer-to-layer registration rules increasing the parasitics, and
30 nm have already been demonstrated for transistors fabricated in large device dimensions, which result in slower-operating circuits.
the back-end-of-line of conventional silicon CMOS chip technol-
ogy9. Moreover, organic transistors are widely studied as a potential Digital logic gates
candidate for flexible ICs to complement n-type metal-oxide TFTs10, Logic gates are the building blocks of complex digital circuits and
because p-type metal-oxides matching the performance of amor- require specific optimization depending on the process technology.
phous IGZO have not yet been discovered. The most optimal configuration is CMOS, which profits from not
A recent review of the effects of mechanical stress on the intrin- only the co-existence of complementary p-type and n-type tran-
sic electrical performance of different semiconductors concluded sistors, but also all the circuit techniques developed for conven-
that amorphous metal-oxide semiconductors are the most resil- tional Si CMOS since the 1970s. Complementary logic is possible
ient under mechanical strain11. In addition, semiconductors are in LTPS, but organic and metal-oxide TFTs do not have adequate

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© 2018 Macmillan Publishers Limited, part of Springer Nature. All rights reserved.
Perspective Nature Electronics

Table 1 | Comparison of different properties and applications for the four TFT technologies
Parameter a-Si LTPS Oxide Organic
µ (cm² V s )
–1 –1
0.5–1 50–100 10–40 0.1–10
Process complexity Low High Low Low
Manufacturing cost Low High Low Low
Bias and light stability Poor Good Fair Poor
Intrinsic properties on Poor Poor Good Fair-to-good
mechanical stress, without
stack optimization
Semiconductor n-type CMOS n-type p-type (n-type possible)
TFT-to-TFT uniformity Good Low Good Low
Large-area uniformity Good Low Good Low
L-scaling (lateral device – Limited due to Deep-submicrometre demonstrated Limited due to
architecture) polycrystalline contact resistance
semiconductor and polycrystalline
(µ​m-range) semiconductor (µ​m-range)
Backplane applications Low-end and large-area High-end display Low-to-high-end display and imager Low-end backplane and
display and imagers and imagers, with applications and large-area panels circuit applications
on-panel circuitry
Circuit applications Low-end applications High-end digital and Low-to-high-end digital, low-to-medium- Low-end applications
analogue end analogue

complementary counterparts. The level of matching for both tran- Diode-load logic operates much faster than zero-VGS-load logic but
sistor types will affect the properties of the complementary logic suffers from a low gain and reduced noise margin, and therefore
gate, including speed, power, robustness and area. In a comple- lower overall robustness31.
mentary technology, both transistor types must possess a near-zero Several methods can be used to increase the robustness of these
threshold voltage and sufficiently low off-current. Furthermore, the logic gates. One option is to increase the number of transistors per
charge carrier mobilities must differ by no more than a decade for logic gate in order to improve the noise margin, but at the cost of a
both transisitor types. Low threshold voltages are essential for larger area. Alternatively, transistors can be operated in two differ-
downscaling the supply voltage. Off-currents directly impact the ent operation modes — depletion or enhancement — and with at
static leakage current of a logic gate in both its on- and off-state, least two different threshold voltages per logic gate. The practicali-
and therefore affect its total power consumption. Figure  2 shows ties of implementing different threshold voltages are often depen-
an example whereby the off-current of the p-type transistor con- dent on the particular technology; examples include doping the
tributes mainly to the static power consumption for different inte- channel, varying the thickness of the semiconductor and changing
gration levels of the targeted circuit. Low off-currents will become the gate–dielectric thickness. A primary consideration in the choice
more important as we reach higher circuit integration densities. of the implementation is for process flow to stay sufficiently simple
In addition, differences in charge carrier mobility between n- and such that yield and cost remain attractive.
p-type TFTs have an impact on area, speed and power. If the mobili- By nature of having a thin film of semiconductor as the active
ties differ too much, the area consumption and speed of the comple- layer, a TFT can naturally be equipped with two gates: a front
mentary logic gate will be negatively affected in favour of unipolar gate and a back gate. A back gate operates in a similar way to the
logic gates. body bias of Si CMOS and can therefore be used to regulate the
Implementing a complementary technology flow is more com- threshold voltage of each TFT individually. Dual-gate unipolar
plex than fabricating a unipolar transistor technology, and the inverters have already proven their benefits in terms of logic gate
additional steps for a complementary flow relate directly to higher robustness32 without an additional penalty on area. In this solu-
manufacturing cost. Therefore, from the cost perspective, unipolar tion, a global chip-level bias signal is required, for example, to shift
technologies can be beneficial for the realization of a flexible digital the threshold voltage VT for all drive TFTs. The inverter scheme is
IC, especially when there is no area reduction as a result of the intro- shown in Fig. 2g.
duction of a non-matching complementary semiconductor. Logic gate robustness can also be improved for back-gate-
Unipolar logic gates are the main option for realizing flexible ICs free TFT technologies by introducing more transistors per logic
in TFT technologies that do not have a complementary counterpart. gate. Two examples are level shifters33 and pseudo-CMOS logic
The main disadvantages of unipolar logic gates over complementary (Fig. 2h)34, both of which shift the inverter’s voltage transfer curve
logic gates are reduced robustness30 and increased area and power towards the middle of the power rail, thereby improving robustness.
consumption. Figure  2 details different unipolar logic topologies. Besides an increase in consumed area, an additional power rail to
Resistive-load logic requires on-chip resistors and will result in the drive the additional TFTs may be required for optimal operation.
lowest TFT count. If the technology does not offer resistors in the Level shifter logic with positive feedback employs 4–5 TFTs for an
right range, a TFT can alternatively be used as a load. Two options inverter function with only two power supplies35. This logic style
in this regard are shown in Fig. 2e,f: enhancement-load or diode- results in the largest unipolar inverter gain and therefore the highest
load logic, and depletion-load or zero-VGS-load logic (VGS being the noise margin per supply voltage published to date (76 dB and 8.2 V
voltage between the gate and the source). The suitability of each on 20  V, respectively), which is obtained by positive feedback on
option depends on the available threshold voltage of the existing the back-gate, including a global signal within power rails to tune
technology. Zero-VGS-load logic only operates with normally-on individual threshold voltages. Finally, the robustness of unipolar
devices, or devices that are already switched on at 0  V gate bias. logic gates can be improved by using unipolar differential logic, at

32 Nature Electronics | VOL 1 | JANUARY 2018 | 30–39 | www.nature.com/natureelectronics

© 2018 Macmillan Publishers Limited, part of Springer Nature. All rights reserved.
Nature Electronics Perspective
a 1 μA
b
p-TFT n-TFT 10 mW VDD = 10 V I
100 nA 10 nA
I
1 mW 1 nA
10 nA
100 μW
100 pA

Static Power (W)


1 nA
10 μW
IDS (A)
10 pA
100 pA
1 μW 1 pA
10 pA
100 nW
1 pA 10 nW
100 fA 1 nW

10 fA 100 pW
–10 –5 0 5 10 102 103 104 105 106
VGS (V) Number of logic gates

c d e f
100 nW
VDD VDD VDD
Power consumption for 10,000 n-TFTs (W)

1 μW
Moore’s law + technological evolutions,
10 μW gate and system level Out Out Out

100 μW In In In
200 nm
1 mW Moore's law for flexible GND GND GND
500 nm
electronics
10 mW g h
2 μm VDD Vbias VDD
Scaled SAL [46]
100 mW
5 μm
1W Pseudo Out
ESL SAL Out
CMOS In In In
10 W Vback

GND GND
100 W
10 μs 1 μs 100 ns 10 ns 1 ns 100 ps 10 ps
Gate delay (s)

Fig. 2 | Predicted impact of TFT technology parameters on power consumption and logic styles. a, TFT transfer characteristics of complementary
transistors with equal mobility and threshold voltage, where the p-type off-current is varied. IDS, current between drain and source; VGS, voltage between
gate and source; Ioff, current at zero voltage. b, Impact of varying p-type off-currents on the static power consumption of complementary logic gates for
increasing integration. c, Impact of technology improvements on power consumption and gate delay for IGZO ESL (Fig. 1)44, SAL (Fig. 1)41 and scaled-
SAL46 technologies. Data points from a 12-bit IGZO RFID transponder chip realized in ESL44 (black square) and SAL41 (black circle) technologies. The
IGZO NFC chip is represented by the red circle, realized in a scaled-SAL technology46. The red dashed line shows the impact on power and gate delay for
the scaled-SAL NFC chip, if Moore’s law for flexible electronics is applied with full geometry and voltage scaling, ranging from 5 μ​m to 200 nm. The blue
square is an extrapolation target that reveals the need for additional circuit and technology evolutions to reach ultralow-power, fast-operating circuits.
d, n-type resistive-load logic. GND, ground. e, n-type diode-load logic. f, n-type zero-VGS-load logic. g, Dual-gate n-type diode-load logic. h, n-type diode-
load pseudo-CMOS logic.

the cost of larger area consumption36. This style uses only unipolar A third way to lower the power consumption could be found
single-gate TFTs and combines positive feedback with the concept in technological improvements or evolutionary steps. Technology
of differential logic. scaling similar to Moore’s law for flexible thin-film ICs may also
A fundamental problem of unipolar logic gates is their static be crucial for the realization of complex VLSI circuits on foil,
power consumption. Dynamic logic is therefore an interesting area thereby paving the way to a larger portfolio of applications. The
of research as it has already been shown to lower the static leak- intrinsic delay of scaled logic gates will improve with the scaling
age current and reduce area consumption37. The leakage current of factor when full scaling (that is, equal in voltage and geometry) is
the technology has an impact on its operating frequency. VLSI TFT applied (Fig. 2c). The transistor density needed to realize complex
circuits based on such clocked dynamic logic are still a challenge circuits improves with the square of the scaling factor, as does the
because of the difficult design and strong requirements on clock power per function. The power density therefore remains equal.
synchronization. The NFC chip described in the following section is comprised of
Future trends may be to invent novel logic gates based on uni- 1,712 metal-oxide n-TFTs, exhibiting 7.37 ns gate delay and 7.5 mW
polar technologies that actively compensate for the shortcomings power consumption. Figure  2c recalculates this for 10,000 TFTs,
of regular unipolar logic gates, without needing to add the com- assuming mainly static power losses. Applying Moore’s law to flex-
plementary transistor-type  and, consequently, avoiding a more ible eletronics towards a 200 nm gate length results in 737 ps gate
complex process flow. Such logic gates may employ additional delay and 438  μ​W power consumption for 10,000  n-TFTs. These
transistors with a feedback function that reduces transistor leakage numbers only consider advancements in the device parameters. In
after the switching action has occurred38. Feedback circuits at the reality, parasitics from the interconnects play a crucial role and must
system level for disabling large idle blocks are also unexplored in be taken into account. Lowly resistive and strongly decoupled metal
TFT circuits. wires for interconnects are also of high importance for realizing this

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© 2018 Macmillan Publishers Limited, part of Springer Nature. All rights reserved.
Perspective Nature Electronics

roadmap. Power density will be of huge importance in the future, robustness of the chip without the presence of a back-gate. Different
as circuits tend to evolve into more complex chips, yielding more implementations of the pseudo-CMOS logic gate have been used
functionality and transistors in a similar area. Power consumption across the design to serve a variety of different purposes, includ-
and joule heating will require particular attention in thin-film tech- ing fast implementations for the clock division part and low-power
nologies because plastic substrates and thin-film metals are poor implementations for the core part.
heat conductors. If dynamic power consumption in such novel Figure  3 depicts the effect of downscaling the channel length.
logic styles proves to be dominant, additional voltage scaling and The gate delay of a pseudo-CMOS inverter at 5 V VDD and 10 V Vbias
clock frequency reductions (such as parallelism or pipelining) may improves from 63.4 ns to 5.2 ns for 5 μ​m to 2 μ​m channel lengths.
contribute to lowering the overall power consumption. Other well- This is within the specified duration of 7.37  ns, determined as
known techniques such as optimal device sizing, clock gating and the maximum gate delay needed to directly divide the 13.56 MHz
utilization of different logic styles in a single chip (fast logic gates incoming clock signal. A fast pseudo-CMOS implementation with a
versus low-power logic gates) can be explored for VLSI flexible ICs. 1.5 μ​m channel length (L1.5F) results in a gate delay of 2.4 ns at 5 V
TFT technologies are expected to improve parameters such VDD and 10 V Vbias.
as charge carrier mobility, variability and bias instability. Larger These gate delays are sufficient to divide the 13.56 MHz carrier
mobilities will enable logic gate optimization in terms of speed, frequency, yet the corresponding power figures suggest limiting the
area or a combination of both. With LTPS and amorphous oxide use of these gates when designing the full chip. Four different ratios
TFTs, the state-of-the-art transistor has a self-aligned archi- yielding low-power pseudo-CMOS implementations have been
tecture with minimum parasitic overlap between gate and evaluated, resulting in lower-power operation with a small increase
source/drain8,39–41, thus providing fast logic gates with low power in gate delay (Fig. 3c,d), which is affordable for the core part of the
consumption. Figure  2c shows such an improvement in power chip. Another key advantage of low-power implementations, par-
consumption and gate delay for slower etch stopper layer (ESL) ticularly LP3 and LP4, is the more symmetric power distribution
and faster self-aligned layer (SAL) metal-oxide TFT technologies. between VDD and Vbias (Fig. 3g). This ensures the correct generation
Figure  1f details the cross-section of both TFT architectures. ESL of VDD and Vbias by the rectifier circuit, as both power nodes observe
transistors exhibit a large parasitic gate–source and gate–drain over- a similar load.
lap capacitor, which is substantially minimized for the SAL archi- Low-power optimizations at the system and architectural levels
tecture. In addition, the channel length of SAL technology is equal have been performed by selectively choosing the proper pseudo-
to the definition of the gate layer, which makes it easily scalable, CMOS implementation where needed. The clock generator is a
whereas the channel length of ESL technology is approximately seven-stage toggle flip-flop chain in which the first stage is imple-
three times its critical dimension due to the overlaps created by mented with L1.5F logic (Fig. 4b). The power consumption has been
including the channel protection layer (as indicated in Fig.  1f). decreased gradually along these seven stages by selecting slower and
Further evolutions in stack definition are expected to provide more lower-power pseudo-CMOS gates. The final stages are implemented
metallization layers for interconnects and additional downscaling of with LP3 at a channel length of 4 μ​m, which has also been used for
the transistor footprint. the digital core part (Fig.  4c). The data-formatting block requires
a slightly faster operating speed; therefore LP3 at a channel length
Towards VLSI (digital) circuits on foil of 2 μ​m has been selected. The CRC code is hardwired or pre-pro-
RFID tags have received significant attention in the field of thin- grammed in the memory because a regular CRC generator would
film electronics because they could act as low-cost IoT nodes or add an additional 1/3  of the total number of TFTs, resulting in a
be capable of tagging everyday objects. High-frequency RFID tags, substantial reduction in static power consumption. The memory
operating at a base carrier frequency of 13.56 MHz, function at a has been realized in two generations: synthesized read-only mem-
maximum distance of 10 cm for proximity readers and up to 1 m ory (ROM), and laser-programmed ROM (LPROM). In LPROM,
for vicinity readers. TFT-based RFID tags can be grouped into two 16 bits of the payload and 16 CRC bits are one-time-programmable.
categories: those that communicate with specially designed RFID Figure 4h shows the die picture of the combined clock genera-
readers with custom protocols, like 8-, 12- or 16-bit tags41–45; and tor, digital core generator and data-formatting block. The size of the
those that communicate with commercial NFC readers, which are final chip is determined by the geometry of the standard cell library
embedded in many smartphones and handheld devices. Chip design and the number of metals used for interconnects, in this work lim-
requirements are less stringent for the first category, as simpler pro- ited to two, which also serve as gate and source–drain layer. An
tocols can be defined to account for the technology limitations of example standard cell is a two-input NOR gate (Fig. 4d) employing
TFTs. Such protocols are embedded on small-sized dedicated chips six IGZO TFTs and measuring 163 μ​m ×​  290 μ​m. The die picture
with a limited number of transistors (<​1,000), which is less interest- of the chip also reveals the location of the standard cells and the
ing for Si CMOS technologies. gaps in between the cells for the automatic place and route algo-
NFC tags must comply with ISO standards (for example, ISO rithm. The efficiency of the routing — and therefore the chip down-
14443-A), which were set for Si CMOS technologies exhibiting sizing — can be envisioned by introducing more routing layers, as
charge carrier mobilities approximately 100 times larger than those discussed previously. The standard cell library consists of six cells,
of metal-oxide TFTs. The selected ISO standard is the NFC barcode including a buffer and a flip-flop. Because automatic place and rout-
protocol, a tag-talks-only protocol whereby the tag transmits its ing algorithms introduce more parasitics, it was decided to manu-
128-bit memory in 1.21 ms and remains silent for 3.6 ms. This fast ally route the most time-critical blocks, such as the clock generator
NFC protocol can detect a tag within 5 ms. The three main chal- and the data-formatting block.
lenges when designing a metal-oxide TFT-based NFC barcode tag The final chip operates successfully at 3 V supply and 6 V Vbias,
are the data rates of 106 kbit s–1 (carrier frequency divided by 128), a consumes only 7.5 mW for 1,712 n-TFTs, and measures 50.55 mm2
128-bit memory read-out, including 16 CRC bits, and a limited inci- (Fig. 4e)46. Figure 1e shows a flexible NFC barcode chip, including
dent power at the tag from the smartphone, in the range of ~10 mW. rectifier and load modulator, combined with an inductive antenna.
The technology for this work is a self-aligned metal-oxide TFT The chip also serves as the bridge that connects the antenna. The
architecture, which was selected because of its low parasitics and pre-programmed 128-bit memory on the flexible NFC tag can be
potential for downscaling the channel length to 2 μ​m and 1.5 μ​m successfully tapped wirelessly into an NFC-enabled smartphone.
(Fig.  1f). Pseudo-CMOS logic gates have been chosen to serve Figure  4e–g provides more measurement details and shows the
as the primary logic family for this technology, maintaining the chip’s change in power with supply voltage. In addition, the mea-

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Nature Electronics Perspective
a b c d 30
Vbias = 2VDD 100 mW 40
200 Vbias = 2VDD Vbias = 2VDD LP4 Vbias = 2VDD
L5 20
100 20 LP3
L4 10
10 mW LP1

Power (mW)
Stage delay (ns)

40 L3 4 LP2

Stage delay (s)


LP3

Power (W)
L1.5F L2
20 L2 2 L2 10
L2 NFC 1 mW L2F
10 L2F specification 1 LP1
L3 7
L4 0.4 LP2 6
4 L1.5F 100 μW L5 5
0.2 LP4
2 0.1 4
1 10 μW 3
2 3 4 5 2 3 4 5 2 3 4 5
2 3 4 5
VDD (V) VDD (V) VDD (V)

e f g
Vbias VDD 1.0
TFT L2 L2F LP1 LP2 LP3 LP4

Relative power distribution


VDD = 3 V; Vbias= 6 V
0.8
T1 10/2 16/2 4/2 4/2 4/4 2/4
T1 T3
T2 100/2 66/2 40/2 40/2 20/2 10/2 In Out 0.6

Power Vbias
T3 100/2 100/2 100/2 60/2 60/2 60/2 T2 In T4
0.4

Power VDD
T4 100/2 100/2 100/2 60/2 60/2 60/2
GND 0.2

0.0
L2 L2F LP1 LP2 LP3 LP4

Fig. 3 | Optimization of single-gate pseudo-CMOS logic gates for power and speed. a,b, Impact of downscaling channel length for regular and fast
implementations of pseudo-CMOS logic on stage delay (a) and power consumption (b). c,d, Impact of different low-power implementations of pseudo-
CMOS logic on power consumption (c) and stage delay (d). e, Overview table of different transistor sizes for all implementations. All units are μ​m. L, channel
length; F, fast; LP, low power; T1–T4, transistors of a pseudo-CMOS logic gate, detailed in f. f, Schematic of a pseudo-CMOS logic gate. g, Relative power
distribution between Vbias and VDD for different pseudo-CMOS logic gate implementations. Credit: panels a–e adapted from ref. 46, IEEE.

sured signals of the IGZO NFC barcode tag when approached by can be brought to foil at low area and power consumption, a large
an NFC reader device are plotted in Fig. 4f,g. The correct proto- application field can be envisioned whereby data is pre-processed
col behaviour is observed, with a silent period of 3.6 ms alternat- at the patch or IoT-node level.
ing between 1.21 ms code-transmission periods. A more detailed
zoom of the first bits in the sequence shows the correct bit repre- Analogue circuits
sentation and bit-timing according to the ISO 14443-A protocol. IoT sensor nodes collect data in the analogue domain, to be digi-
Another interesting and complex digital circuit is a micro- tized with analogue-to-digital or time-to-digital converters prior
processor. The first (and so far most complex) thin-film flex- to cloud storage. Data processing in the digital domain is advanta-
ible microprocessor was published in 20053. It comprises ~32,000 geous for TFT-based circuits, as digital circuits are more mature
transistors based on flexible complementary LTPS transistors, than analogue TFT-circuits. Analogue-to-digital converters have
which are released from the carrier by employing the ‘surface-free already been demonstrated in TFT technologies, based on  a-Si,
technology by laser ablation/annealing’ process flow47. The first organic, metal-oxide and LTPS transistors, yielding up to 8-bit
unipolar organic microprocessor fabricated directly on flexible conversion at a maximum sampling rate of 300 S s–1 for unipolar
substrates exhibited a clock frequency of 40  Hz to execute 8-bit IGZO technologies51. Many improvements are still required before
operations48. In addition, 1-bit scalable microprocessor archi- commercial products are feasible, including a gradual change in
tectures have been demonstrated based on different emerging process from 1-bit threshold sensing to multibit sensor conversion.
foil-compatible semiconductors, namely carbon nanotubes12 and The analogue TFT world also benefits from the technologi-
two-dimensional materials49. Solution-processed n-type metal- cal evolutions discussed in the previous section. Introducing
oxides have been combined with an evaporated p-type organic higher-mobility semiconductors will lead to faster sampling
semiconductor, resulting in the first hybrid organic–oxide 8-bit rates and larger transconductances, assuming other TFT and
complementary thin-film microprocessors, operating at 2.1  kHz process parameters remain similar. The conversion speed can
(ref. 10). Extrapolating the speed of the microprocessor by replacing be increased by downscaling the TFT technology, although the
the logic gates with aforementioned fast pseudo-CMOS logic gates already limited gain of the operational amplifier or comparator
may result in speeds of more than 100,000 instructions per second, may be reduced further owing to the lower output resistance of
thereby enabling a broad window of applications. The power con- scaled TFTs. Improvements in variability and bias instability will
sumption of this chip will probably exceed the application speci- lead to lower offset for differential amplifiers, thereby increas-
fications, suggesting there is  a strong need to apply techniques ing the conversion accuracy. The introduction of a matching
to reduce the power consumption. At the system level, disabling complementary TFT is likely to be the most significant develop-
idle blocks in the architecture during operation by power gat- ment for analogue electronics, more so than introducing digital
ing, clock gating or active feedback via the back-gates can reduce flexible ICs, improving conversion rates, strongly enhancing the
power consumption. Designing complex architectures specifically offset and gain of the amplifiers, and downscaling the consumed
for each application will also provide significant benefits. Unused area. Analogue circuits based on unipolar technologies already
gates should be eliminated50, memory and bus widths should be benefit if stable passives (such as a high-resistivity layer with low
sized compliant to the application requirements, and VLSI circuit variation) are included in the process flow, thereby improving the
overheads should be limited. If sufficiently fast data processing area and gain of the amplifiers.

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© 2018 Macmillan Publishers Limited, part of Springer Nature. All rights reserved.
Perspective Nature Electronics

a
Power
Clock Digital
generator core
NFC
Modulator
ISO14443 Memory
format readout

IGZO NFC barcode tag

b
D Qn D Qn D Qn D Qn D Qn D Qn D Qn
L1.5F L2F L2 L2 L4_LP3 L4_LP3 L.4_LP3
13.56 MHz Clock/2 Clock/4 Clock/8 Clock/16 Clock/32 Clock/64 Clock/128
Q Q Q Q Q Q Q

Large Static power Low

Fast Speed Slow

c d
D Qn out
8:1 MUX
fc/128 outnot
Q

fc/128 7-bit binary 128 bit ROM D Qn


counter CA 96 25 78
2-bit line 3E 61 8F D1 fc/128 outEN
select Q
00 25 0E 4B
F0 93 2-bit bin
CRC:0D 20 counter

e f g
20 3.0 4
Vbias = 2VDD
1.21 ms
15 3
Power (mW)

2.0
Vout (V)

Vout (V)

10 2
1.0 3.6 ms
5 1

0 0.0 0
3.0 3.2 3.4 3.6 3.8 4.0 10 12 14 16 18 20 9.66 9.67 9.68 9.69 9.70 9.71 9.72
VDD (V) Time (ms) Time (ms)

h
Digital core (1,304 TFTs)
Clock generator
(274 TFTs)

ISO 14443 Format


(134 TFTs)

Fig. 4 | Design of the IGZO NFC barcode foil. a, System overview and key blocks of the IGZO NFC barcode tag. b, Detailed block diagram of the clock
generator, exhibiting seven toggle flip-flops. D, input of the flip-flop; Q, output; Qn, inverse output. c, Detailed block diagram of the digital core part,
designed in the LP3 library with a channel length of 4 μ​m (L4_LP3). fc, carrier frequency; outEN, output enable; outnot, inverse of the output; MUX,
multiplexer.  d, Standard cell layout of a NOR-2 input gate in the L4_LP3 library, measuring 163 μ​m ×​ 290 μ​m. e, The measured power consumption of the
barcode chip versus the supply voltage. f, Measurement details of the fully integrated IGZO NFC barcode, with the antenna displaying correct behaviour
when approached with an NFC reader device. g, Zoom of the first bits displaying correct bit representation of the ISO 14443-A standard. h, Die photograph
of the IGZO NFC foil, indicating the three main block diagrams. Figure adapted from: Credit: adapted from ref. 46, IEEE.

Amplifiers are required for a multitude of applications, not from LPROM to static random-access memory52, and in future
only sensor-node IoT. Integrated sense amplifiers are beneficial could be used in non-volatile memory arrays embedded in TFT
for reading out different memory topologies in a rapid fashion, technologies. Large-area imaging backplanes require in-pixel

36 Nature Electronics | VOL 1 | JANUARY 2018 | 30–39 | www.nature.com/natureelectronics

© 2018 Macmillan Publishers Limited, part of Springer Nature. All rights reserved.
Nature Electronics Perspective
amplification and sense amplifiers to detect incoming signals. Hybrid combination of silicon CMOS and TFT technologies
Low-noise amplification based on TFT technologies could also There are number of potential opportunities for Si CMOS chip tech-
be used in wearable health patches to monitor vital signals, nology to be interfaced directly with TFT circuitry. I focus here on
wherein sensors or electrodes are attached to the body and inter- solutions in which there is a clear gap in system requirements and
connected to a Si CMOS IC. The analogue amplifiers can be solutions offered by specific IC technologies. Flexible TFTs are lim-
mounted nearby the sensor/electrode to improve the signal-to- ited mainly in terms of their electrical performance; for example,
noise ratio of the sensor signal prior to transmission to the Si IC. Bluetooth or WiFi communication with TFTs is not yet possible
Single-stage high-gain amplification in such patches is a strong due to the limited cut-off frequency. Si CMOS ICs, in contrast, have
asset that has been demonstrated by means of a positive feed- area constraints and are therefore limited in terms of their number
back mechanism and back-gate technology in a unipolar IGZO- of input/output pads. Thus, it would be beneficial in some cases to
based design, leading to 30 dB gain53. The back-gate is capable combine silicon CMOS ICs and TFT flexible chips at the system
of not only enabling multi-threshold voltage logic (as discussed level. The choice for this solution will be strongly dependent on the
earlier), but also improving the transconductance or the output system requirements and will affect the cost and complexity of the
resistance of the individual transistors. Enhancing these TFT solution. An example of such integration is the hybrid system-in-
parameters is a valuable property of analogue circuits, which foil approach58,59, in which a thinned silicon CMOS IC is embedded
consists of load TFTs and current sources that require a large in a flexible substrate and combined with foil-compatible TFT tech-
output resistance, or improved transconductance for the input nologies and sensors. Previous sections discussed some examples
pairs, leading to 50  dB gain for a three-stage unipolar metal- of this approach, such as a Si NFC reader chip wirelessly connect-
oxide amplifier54. ing to a flexible TFT-based NFC tag, or a TFT low-noise amplifier
Designing analogue electronics requires a key understanding of located near a sensor input to improve the signal-to-noise ratio
the mismatch or deviations of parameters between two transistors. prior to transmitting this analogue signal to a Si chip. More obvi-
A mismatch law for conventional Si CMOS has been reported55, in ous examples are in fact active matrix displays and imagers. A TFT
which it was concluded that device parameter mismatch is inversely backplane in a display uses its transistors solely as switches or to
proportional to the square root of the device area. A properly oper- regulate the current through the OLED frontplane. More advanced
ating differential input pair or a current-mirror circuit relies on pixel schemes also employ multiple TFTs per pixel, thereby com-
the matching properties of two transistors. It has been shown that pensating for the non-idealities of TFT backplanes, such as bias
the spread in organic transistor characteristics is too large, thereby instabilities and uniformity issues. Si CMOS chips, like a graphics
excluding the design of a current-steering digital-to-analogue con- processing unit, will translate the display image into the desired
version architecture56. Instead, for this organic technology, it was data and then select signals. The trend towards bezel-free displays
found that the capacitor mismatch follows Pelgrom’s area-scaling moves more complexity to the TFT backplanes, requiring integrat-
rule, resulting in a 6-bit switched-capacitor architecture. An inter- ing TFT-based scan drivers for the signal selection and multiplexers
esting post-fabrication select-and-connect method has also been to reduce the number of data control signals.
reported to cope with large mismatch values for organic transis- A multiplexer/demultiplexer circuit based on TFTs could be
tors57. This method led to an optimal area and power overhead valuable for actively extending the limited number of input/output
reduction, compared with the introduction of many parallel tran- pins of a Si CMOS chip. Applications that require a large number
sistors. Device mismatch is a problem not only during manufac- of sensors or actuators can be envisioned in this regard. A large-
turing (for dimensions, doping and interfaces), but also during area wearable patch could consist of a large array of distributed elec-
handling and operation. Mechanical handling of flexible electron- trodes, with a TFT-based amplifier or analogue-to-digital converter
ics can introduce locally tensile or compressive stress on the device attached to each electrode. The pre-treated signals are subsequently
and therefore impact its characteristics. A proper ‘floor plan’ of the transmitted to a single Si CMOS IC by means of a TFT-based mul-
design is required to accommodate for such effects in final prod- tiplexer, for which time- or frequency-division multiplexing of the
uct handling. During operation, two transistors in a differential input/output pins are two valid candidates. The bandwidth of the
pair may be biased with different conditions, resulting in a different multiplexer will depend strongly on the technology, voltage range,
reduction in bias stress current for each transistor. This causes the number of input/output pins and power budget. Downscaling TFT
device characteristics to start deviating, which impacts the proper technologies will lead to lower supply voltages; 5 V, 3.3 V, 1.5 V and
functioning of the differential pair. It will be important for future sub-1  V VDD voltages can be envisioned, enabling direct commu-
developments, as technologies mature, to obtain accurate models nication between a flexible TFT IC and a Si CMOS IC60. On the
of the transistor behaviour under different circumstances, thereby other hand, Si CMOS ICs that need to drive high voltage actuators
ensuring correct functioning of the analogue blocks without severe can make use of TFT-based level shifters to increase the CMOS-
design overhead. compatible voltage range towards that required by the actuator.
Combining health patches or sensor nodes with RFID or NFC
tags is an intriguing direction for this field. As explained previ- Conclusions
ously, an accurate and stable time signal can be derived from the This Perspective discussed the opportunities and shortcomings of
incoming carrier frequency in an RFID tag. This time reference TFT technologies for applications beyond displays, such as low-cost
can be used to convert the sensor signal to a digital value via a IoT and wearable electronics. In order to optimize cost, robustness,
time-to-digital converter. A full NFC solution based on the NFC area and power, improvements in transistor technology must be
barcode protocol sets restrictions for the data conversion rate, as driven by the needs of flexible TFT-based ICs. One circuit-specific
128-bit data is transmitted within 1.21 ms. The minimum time for technology improvement includes the introduction of Moore’s law
analogue conversion is around 1 ms, depending on the number of for flexible electronics, in which flexible chips may become smaller,
occurrences needed prior to smartphone detection. Afterwards, thinner and higher performing. Another key asset for TFT tech-
the converted digital bit sequence must be included together with nologies is an individual back-gate for each transistor, which can be
a newly calculated 16-bit CRC number, albeit by means of a CRC employed in logic gates to enable the use of multiple threshold volt-
generator, a look up table or a synthesized code scheme. The num- ages and therefore provide more robust digital logic, or in analogue
ber of converter bits will decide which of the previously discussed circuits where the transconductance or output resistance must be
solutions may be the most appropriate, given the area and power adapted. Complex routing in flexible circuit technology may also
constraints of the tag. require extra metal layers in addition to the gate and source–drain

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© 2018 Macmillan Publishers Limited, part of Springer Nature. All rights reserved.
Perspective Nature Electronics

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Correspondence and requests for materials should be addressed to K.M.
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