CS 322

Computer Organization

Fall 2021

1
Refer to Book2:
Patterson & Hennessy,
“Computer Organization &Design”

Slide Sources:
Dr. Sumanta Guha (Asian Institute of technology)
who adapt and supplement slides Patterson &
Hennessy COD book website (copyright Morgan
Kaufmann)

2
2.1 Introduction
◼ In this book, we will study
 The organization of a real computer (MIPS architecture) and its
instruction set.
◼ Here, we start to learn how to design a computer
organization, considering design goals:
 maximize performance, minimize cost and energy, and reduce
design time
◼ Our starting point is the instruction set which specifies a
processor’s functionality
 what operations it supports
 what storage mechanisms it has & how they are accessed
 how the programmer/compiler communicates programs to
processor

3
Instruction Set Similarity
◼ By studying, the instruction set of MIPS technology, you
will notice that its similarity with Mano’s computer.
◼ Also, this similarity will exist by comparing MIPS
instruction set with 3 other popular instructions sets:
 ARMv7 (32 bits) and ARMv8 (64 bits), the most popular
instruction set in the world.
 Intel x86, which powers both the PC and cloud of PostPC Era.
◼ The similarity of instruction sets occurs because:
 There are a few basic operations that all computers must provide
(ALU operation, memory access, control flow,… ).
 All computers are constructed based on similar principles.

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MIPS architecture
◼ MIPS technologies
 Inspired most architectures developed since the 80's
 Its name is not related to millions of instructions per second
 It stands for Microcomputer without Interlocked Pipeline Stages

◼ MIPS ISA– Instruction Set Architecture:

– A representative RISC ISA
 RISC -- Reduced Instruction Set Computer
 Only load and store instruction can access memory, other
instructions only performed on registers
– A fixed-length, regularly encoded instruction set
2.2 Operations of Computer Hardware

◼ All MIPS arithmetic instructions have 3 operands

◼ Operand order is fixed (ex: destination first)
Assume that :
A → $s0
◼Example: B → $s1
C code: A = B + C C → $s2

MIPS code: add $s0, $s1, $s2 #$s0$s1+$s2

compiler’s job to associate

variables with registers
Design Principle 1
Design Principle 1: simplicity favors regularity.
which means “Regular instructions make simple hardware!”

◼ Simpler hardware reduces design time and

manufacturing cost. Allowing variable number
of operands would
simplify the assembly
◼ But, this complicates some things... code but complicate the
hardware.
C code: A = B + C + D;
E = F - A;
Assume that :
A → $s0
MIPS code add $t0, $s1, $s2 B → $s1
(arithmetic): add $s0, $t0, $s3 C → $s2
sub $s4, $s5, $s0 D → $s3
E → $s4
F → $s5
2.3 Operands of the Computer Hardware
◼ Arithmetic operations occur only on registers in MIPS
instructions, thus the operands of arithmetic instructions
must be stored in registers.
◼ In MIPS :
 There are small number of registers – only 32 registers provided
with 32 bits each.
◼ MIPS operands:
 Use two- character names following a dollar sign to represent a
register, instead of numbers from 0 to 31.
 Example:
$t0-$t9 – temporary registers needed to compile the program
into MIPS instructions
$s0-$s7 – saved to variables in high level programs

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Design Principle 2
Design Principle 2: smaller is faster.
which means choose small number of registers for fast operations.

◼ Why?
 The number of bits it would take in instruction format
(5 bits in MIPS)
 Electronic signals have to travel further on a
physically larger chip increasing clock cycle time.
 Smaller is also cheaper!
MIPS Load/Store Architecture
◼ MIPS is a Load/Store Architecture
 Only load/store type instructions can access memory
◼ Instructions that transfer data between memory and
registers are called data transfer instructions.
◼ MIPS data transfer instructions
 lw (load word), copies data from memory to a register.
 sw (store word), copies data from a register to memory.

◼ To access a word in memory, the instruction must supply

the memory address

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Load/Store Instructions
◼ Load instruction Constant Base address
Destination register (offset) (start address of data)

MIPS Code: lw $t0, 0($s3) #$t0  M[$s3+0]

◼ Store instruction Constant

(offset) destination address
Source register

MIPS Code: sw $t0, 0($s3) #M[$s3+0] $t0

Note:
- Load word has destination first, store has destination last

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 MIPS byte addressing
◼ MIPS actually uses byte addressing
◼ Most data items are contained in words, a word is 32 bits
or 4 bytes. Registers hold 32 bits of data.
◼ In MIPS, words must start at addresses that are
multiples of 4. This is called an alignment restriction.
Assume PC=0,
want to read next word
of data (4 bytes)

To get next data

word, need to
increment PC
by 4 4GB= 232 bytes with byte addresses from 0 to 232- 1
= 230 words with byte addresses 0, 4, 8, ... 232- 4
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 Memory Organization:
Big/Little Endian Byte Order
◼ Bytes in a word can be numbered in two ways:
 byte 0 at the leftmost (most significant) to byte 3 at the
rightmost (least significant), called big-endian 0 1 2 3
 byte 3 at the leftmost (most significant) to byte 0 at the
rightmost (least significant), called little-endian 3 2 1 0

Big-endian Little-endian
Memory Memory

Word 0 Byte 0 Byte 1 Byte 2 Byte 3 Byte 3 Byte 2 Byte 1 Byte 0 Word 0

Word 1 Byte 4 Byte 5 Byte 6 Byte 7 Byte 7 Byte 6 Byte 5 Byte 4 Word 1

MIPS use “big-endian” byte order

 Load/Store Instructions
◼ What about complex data —arrays and structures.
◼ Byte addressing also affects the array index.
Assume that :
h → $s2
◼ Example: A → $s3
C code: A[12] = h + A[8];
Base register
destination Offset
(start address
(multiple of 4)
of array)
MIPS code (load): lw $t0, 32($s3)
#$t0 A[8]
#$t0 M[$s3+(8*4)]
(arithmetic): add $t0, $s2, $t0 #$t0 h +A[8]
#$t0 $s2+$t0
(store): sw $t0, 48($s3) #A[12]$t0
#M[$s3+(12*4)] $t0
The compiler which allocates data structures like arrays and structures to locations
in memory. So, it can then place the proper starting address into base register.
Spilling registers
◼ Many programs have more variables than computers
have registers.
◼ So, the compiler tries to spilling registers , which means:
 keep the most frequently used variables in registers and
 place less commonly used variables (or those needed later) into
memory

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Constant or Immediate Operands
◼ Small constants are used quite frequently (50% of operands)
e.g., A = A + 5;
B = B + 1;
C = C - 18;

◼ One Solution:
 Reserve a register for constants
 put program constants in memory and load them as required

◼ Alternative solution:
 Offer versions of arithmetic instructions in which one operand is a constant.
◼ MIPS Instructions:
addi $s3, $s3, 4 # $s3=$s3 + 4
The operations in the alternative solution are much faster and use less energy,
Than if constants were loaded from memory.

Design Principle 3: Make the common case fast

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The register zero
◼ MIPS dedicates a register $zero ( register number $0) to
be hardwired to the value zero.
◼ The constant zero offers useful variations in instruction
set
Ex: The move operation is just an add instruction where
one operand is zero.
add $s1, $s0, $0 # $s1 $s0
# $s1 $s0+$0

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So far we’ve learned:
◼ MIPS
 loading words but byte addressing with big-endian
 arithmetic on registers only (Load/store instruction

◼ Instruction Meaning

add $s1, $s2, $s3 $s1 = $s2 + $s3

sub $s1, $s2, $s3 $s1 = $s2 – $s3
addi $s3, $s3, 4 $s3 = $s3 + 4
lw $s1, 100($s2) $s1 = M[$s2+100]
sw $s1, 100($s2) M[$s2+100]= $s1
2.5 Representing instructions in the computer

◼ Instructions, like registers and words of data, are also 32

bits long
◼ Instruction Format R-type (“R” for Register):

opcode – first second register function field -

register destin- shift selects variant
operation register
source ation amount of operation
source
operand operand operand

◼ Example: add $t0, $s1, $s2 #$t0 $s1+$s2

 registers are numbered, e.g., $t0 is 8, $s1 is 17, $s2 is 18

31 26 25 21 20 16 15 11 10 65 0
000000 10001 10010 01000 00000 100000
op rs rt rd shamt funct
Design Principle 4
Design Principle 4: Good design demands a compromise

The compromise chosen by the MIPS designers is to

keep all instructions the same length

➢ thereby requiring different kinds of instruction formats for

different kinds of instructions

◼ Consider the load-word and store-word instructions,

 what would the regularity principle have us do?
◼ The offset were to use one of the 5-bit fields in previous
instruction format, and it would be limited to only 25 or 32
…. too small
I-type instruction format
◼ Introduce I-type instruction format (“I” for Immediate) is
used by immediate and data transfer instructions

◼ Example: lw $t0, 1002($s2) #t0 M[$s2+1002]

31 26 25 21 20 16 15 0
100011 10010 01000 0000001111101010
op rs rt 16 bits offset

2^16=65536/4=16384 maximum array size

Immediate Operands
◼ It uses I-type format

◼ Example: addi $s1, $s1, 4 #$s1 = $s1 + 4

31 26 25 21 20 16 15 0
001000 11101 11101 0000000000000100
op rs rt 16 bits offset
Distinguish formats
◼ To reduce the complexity of hardware with multiple
instruction formats, keep the formats similar.
 For example, the first three fields of the R-type and I-type
formats are the same size and have the same names; the length
of the fourth field in I-type is equal to the sum of the lengths of
the last three fields of R-type.
◼ So, each format is assigned a distinct set of values in the
first field (op) so that the hardware which format to deal
with.

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“n.a.” (not applicable) means this field does not appear in this format.
Translating MIPS Assembly Language
into Machine Language
◼ If $t1 has the base of the array A and
$s2 corresponds to h, the statement
A[300] = h + A[300];
is compiled into:
lw $t0,1200($t1) # $t0 gets A[300]
add $t0,$s2,$t0 # $t0 gets h+A[300]
sw $t0,1200($t1) # A[300]gets h+A[300]
◼ let’s first represent the machine language instructions
using decimal numbers.

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Translating MIPS Assembly Language
into Machine Language (Cont.)
◼ The machine language instructions using decimal
numbers

◼ The machine language instructions using binary

representation

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Other examples

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2.6 Logical operations
◼ C and Java logical operators and their corresponding
MIPS instructions.

◼ Note:
 MIPS implement NOT using a NOR with one operand being zero.
A NOR 0 = NOT (A)
 The two MIPS shift instructions are called shift left logical (sll)
and shift right logical (srl).

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MIPS Shift operation
◼ Assuming that the original value was in register $s0 and
the result should go in register $t2:
sll $t2,$s0,4 #$t2 = $s0 << 4 bits
◼ The machine language of the instruction above

◼ Note:
 The encoding of sll is 0 in both the op and funct fields
 The rs field is unused and thus is set to 0.

◼ Logical operations has R-type instruction format.

All R-type instructions has 0 in op
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MIPS Logical operations
◼ AND (funct=3610) and OR (funct=3710)operations,
AND $t0,$t1,$t2 # $t0 = $t1 & $t2
OR $t0,$t1,$t2 # $t0 = $t1 | $t2
◼ NOT can be implemented using NOR, if the register
$t3 has the value 0, the result of the MIPS instruction
NOR $t0,$t1,$t3 # $t0 = ~($t1 | $t3)

◼ Constants are useful in AND and OR logical operations

as well as in arithmetic operations, so MIPS also
provides the instructions and immediate (andi) and or
immediate (ori).
MIPS instruction set architecture has
no immediate version of NOR. 29
2.7 Instructions for making decisions
◼ Decision making instructions
 alter the control flow, i.e., change the next instruction to be
executed

◼ MIPS conditional branch instructions:

# if $t4 != $t5 goto Label address
bne $t4, $t5, Label
# if $t0 = $t1 goto Label address
beq $t0, $t1, Label

◼ Example: if (i==j) h = i + j;
bne $s0, $s1, Label
add $s3, $s0, $s1
Label: ....
Control: Conditional Branch
◼ The instructions bne and beq are I-type format
bne $t0, $t1, Label I-type instructions
beq $t0, $t1, Label

op rs rt 16 bit offset I-Type

◼ 16 bits is too small to reach a 232 address space

◼ Solution: Specify a register (as for lw and sw) and add it

to 16-bit offset
 use PC (= program counter), called PC-relative addressing,
based on
 principle of locality: most branches are to instructions near
current instruction (e.g., loops and if statements)
Control: Conditional Branch
word-relative addressing:
◼ Also, the 16-bits offset in MIPS 25 words = 25*4=100 bytes;
 refer to the number of words to the next instruction instead of
the number of bytes.
After 25 words from PC
◼ Example: beq $t0, $t1, Label
000100 01000 01001 0000000000011001
Assume Label is after this beq instruction by 25 instructions
(i.e. words), this instruction at address 100010
◼ So, PC =(PC+4)+(25*4)
=(1000+4)+100 1000 Beq $t0, $t1,Label
1004
= 1104 PC

MIPS branch destination address

= (PC + 4) + (4 * offset)
Label 1104
Because hardware typically increments PC early
in execute cycle to point to next instruction
Control: Unconditional Branch (Jump)
◼ MIPS unconditional branch instructions:
j Label
◼ Example:
if (i!=j) beq $s4, $s5, Else
h=i+j; add $s3, $s4, $s5
else j Exit
h=i-j; Else: sub $s3, $s4, $s5
Exit: ...
◼ J-type (“J” for Jump) instruction format
op 26 bit number
6 bits 26 bits word-relative
 Example: j Label # addr. Label = 100 addressing:
25 words = 100 bytes
000010 00000000000000000000011001
 Addresses in Jump
◼ Word-relative addressing also for jump instructions

Pseudo-direct J op 26 bit address

addressing

◼ MIPS jump j instruction replaces lower 28 bits of the

PC with 00L where L is the 26 bit address; it never
changes upper 4 bits
 Example: if PC = 1011X (where X = 28 bits), it is replaced
with 101100L
 there are 16(=24) partitions of the 232 size address space,
each partition of size 256 MB (=228), such that, in each
partition the upper 4 bits of the address is same.
 if a program crosses an address partition, then a j that
reaches a different partition has to be replaced by jr with a
full 32-bit address first loaded into the jump register
 therefore, OS should always try to load a program inside a
single partition
Loops
◼ Here is a traditional loop in C:
while (save[i] == k)
i += 1;
◼ Assume that i and k correspond to registers $s3 and $s5
and the base of the array save is in $s6.

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Loop assembled instructions

The assembled instructions and their addresses

Word-addressing & PC-relative: Word & Pseudo-direct addressing

PC=80016 + (2*4) = 80024 PC= PC|| (20000*4) = 8000036
Control: Comparison instructions
◼ Comparison instructions: less than, greater than,…
slt $t0, $s1, $s2
#$t0=1,if $s1<$s2, otherwise $t0=0;

◼ It is R-type instruction (funct=4210)

◼ MIPS offers two versions of the set on less than
comparison to handle signed and unsigned numbers..
 Set on less than (slt) and set on less than immediate (slti)
work with signed integers.
 Unsigned integers are compared using set on less than
unsigned (sltu) and set on less than immediate unsigned
(sltiu)

37
Signed versus Unsigned Comparison

38
Case/Switch instructions
◼ The simplest way to implement switch:
 Turning the switch statement into a chain of if-then-else
statements.
◼ More efficiently alternatives: jump address table or jump table
 It is a table of addresses that correspond to labels in the code,
 The program loads the appropriate entry from the jump table into a
register. It then needs to jump using the address in the register.
◼ To support such situations, computers like MIPS include:
 a jump register instruction (jr), meaning an unconditional jump to
the address specified in a register. Then it jumps to the proper
address using this instruction.

39
2.8 Procedures in computer hardware
◼ In MIPS, to execution of a procedure (or callee), the
program must :
1. Put parameters in a place where the procedure can
access them.
2. Transfer control to the procedure.
3. Acquire the storage resources needed for the procedure.
4. Perform the desired task.
5. Put return values in a place where the calling program
can access it.
6. Return control to the point of origin, since a procedure
can be called from several points in a program.

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2.8 Procedures in computer hardware
◼ MIPS software follows the following convention for
procedure calling in allocating its 32 registers:
 $a0–$a3: four argument registers in which to pass parameters
 $v0–$v1: two value registers in which to return values
 $ra: one return address register to return to the point of origin

◼ To allocate these registers, MIPS assembly language

includes an instruction just for the procedures (i.e. callee),
the jump-and-link instruction (jal)
jal <Address> # $ra = PC + 4
# PC = <address>

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 The big picture

caller, Callee,
* puts the parameter values in $a0–$a3 *performs the calculations,
* uses jal X to jump to procedure X *places the results in $v0 and $v1,
*returns control to the caller using
◼ Need “jump” and “return”: jr $ra.

 jal ProcAddr # issued in the caller

• save the return instruction address in $31 ($ra= PC+4)
• jumps to ProcAddr (PC = ProcAddr)
 jr $ra # last instruction in the callee
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• jump back to the caller procedure (PC = $ra)
MIPS general purpose registers

Register 1, called $at, is reserved for the assembler, and

registers 26–27, called $k0–$k1, are reserved for the operating system. 43
More registers: Stack
◼ The ideal data structure for spilling registers is a stack
◼ Stack
 A dedicated area of memory
 Last In First Out (LIFO)
 Used to
◼ Hold values passed to a procedure as arguments if arg > 4
◼ Save register contents when needed
◼ Provide space for variables local to a procedure
◼ Stack pointer
 Stores the address of the top of the stack
 $29 ($sp) in MIPS
◼ Stack operations
 push: place data on stack (sw in MIPS), decrease $sp by 4
 pop: remove data from stack (lw in MIPS), increment $sp by444
Stack content during procedure call

The values of the stack pointer and the stack

(a) before, (b) during, and (c)after the procedure call (pop).

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 Procedure example $a0 $a1 $a2 $a3

Need one local variable f

➔ $s0 will be used.
➔ Need to save its content first

leaf_example:

Restore
back the
content of
$s0
Return to
46
caller
Preserved and Not preserved registers
Preserved registers: Not preserved registers:
◼ Callee assume that the ◼ Callee can use them
caller may used them. directly without saving
◼ So, callee responsible to: their contents first.
 save their values before it
uses them (in stack) , and
 Restore their values before
return to caller

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Main function
◼ The main function that call leaf_example callee
 Should puts the parameter values in $a0–$a3 before calling
. . .
main:

.. .
add $a0, $s0, $0
add $a1, $s1, $0 Pass parameters values exist
add $a2, $s2, $0 in ($s0 -- $s3) to arguments
add $a3, $s3, $0 registers ( $a0 -- $a3)

jal leaf_example Call procedure leaf_example

add $s0, $v0, $0 Receive return values exist in
. . . ($v0) to saved registers ( $s0)

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 Procedure frame
◼ Each procedure is associated with a procedure
frame or activation record
◼ Each frame has a frame pointer: $fp ($30)
main {
…
proc1
…}
proc1 {
…
proc2
…}
proc2 {
…
proc3
…}
The frame pointer does not change during procedure execution, unlike the stack
pointer – although can use $sp with a little extra math 49
Procedures
◼ Example C code:

// procedure adds 10 to input parameter

int main()
{ int i, j;
i = 5;
j = add10(i);
i = j;
return 0;}

int add10(int i)
{ return (i + 10);}
 Procedures
◼ Translated MIPS assembly
◼ Note more efficient use of registers possible! save register
.text in stack
.globl main add10:
addi $sp, $sp, -4
main: sw $s0, 0($sp)
addi $s0, $0, 5
add $a0, $s0, $0 addi $s0, $a0, 10
argument add $v0, $s0, $0
result
to callee jal add10 to caller
control returns here
jump and link restore lw $s0, 0($sp)
add $s1, $v0, $0 values addi $sp, $sp, 4
add $s0, $s1, $0
return jr $ra
li $v0, 10 system code
MEMORY High address
syscall & call to
exit $sp
Content of $s0
Low address
◼ See more examples Sec. 2.13 Sort example

52
Global pointer
◼ A C variable is generally a location in storage, and its
interpretation depends both on its type and storage
class.
 Type: integers, characters,...
 Storage classes: automatic and static.
◼ Automatic variables:
 are local to a procedure and are discarded when the procedure
exits.
◼ Static variables:
 exist across exits from and entries to procedures.
 variables declared outside all procedures
◼ To simplify access to static data, MIPS software
reserves another register, called the global pointer, or
$gp. 53
MIPS memory allocation

Also called heap

Store dynamic Data structure,
like linked list

Static var., Global var., arrays

Machine code of programs

Reserved for OS

54
MIPS register conventions

Register 1, called $at, is reserved for the assembler, and

registers 26–27, called $k0–$k1, are reserved for the operating system. 55
MIPS addressing Modes
◼ In immediate addressing the address is simply an immediate value
in the instruction:
addi $t0,$t0,4 # add value 4 to $t0
◼ In register addressing the address is simply the value in a register:
lw $t0, ($s3) # use value in $s3 as address
◼ In base and displacement addressing the address is the sum of an
immediate and the value in a register:
lw $t0, 100($s3) # address is $s3 + 100
◼ PC-relative addressing, where the branch address is the sum of the
PC and a constant in the instruction
beq $t0, $t1, 5 #address is (PC+4) + (4 * 5)
◼ Pseudodirect addressing, where the jump address is the 26 bits of
the instruction concatenated with the upper bits of the PC
j 20000 # address is PC|| (20000*4)

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Pseudo-instructions
◼ The assembler can also treat common variations of
machine language instructions as if they were
instructions in their own right.
◼ The hardware need not implement these instructions;
however, their appearance in assembly language
simplifies translation and programming. Such
instructions are called pseudoinstructions.
◼ Thus the MIPS assembler accepts this instruction even
though it is not found in the MIPS architecture:
move $t0,$t1 # register $t0 gets register $t1
◼ The assembler converts this assembly language
instruction into the machine language equivalent of the
following instruction:
add $t0,$zero,$t1 # register $t0 gets 0 + register $t1 57
◼ The pseudoinstructions give MIPS a richer set of
assembly language instructions than those implemented
by the hardware
◼ The MIPS pseudoinstructions:
 blt (branch on less than) into the two instructions slt and bne
 bgt, bge, and ble. It also converts branches to faraway
locations into a branch and jump.
◼ If you are going to write assembly programs, use
pseudoinstructions to simplify your task.
◼ To understand the MIPS architecture and be sure to get
best performance, however, study the real MIPS
instructions found in Figures 2.1 and 2.19.

58
59
MIPS instructions (in decimal numbers)

opcode rs rt rd shamt Funct Address

add 0 reg reg reg 0 3210 n.a.

sub 0 reg reg reg 0 3410 n.a.

Slt 0 reg reg reg 0 4210 n.a.
addi 810 reg reg n.a. n.a. n.a. const.

lw 3510 reg reg n.a. n.a. n.a. addr.

sw 4310 reg reg n.a. n.a. n.a. addr.

beq 410 reg reg n.a. n.a. n.a. addr.

bne 510 reg reg n.a. n.a. n.a. addr.

j (jump) 210 n.a. n.a. n.a. n.a. n.a. addr.

jal 310 n.a. n.a. n.a. n.a. n.a. addr.

60
MIPS assembly language

61
MIPS assembly language (Cont.)

62