Aoc Unit-1
Aoc Unit-1
Aoc Unit-1
Subject Department of
Computer Application
05BC2102
Architectural Organization of Subject:
Architectural
Computers Organization of
Computers
Unit#1
Asst. Prof. Sheth Niraj
Unit#1 Digital Logic Circuits:
Syllabus
● “Computer System
Architecture”, M. Morris
Books Mano, Pearson Publication,
Third Edition.
● Digital Computers
● Logic Gates
● LAPTOP
Digital ● DESKTOP
Computers ● MOBILE
● PALMTOP
Digital • Step 3: Repeat the above steps until you get 0 as the
Computers quotient.
• Step 4: Now, write the remainders in such a way that the
last remainder is written first, followed by the rest in the
reverse order.
• This number is the binary value of the given decimal
number.
Faculty of Computer Application 12
Unit#1 Digital Logic Circuits:
Decimal to
● Convert 356 decimal to binary
binary
Number Remainder
2 356
2 178 0
2 89 0 ● Writing from
bottom to top
2 44 1
Decimal to we get
2 22 0
binary 2 11 0 ● (101100100)2
2 5 1
2 2 1
2 1 0
2 0 1
Binary to
● Convert 11010101 to decimal
decimal
Binary to
1x128 + 1x64 + 0 + 1x16 + 0 + 1x4 + 0 + 1x1
decimal
128+64+0+16+0+4+0+1 = 213
Digital
Computers
● Input
Digital • And then, transmit the converted data into the main
Computers memory of the computer. The sole purpose is to
connect the user and the computer. In addition, this
creates easy communication between them.
● Memory Unit
● Output
● Digital Computers
● Logic Gates
Logic Gates
Logic Gates ● An AND gate’s symbol and truth table are as follows:
A B A.B
0 0 0
0 1 0
1 0 0
Department of Computer Application 1 1 1 30
Unit#1 Digital Logic Circuits:
Number of possible combination depend upon the
variable so if n input are there then 2n possible
combination possible
So if 3 variable are there then 23 = 8 possibility
A B C
Logic Gates 0 0 0
AND gate 0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
Department of Computer Application
1 1 1 31
Unit#1 Digital Logic Circuits:
Logic Gates
AND gate
Logic Gates
OR gate
Logic Gates
NAND gate
Logic Gates
NOR gate
Logic Gates
Ex-OR gate
Logic Gates
Ex-NOR gate
Logic Gates
Logic Gates
● ( (A . B + C’) . D)’
Logic Diagram
● ( A’ . ( A + B) ) + (A + B)
Logic Diagram
● Digital Computers
● Logic Gates
● Boolean Laws
1) Commutative law
Boolean
● Any binary operation which satisfies the following
Algebra expression is referred to as commutative operation.
2) Associative law
● This law states that the order in which the logic
operations are performed is irrelevant as their effect
Boolean is the same.
Algebra
3) Distributive law
● Distributive law states the following condition.
4) AND law
● These laws use the AND operation. Therefore they
are called as AND laws.
Boolean
Algebra 5) OR law
● These laws use the OR operation. Therefore they are
called as OR laws.
6) INVERSION law
● This law uses the NOT operation. The inversion law
states that double inversion of a variable results in
the original variable itself.
Boolean
Algebra
● DE MORGAN’S LAW
Algebra ● Theorem 1
● Theorem 2
Boolean
Algebra
Boolean
Algebra
Boolean
Algebra
Boolean
Algebra
● BC+BC´+BA=B
Boolean ● (A+C)(AD+AD´)+AC+C=A+C
Algebra ● A´(A+B)+(B+AA)(A+B´)=A+B
● A+A´B+A´B´C+A´B´C´D+A´B´C´D´E=A+B+C+D+E
● BC+BC´+BA
● B(C + C’ + A)
Boolean
● B(1 + A) (C+ C’=1)
Algebra
● B(1) (1+A=1)
● B
● Digital Computers
● Logic Gates
Maurice Karnaugh
● Karnaugh is an
American physicist,
mathematician and
inventor.
Map
Simplification ● Karnaugh worked at
Bell Labs (1952-66),
developing the
Karnaugh map
(1954)
● The K-map grid is filled using 0's and 1's. The K-map is solved by
making groups. There are the following steps used to solve the
expressions using K-map:
1. First, we find the K-map as per the number of variables.
2. Find the maxterm and minterm in the given expression.
Map 3. Fill cells of K-map for SOP with 1 respective to the minterms.
Simplification 4. Fill cells of the block for POS with 0 respective to the maxterm.
5. Next, we create rectangular groups that contain total terms in the
power of two like 2, 4, 8, … and try to cover as many elements as we
can in one group.
6. With the help of these groups, we find the product terms and sum
them up for the SOP form.
Map
Simplification
● 2 variable k map
Map
A B
Simplification
0 0
0 1
1 0
1 1
x y
0 0
0 1
Map 1 0
Simplification 1 1
A B C
0 0 0
Map
0 0 1
Simplification 0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Department of Computer Application 73
Unit#1 Digital Logic Circuits:
A B C
0 0 0
0 0 1
0 1 0
Map 0 1 1
Simplification 1 0 0
1 0 1
1 1 0
1 1 1
Map
Simplification
Map
Simplification
● Group can be overlap.
Map
Simplification
Map
Simplification
Map
Simplification
X Y Z MINTERM SYMBOL
0 0 0 X’.Y’.Z’ m0
Map 0 0 1 X’.Y’.Z m1
Simplification 0 1 0 X’.Y.Z’ m2
0 1 1 X’.Y.Z m3
1 0 0 X.Y’.Z’ m4
1 0 1 X.Y’.Z m5
1 1 0 X.Y.Z’ m6
1 1 1 X.Y.Z m7
Department of Computer Application 84
Unit#1 Digital Logic Circuits:
● Sum Of Product Simplification
X Y Z MINTERM SYMBOL
0 0 0 X+Y+Z M0
Map 0 0 1 X+Y+Z’ M1
Simplification 0 1 0 X+Y’+Z M2
0 1 1 X+Y’+Z’ M3
1 0 0 X’+Y+Z M4
1 0 1 X’+Y+Z’ M5
1 1 0 X’+Y’+Z M6
1 1 1 X’+Y’+Z’ M7
Department of Computer Application 86
Unit#1 Digital Logic Circuits:
● Product Of Sum Simplification
Map
Simplification
● Digital Computers
● Logic Gates
● BLOCK DIAGRAM
Combinational
Circuits
Block diagram
HALF ADDER
Truth Table
INPUT OUTPUT
X Y SUM CARRY
HALF ADDER 0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Logical Expression:
For Sum:
HALF ADDER
Sum = A XOR B
For Carry:
HALF ADDER
Carry = A AND B
Implementation:
HALF ADDER
Block diagram
FULL ADDER
FULL ADDER
FULL ADDER
FULL ADDER
● Digital Computers
● Logic Gates
● Digital Computers
● Logic Gates
S R OUTPUT Q
RS Flip-Flops 0 0 No Change
0 1 Reset
1 0 Set
1 1 Invalid
RS Flip-Flops
D Flip-Flops
J K OUTPUT Q
JK Flip-Flops 0 0 No Change
0 1 Clear
1 0 Set to 1
1 1 Q(t)’ – complement
JK Flip-Flops
Clk T OUTPUT Q
T Flip-Flops 0
0
0
1
NO CHANGE
NO CHANGE
1 0 1 (Q’)
1 1 0 (Q)
T Flip-Flops
THANK YOU