A Multi-Loop Low-Dropout FVF Voltage Regulator

with Enhanced Load Regulation

(Invited Paper)

Mahender Manda, Sri Harsh Pakala, and Paul M. Furth

VLSI Laboratory, Klipsch School of Electrical and Computer Engineering,
New Mexico State University, Las Cruces, NM 88003, USA
Email: {mahender, sriharsh, and pfurth}@nmsu.edu

Abstract—-This paper introduces a multi-loop fast transient s

response flipped voltage follower (FVF) low-dropout (LDO) sZ&
voltage regulator suitable for system-on-chip (SOC) applications. 9* DW^^
Dϲ
While typical FVF-based LDOs exhibit fast transient response, ($

which is critical for SOC applications, their output DC accuracy

is limited due to low loop gain of the FVF. In this work,
sD/Z sKhd
we introduce a multi-loop design aimed at improving the DC
accuracy while preserving the transient performance. The LDO Dϳ s^d Dϴ
is implemented in a 180-nm CMOS process to provide an output
voltage of 1.5V at a maximum load current of 10mA from  5/ &/
an input line voltage of 1.8V. The designed LDO’s quiescent
current is 53μA at minimum load. Simulation results showcase
the advantages of the multi-loop design with a transient response s^^ (UURU $PSOLILHU 96(7 *HQHUDWLRQ )9)
time of 0.73ns and a figure of merit (FOM) of 3.9ps. Fig. 1: Single-transistor-control FVF LDO adapted from [5].
Index Terms—flipped voltage follower, folded flipped voltage
follower, FVF, LDO, capacitor-less LDOs, SOC, low dropout, M7 − M8 . An FVF stage is used at the output of the LDO to
voltage regulators. improve transient response.
However, due to low loop gain of the FVF [8], the LDO
I. I NTRODUCTION has substandard load regulation. Poor load regulation is also
because VOU T is not tightly bound to VREF .
With the increase in demand for portable electronics, Another major drawback of [5] is the limitation on mini-
system-on-chip’s (SOCs) with increased complexity have be- mum and maximum load current [9]. If the load is less than the
come widely prevalent. SOCs require several circuit blocks to minimum, the gate voltage of Mpass increases to reduce the
implement a complete system. While incorporating different overdrive voltage. This pushes M8 out of saturation, which
circuit blocks on a single chip, voltage regulators which is undesirable for proper functioning of LDO. At high load
require minimal area are essential for providing clean ripple- currents the output dominant pole is in proximity with the
free supply rails across the integrated circuit [1], [2]. Fully- internal non-dominant pole, leading to poor phase margin.
integrated low-dropout (LDO) voltage regulators are specif- Another FVF implementation is done in [8], It consists of
ically used in such circumstances [3], [4]. Among many a triple-input error amplifier to improve load regulation and
existing topologies, fully-integrated flipped voltage follower also employs Buffer Impedance Attenuation (BIA) technique
(FVF) based LDOs are an attractive topological choice due to move the internal poles to high frequency, away from the
to their low output impedance, fast transient characteristic and output pole [8].
minimal area requirements for implementing regulators for on- Despite the use of a triple-input error amplifier, the loop gain
chip applications [5]–[7]. for the regulating loop in [8] is low, resulting in deficient load
A single-transistor-control FVF based LDO adapted from regulation. Our proposed design enhances the load regulation
[5] is shown in Fig. 1. The LDO consists of an error amplifier by introducing another loop. While the LDO in [8] has a single
(EA), a VSET generation stage and an FVF output stage. compensation capacitor CB , another compensation network is
Voltage VM IR is regulated by the error amplifier in order to set introduced in the proposed design to make the LDO stable.
VM IR equal to VREF . The VSET generation stage forms the This also results in reducing the disturbance on VOU T during
bridge in between VM IR and VOU T . VSET is held one VSG a load transient.
below VM IR by diode connected transistor M7 . The generated This paper is organized as follows: Section II describes
VSET is used to bias transistor M8 in the FVF stage. From Fig. implementation details of proposed multi-loop LDO. Section
1 it can be observed that VM IR and VOU T are approximately III presents simulated results. Conclusion and comparison with
equal due to the floating current mirror formed by transistors literature are discussed in Section IV.

978-1-5090-6389-5/17/$31.00 ©2017 IEEE 9

 II. I MPLEMENTATION OF P ROPOSED LDO to enhance the load regulation through the negative feedback
of Loop 4.
The proposed multi-loop LDO is an enhanced version of the Fig. 3 depicts the schematic of the proposed LDO. Transis-
work presented in [8]. The LDO in [8] was implemented in tors M1 -M5 form the triple-input NMOS differential amplifier.
a 65-nm CMOS process. However, in this work we selected Transistor M3 forms the third input for the error amplifier,
a low-cost 180-nm process. In order to scale the design to allowing to feedback VOU T , thereby enhancing DC accuracy.
a different process node, a scaling factor of the ratio of the Feedback from VM IR to transistor M2 forms Loop 2, as
maximum supply voltage of 180-nm core devices to those of described above. Control voltage VSET required for the output
65-nm core devices is chosen. FVF stage is generated using transistors M6 , M7 and M15 .
VSET generated through the diode-connection of transistor M7
s is used to bias M8 in the output FVF stage. A compensation
sZ& capacitor CB is required to ensure stability of the FVF
s DW^^
($
($
Dϲ s' LDO [8]. The BIA technique is implemented using an FFVF
Z
due to its extremely low output impedance compared to a
/RRS 
/RRS 
sD/Z sKhd regular voltage buffer [8], [10]. An FFVF buffer is constructed
/RRS 
/RRS  using transistors M9 -M13 . Introducing an FFVF reduces the
Dϳ s^d
resistance at the gate of MP ASS and the capacitance at node
Dϴ

VA , moving the poles at both VG and VA away from the output
Z> >
s dominant pole [8].
However in the 180-nm process, higher parasitics result in
s^^ (UURU $PSOLILHU (UURU $PSOLILHU 96(7 *HQHUDWLRQ %XIIHUHG )9)
an unacceptably low phase margin (PM) of Loop 1. Therefore,
Fig. 2: Block diagram of proposed multi-loop FVF LDO.
a compensation network ZC formed by resistor RC and
capacitor CC is used to improve the PM of Loop 1. To
Fig. 2 presents the block diagram of the proposed LDO. further supplement the speed of the buffered FVF stage, the
Loop 1 consists of a Folded Flipped Voltage Follower (FFVF) parasitic capacitance associated with it is reduced by doubling
driving an output FVF stage. Loop 1 by itself can regulate the the effective length of bias transistors M17 -M19 , such that
output voltage but exhibits poor load regulation owing to its size of transistors M11 , M12 and M14 can be halved for the
low loop gain. The low output impedance of the FVF stage same bias current. The FVF LDO’s pass element is a PMOS
provides a high unity gain frequency (UGF) for Loop 1 [10]. transistor MP ASS .
This enables it to react immediately to changes in the load [8] derives the relationship between its VREF and VOU T
current. Loop 2 consists of an error amplifier (EA1) and is based on the input transistor sizing of the triple-input differ-
predominantly used to set a left-half-plane (LHP) zero which ential amplifier and is given by
aids in the stabilization of the LDO. Another function of Loop  
1 3
2 is generation of voltage VSET . [8] describes that sufficient VREF − · VM IR − · VOU T · AEA = VOU T (1)
DC accuracy of the LDO is achieved through the introduction 4 4
of Loop 3. Loop 3 enhances the DC accuracy through the where VM IR = VOU T + Δ V . From (1) we find that, VOU T =
connection of VOU T to one input of the error amplifier (EA1). VREF − Δ V /4. This states that, VOU T is held close to VREF
The proposed work introduces a second error amplifier (EA2) than to VM IR .

s
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s Dϲ
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s ϰ ͗ ϭ ͗ϯ 9287
9287
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Dϭ DϮ Dϯ Dϳ s^d Dϴ
//^
Z
5/ &/
 s
s
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s^^ %LDVLQJ DQG (UURU $PSOLILHU (UURU $PSOLILHU 96(7 JHQHUDWLRQ %XIIHUHG )9)
Fig. 3: Architecture of proposed multi-loop FVF LDO.

10
 Though VOU T is regulated approximately equal to VREF , The complete AC analysis summary is presented in Table I.
the low loop gain through Loop 3 limits the load regulation Loop 1 exhibits the highest UGF of 180MHz, and the lowest
that can be achieved through the architecture shown in [8]. PM of 26◦ . For Loop 2, a gain of approximately 52dB is
To further enhance the DC accuracy, a second error amplifier achieved along with a phase margin of 82◦ . Loop 3’s gain is
(EA2) is introduced, as shown in Fig. 3. Node VOU T is fed reduced due to the presence of Loop 2 resulting in a low loop
back to the negative terminal of EA2 to form Loop 4 through gain of 1.20dB, as shown in Table I. Finally, the introduced
the connection of node VB to the gate of transistor M1 . Loop 4’s gain is equal to 32dB with a PM of 86◦ .
An integrating capacitor CR is required to stabilize Loop 4.
The negative feedback action results in the modulation of the Loop Loop gain (dB) UGF (MHz) PM (◦ ) Comments
internal reference VB to further improve regulation. 1 26.5 180.5 26 DC at VSET
2 51.9 31.4 82.18 Open: Loops 3, 4
III. S IMULATION R ESULTS 3 1.20 1.24 86.4 Open: Loop 4
4 32 0.38 86.31 -
The proposed multi-loop FVF LDO is designed in a 180-
nm CMOS process. The supply voltage of the implemented TABLE I: Summary of AC analysis of individual loops at load current of 10 mA.
LDO is 1.8V. The LDO is designed to provide a regulated
output voltage of 1.5V across a load current range of 0μA - 30
10mA. The LDO consumes a total quiescent current of 93μA
20
at maximum loading conditions. At maximum load current the

Gain (dB)
10
simulated dropout voltage is 225mV.
0

A. AC Stability Analysis
10

AC small-signal analysis is performed on the proposed 0

Phase (Degrees)
multi-loop LDO to verify its stability across the complete load Without ZC
range.
100 With ZC

200
s
sZ& 3 4 5 6 7 8 9
10 10 10 10 10 10 10
s DW^^ Frequency (Hz)
($ Dϲ s'
($ Fig. 5: Magnitude and Phase response of Loop 1 with and without compensation network
Z
ZC .
/RRS 
/RRS 
sD/Z sKhd B. Transient Analysis
/RRS 
/RRS  The implemented LDO’s transient performance is charac-
Dϳ s^d Dϴ terized through a load transient simulation. A load transient

s
Z> > step of 0μA to 10mA is provided at the output node VOU T
of the LDO with a rise time of 10ns. The response of the
s^^ (UURU $PSOLILHU (UURU $PSOLILHU 96(7 *HQHUDWLRQ %XIIHUHG )9)
LDO is measured in terms of ΔVOU T , recovery time TR , and
Fig. 4: Break points of individual loops for AC analysis. load regulation. The LDO’s load transient response is shown
in Fig. 6. The proposed LDO achieves a transient response
In order to accurately deduce the magnitude and phase time (TR ) of 0.73ns, while exhibiting a DC load regulation of
response of individual loops, each loop is broken as shown 0.031mV/mA.
in Fig. 4. For simulating the AC response of Loop 1, it is
required to break the loop at node VA , as shown in Fig. 4. 10
Load Current (mA)

8
In order to accurately observe the effect of node parasitics, a 6
parasitic loading stage is also required [5]. Another important 4

point to note is the requirement to isolate the effects of other 2

0
loops on Loop 1. Therefore to establish the DC operating point
of transistor M8 , node VSET is also considered as a break 1.55

point for Loop 1. As such, a DC voltage source can be used

50mV/Div

to establish operating conditions for transistor M8 . Now, Loop

1.5

2 is broken at node VM IR while performing AC analysis to 1.45

verify the stability of Loop 2. For Loop 3, the loop’s break 2 2.5 3 3.5
Time(
s)
point is at node VOU T . Finally the newly-introduced Loop Fig. 6: Load transient response of proposed multi-loop LDO.
4 is broken at node VB . The magnitude and phase response
of Loop 1 are shown in Fig. 5. We note that without the
compensation network ZC , Loop 1’s phase margin is 6◦ . With IV. D ISCUSSION AND C ONCLUSION
the introduction of compensation network ZC , at node VD as A multi-loop FVF LDO is proposed with improved load
shown in Fig. 3, Loop 1’s phase margin improves to 26◦ . regulation. A DC regulation loop (Loop 4) is introduced to

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 Publication [11] JSSC 2005 [12] JSSC 2012 [1] TCAS-I 2014 [7] TCAS-I 2014 [8] TCAS-I 2015 [13] EL. 2016 This Work
CL On-chip
Technology 90-nm 45-nm SOI 0.35μm 65-nm 65-nm 28-nm 180-nm
Vout 0.9V 0.9 to 1.1V 1.2V 1V 1V 0.8V 1.5V
Drop out 300mV 85mV 600mV 200mV 150mV 200mV 225mV*
IQ 6mA 12mA 44μA 23.7μA 50 to 90μA 100μA 53 to 93μA
Imax 100mA 42mA 12mA 50mA 10mA 10mA 10mA
Total Cap. 600pF 1.46nF 100pF 27pF 140pF 120pF 153pF
Δ VOU T @TEDGE 90mV@100ps N/A 105mV@500ns 40mV@100ns* 82mV@200ps 26mV@30ps 48mV@10ns
DC Line Reg. 882mV/V** 27mV/V** 0.28mV/V 8.89mV/V 37.1mV/V NA 24mV/V*
DC Load Reg. 0.9mV/mA 0.083mV/mA 0.68mV/mA 0.034mV/mA 1.1mV/mA NA 0.031mV/mA*
TR 0.54ns 0.309ns* N/A N/A 1.15ns 312ps 0.73ns*
FOM 32ps 62.4ps* N/A N/A 5.74ps 3.12ps 3.9ps*

TABLE II: Summary and Comparison of simulated results with the state-of-the-art LDOs.
* Simulated Results. ** Estimated from figure.

improve steady state output regulation of the FVF LDO. The [5] T. Y. Man, K. N. Leung, C. Y. Leung, P. K. T. Mok, and M. Chan,
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ture, widely used TR and figure-of-merit (FOM) are adopted [7] X. L. Tan, K. C. Koay, S. S. Chong, and P. K. Chan, “A fvf ldo
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C · Δ VOU T Systems I: Regular Papers, vol. 61, no. 5, pp. 1304–1312, May 2014.
TR = (2) [8] Y. Lu, Y. Wang, Q. Pan, W. H. Ki, and C. P. Yue, “A Fully-Integrated
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IM AX Furth, “Voltage buffer compensation using flipped voltage follower in
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