NE/SA/SE555/SE555C Timer: Description Pin Configurations
NE/SA/SE555/SE555C Timer: Description Pin Configurations
NE/SA/SE555/SE555C Timer: Description Pin Configurations
Product specification
Timer
NE/SA/SE555/SE555C
DESCRIPTION
The 555 monolithic timing circuit is a highly stable controller capable of producing accurate time delays, or oscillation. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200mA.
PIN CONFIGURATIONS
D, N, FE Packages
GND 1 TRIGGER 2 OUTPUT 3 RESET 4 8 7 6 5
FEATURES
F Package
GND 1 NC 2 TRIGGER 3 OUTPUT 4 NC 5 RESET 6 NC 7 14 13 12 11 10 9 8 VCC NC DISCHARGE NC THRESHOLD NC CONTROL VOLTAGE
Turn-off time less than 2s Max. operating frequency greater than 500kHz Timing from microseconds to hours Operates in both astable and monostable modes High output current Adjustable duty cycle TTL compatible Temperature stability of 0.005% per C
APPLICATIONS
TOP VIEW
Precision timing Pulse generation Sequential timing Time delay generation Pulse width modulation
ORDERING INFORMATION
DESCRIPTION 8-Pin Plastic Small Outline (SO) Package 8-Pin Plastic Dual In-Line Package (DIP) 8-Pin Plastic Dual In-Line Package (DIP) 8-Pin Plastic Small Outline (SO) Package 8-Pin Hermetic Ceramic Dual In-Line Package (CERDIP) 8-Pin Plastic Dual In-Line Package (DIP) 14-Pin Plastic Dual In-Line Package (DIP) 8-Pin Hermetic Cerdip 14-Pin Ceramic Dual In-Line Package (CERDIP) 14-Pin Ceramic Dual In-Line Package (CERDIP) 14-Pin Ceramic Dual In-Line Package (CERDIP) TEMPERATURE RANGE 0 to +70C 0 to +70C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -55C to +125C -55C to +125C 0 to +70C -55C to +125C -55C to +125C ORDER CODE NE555D NE555N SA555N SA555D SE555CFE SE555CN SE555N SE555FE NE555F SE555F SE555CF 0581B 0581B 0581B 0404B 0405B DWG # 0174C 0404B 0404B 0174C
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853-0036 13721
Product specification
Timer
NE/SA/SE555/SE555C
BLOCK DIAGRAM
VCC 8
R THRESHOLD 6
CONTROL VOLTAGE 5
COMPARATOR
R TRIGGER COMPARATOR R 2
RESET 4
OUTPUT STAGE
3 OUTPUT GND
EQUIVALENT SCHEMATIC
FM CONTROL VOLTAGE VCC R1 4.7K R2 330 R3 4.7 K R 4 1 K Q9 Q22 Q8 Q19 R13 3.9K R 7 5 K R12 6.8K
Q21 Q5 Q6 Q7
Q1 THRESHOLD Q2 Q3
Q4
OUTPUT Q23 B
R5 10 K Q10 TRIGGER Q25 RESET DISCHARGE Q14 GND R16 100 R6 100K
R8 5K
Q15 R9 5K
NOTE:
347
Product specification
Timer
NE/SA/SE555/SE555C
NOTES: 1. The junction temperature must be kept below 125C for the D package and below 150C for the FE, N and F packages. At ambient temperatures above 25C, where this limit would be derated by the following factors: D package 160C/W FE package 150C/W N package 100C/W F package 105C/W
348
Product specification
Timer
NE/SA/SE555/SE555C
NOTES: 1. Supply current when output high typically 1mA less. 2. Tested at VCC=5V and VCC=15V. 3. This will determine the max value of RA+RB, for 15V operation, the max total R=10M, and for 5V operation, the max. total R=3.4M. 4. Specified with trigger input high. 5. Time measured from a positive going input pulse from 0 to 0.8VCC into the threshold to the drop from high to low of the output. Trigger is tied to threshold.
349
Product specification
Timer
NE/SA/SE555/SE555C
+125oC
TEMPERATURE oC
-55oC
0.1 +25oC
+25oC 55oC
ISINK mA
ISINK mA
ISINK mA
PROPAGATION DELAY ns
+25oC +70oC
10
15
20
0.1
0.2
0.3
0.4
ISOURCE mA
SUPPLY VOLTAGE V
350
Product specification
Timer
NE/SA/SE555/SE555C
TYPICAL APPLICATIONS
VCC
COMP
FLIP FLOP
3 OUTPUT OUTPUT
2 TRIGGER
COMP
C 4 RESET
f+
1.49 (R A ) 2R B)C
Astable Operation
VCC
COMP
| t |
FLIP FLOP
3 OUTPUT OUTPUT
2 TRIGGER
COMP
1 * V 3 CC
4 RESET
T = 1.1RC
Monostable Operation
351
Product specification
Timer
NE/SA/SE555/SE555C
TYPICAL APPLICATIONS
.001F
Another consideration is the turn-off time. This is the measurement of the amount of time required after the threshold reaches 2/3 VCC to turn the output low. To explain further, Q1 at the threshold input turns on after reaching 2/3 VCC, which then turns on Q5, which turns on Q6. Current from Q6 turns on Q16 which turns Q17 off. This allows current from Q19 to turn on Q20 and Q24 to given an output low. These steps cause the 2s max. delay as stated in the data sheet. Also, a delay comparable to the turn-off time is the trigger release time. When the trigger is low, Q10 is on and turns on Q11 which turns on Q15. Q15 turns off Q16 and allows Q17 to turn on. This turns off current to Q20 and Q24, which results in output high. When the trigger is released, Q10 and Q11 shut off, Q15 turns off, Q16 turns on and the circuit then follows the same path and time delay explained as turn off time. This trigger release time is very important in designing the trigger pulse width so as not to interfere with the output signal as explained previously.
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