3554

Wideband, Fast-Settling OPERATIONAL AMPLIFIER

FEATURES
G SLEW RATE: 1000Vs G FAST SETTLING: 150ns, max (to 0.05%) G GAIN-BANDWIDTH PRODUCT, 1.7GHz G FULL DIFFERENTIAL INPUT

APPLICATIONS
G PULSE AMPLIFIERS G TEST EQUIPMENT G WAVEFORM GENERATORS G FAST D/A CONVERTERS

DESCRIPTION
The 3554 is a full differential input, wideband operational amplifier. It is designed specifically for the amplification or conditioning of wideband data signals and fast pulses. It features an unbeatable combination of gain-bandwidth product, settling time and slew rate. It uses hybrid construction. On the beryllia substrate are matched input FETs, thin-film resistors and high speed silicon dice. Active laser trimming and complete testing provide superior performance at a very moderate price. The 3554 has a slew rate of 1000V/s and will output 10V and 100mA. When used as a fast settling amplifier, the 3554 will settle to 0.05% of the final value within 150ns. A single external compensation capacitor allows the user to optimize the bandwidth, slew rate or settling time in the particular application. The 3554 is reliable and rugged, and addresses almost any application when speed and bandwidth are serious considerations. It is particularly a good choice for use in fast settling circuits, fast D/A converters, multiplexer buffers, comparators, waveform generators, integrators, and fast current amplifiers. It is available in several grades to allow selection of just the performance required.
2 +VS Bal. 8 4 Bal.

3 Freq. Cont.

5 In 1 Out

4 +In

7 VS

International Airport Industrial Park Mailing Address: PO Box 11400 Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP

Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd. Tucson, AZ 85706 Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132 PDS-331C Printed in U.S.A. October, 1993

1983 Burr-Brown Corporation

SPECIFICATIONS
ELECTRICAL
At TCASE = +25C and 15VDC, unless otherwise noted. 3554AM PARAMETER INPUT OPEN-LOOP GAIN, DC No Load Rated Load RATED OUTPUT Voltage Current Output Resistance, Open-Loop DYNAMIC RESPONSE Bandwidth (0dB, small signal) Gain-bandwidth Product 100 90 10 100 106 96 11 125 20 90 225 725 1700 19 1200 60 120 140 200 0.5 20 80 0 10
(1)

3554BM MAX MIN TYP MAX MIN

3554SM TYP MAX UNITS

CONDITIONS

MIN

TYP

RL = 100 IO = 100mA VO = 10V f = 10MHz CF = 0 CF = 0, G = 10V/V CF = 0, G = 100V/V CF = 0, G = 1000V/V CF = 0, VO = 20Vp-p, RL = 100 CF = 0, VO = 20Vp-p, RL = 100 A=1 A=1 A=1 A=1

* * * *

* * * * * * * * * * * * * * * 0.2 8 *

* * * *

* * * * * * * * * * * * * * * 0.2 12 *

dB dB V mA MHz MHz MHZ MHz MHz V/s ns ns ns ns mV V/C V/C V/V pA pA/V * pA || pF || pF nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz Vp-p Vrms fA p-p pA rms V dB V VDC VDC mA C C C C/W C/W

Full Power Bandwidth Slew Rate Settling Time: to 1% to 0.1% to 0.05% to 0.01% INPUT OFFSET VOLTAGE Input Offset, TA = 25C vs Temp (TA = 25C to +85C) vs Temp (TA = 55C to +125C) vs Supply Voltage INPUT BIAS CURRENT Input Bias, 25C vs Temp vs Supply Voltage INPUT DIFFERENCE CURRENT Initial Difference, 25C INPUT IMPEDANCE Differential Common-Mode INPUT NOISE Voltage, fO = 1Hz fO = 10Hz fO = 100kHz fO = 1kHz fO = 10kHz fO = 100kHz fO = 1MHz fB = 0.3Hz to 10Hz fB = 10Hz to 1MHz Current, fB = 0.3Hz to 10Hz fB = 10Hz to 1MHz INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Maximum Safe Input Voltage POWER SUPPLY Rated Voltage Voltage Range, Derated Performance Current, Quiescent TEMPERATURE RANGE Specification Operating, Derated Performance Storage Junction-Case Junction-Ambient

70 150 425 1000 16 1000

* * * * * *

* * * * * *

150 250 2 50 300 50 *

* * 1 15 * * *

* * 1 25 * *

1 2 1011|| 2 1011|| 2 RS = 100 RS = 100 RS = 100 RS = 100 RS = 100 RS = 100 RS = 100 RS = 100 RS = 100 RS = 100 RS = 100 Linear Operation f = DC, VCM = +7V, 10V 125 50 25 15 10 8 7 2 8 45 2 (|VCC|4) 78 Supply 15 35 10

* * * * * * * * * * * * * * * * * * * * *

* * * * * * * * * * * * * * * * * * * * *

44

5 17 Ambient Temperature Ambient Temperature Ambient Temperature Ambient Temperature Ambient Tempterature 25 55 65

18 45 +85 +125 +150

* * 25 55 65

* * +85 +125 +150

* * 55 55 65

* * +125 +125 +150

15 45

15 45

15 45

* Specifications same as for 3554AM.

NOTE: (1) Doubles every +10C.

3554

AMPLIFIER CONNECTIONS
1k

ABSOLUTE MAXIMUM RATINGS

Power Supply Voltage ........................................................................ 18V Input Voltage ........................................................................................ VS Output Short Circuit (to ground) ........................................................... 10s Operating Temperature ................................................... 55C to +125C Storage Temperature ...................................................... 65C to +150C Junction Temperature .................................................................... +165C Lead Temperature (soldering, 10s) ................................................ +300C
eO

100 5 270pF 6 ei 50 3 3554 8

(4)

CF 5pF 1
(4)

27

1000pF

Gain = +1V/V(1)

ORDERING INFORMATION
MODEL 3554AM 3554BM 3554SM PACKAGE 8-Pin Metal TO-3 8-Pin Metal TO-3 8-Pin Metal TO-3 TEMPERATURE RANGE 25C to +85C 25C to +85C 55C to +125C

PACKAGE INFORMATION(1)
PACKAGE DRAWING MODEL 3554AM 3554BM 3554SM PACKAGE 8-Pin Metal TO-3 8-Pin Metal TO-3 8-Pin Metal TO-3 NUMBER 030 030 030

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

3554

TYPICAL CIRCUITS
5.6k 5.6k 2pF CF 5 6 3 3554 8
(4)

1k

ei 50 560 47pF

100 5 270pF
5pF 1 27
(4)

CF 3 3554 8
(4)

5pF 1

27
(4)

6
eO

eO

ei 50

1000pF

1000pF

Gain = +1V/V(1)
Gain = 1V/V (1)

560

5.6k 1.2pF
(4)

R1 100 R3 3k

R2 100 R4 3k C1 1pF to 10pF

D1

D2

Error Signal

ei

CF 5 6 3 3554 8
(4)

10pF 1

27
(4)

HP 5082-2811 Hot Carrier Diodes 1pF to 15pF

eO

e i = 10V tr = tf = 45ns(3)

CF 5 6 3554 7 2 3 10pF 1

1000pF

Amplifier Output

Gain = 10V/V(1)
C3

+ C4 +VCC VCC Settling Time Test Circuit Schematic + C5 C6

100

10k

Common

C4

C3 R1 R3 R4 C1 CF

+VCC

Error Output D2 Output

D1 R2

ei 5 6 3554 1 eO
Input

1 C5

Gain =

+100V/V(2)

C6

VCC

Settling Time Test Circuit Layout View from component side. Shaded area is the pattern side conductor.

NOTES: (1) These circuits are optimized for driving large capacitive loads (to 470pF). (2) The 3554 is stable at gains of greater than 55 (CL 100pF) without any frequency compensation. (3) 45ns is optimum. Very fast rise times (10-20ns) may saturate the input stage causing less than optimum settling time performance. (4) Component may be eliminated when large capacitive loads are not being driven by the device.

3554

TYPICAL PERFORMANCE CURVES

At TC = +25C and 15VDC, unless otherwise noted.

OPEN-LOOP GAIN vs FREQUENCY 120 RL 10k 45 0 CF = 10pF CF = 0 CF = 1pF

OPEN-LOOP PHASE SHIFT vs FREQUENCY RL 10k

Open-Loop Voltage Gain (dB)

100 80 60 40 CF = 5pF 20 0 100 1k 10k 100k Frequency (Hz) 1M 10M 100M

CF = 0pF

Phase Shift (degrees)

45 CF = 5pF 90 135 180 225 100 1k 10k 100k Frequency (Hz) 1M 10M 100M CF = 10pF

VOLTAGE GAIN vs SUPPLY VOLTAGE 110 TA = 55C RL 10k

OUTPUT VOLTAGE vs OUTPUT CURRENT 40

Output Voltage (Vp-p)

Voltage Gain (dB)

100

TA = +125C TA = +25C

30

VS = 18VDC

VS = 15V DC

20

VS = 12VDC

90

10

VS = 5VDC

80 5 10 15 20 Supply Voltage (V)

0 0 50 100 Output Current (mA) 150 200

OUTPUT VOLTAGE vs FREQUENCY 60 50 RL = 100 CF = 0pF

600 500

OPEN-LOOP OUTPUT RESISTANCE vs FREQUENCY

Output Resistance ()

Output Voltage (Vp-p)

CF = 0pF 400 300 200 100 CF = 5pF 0

40 30 20 10 0 100 VS = 18VDC VS = 15VDC VS = 12VDC VS = 5VDC

1k

10k

100k 1M Frequency (Hz)

10M

100M

100

1k

10k

100k Frequency (Hz)

1M

10M

100M

3554

TYPICAL PERFORMANCE CURVES (CONT)

At TC = +25C and 15VDC, unless otherwise noted.

RECOMMENDED VALUES OF COMPENSATION CAPACITANCE vs CLOSED-LOOP GAIN 15

Compensation Capacitance, CF (pF)

SLEW RATE 1500

See typical applications circuits for compensation required for capacitance needs. 10

1200

Slew Rate (V/s)

1 10 Gain (V/V) 100 1000

900

600

300 0 0 0 5 10 15 20 25 30 CF, Capacitance (pF)

VOLTAGE FOLLOWER LARGE SIGNAL RESPONSE Inut Output RL = 100

VOLTAGE FOLLOWER TRANSIENT RESPONSE

10 5 0 5 10

500

Voltage (mV)

Voltage (V)

250 0 250 500

Inut Output RL = 100

100

200

300 Time (ns)

400

500

600

25

50

75 Time (ns)

100

125

150

FREQUENCY CHARACTERISTICS 2.0 2.0

FREQUENCY CHARACTERISTICS

1.5

1.5 Bandwidth

Relative Value

1.0

Slew Rate

Relative Value

Settling Time

1.0

Settling Time

.5

.5 Bandwidth

Slew Rate

0 55 25 5 35 65 95 125 Temperature (C)

0 5 10 15 20 Supply Voltage (V)

3554

TYPICAL PERFORMANCE CURVES (CONT)

At TC = +25C and 15VDC, unless otherwise noted.

SETTLING TIME 1500 10

SETTLING TIME vs OUTPUT VOLTAGE CHANGE 100mV(1) 5mV(1)

Output Voltage Change (V)

1250

10mV(1)

Settling Time (ns)

1000 0.05% 750 500 1% 250 0 1 10 100 1000 Closed-Loop Gain (V/V) 0.1%

0 NOTE: (1) Error band. 5 100mV(1) 10 0 100 200 Settling Time (ns) 300 10mV(1) 5mV(1)

WARMUP DRIFT 600

1200

EFFECT OF THERMAL SHOCK ON OFFSET VOLTAGE

Change in Input Offset Voltage (V)

500 400 300 200

TA = 25C

Without Heatsink

Change in Input Offset Voltage (V)

TA = +125C 1000 800 600 400 3554BM 200 0 TA = +25C Without Heatsink

3554BM 100 0 0 10 20 30 40 50 Time from Power Application (min) 60

10

20

30

40

Time from Heat Application (min)

INPUT BIAS CURRENT 1000 Normanlized Input Bias Current Normanlized Input Bias Current 100 10 1 0.1 0.01 0.001 55 25 5 35 65 95 125 Temperature (C)

INPUT BIAS CURRENT 1000 100 10 1 0.1 0.01 0.001 10 5 0 Input Voltage (V) 5 10

3554

TYPICAL PERFORMANCE CURVES (CONT)

At TC = +25C and 15VDC, unless otherwise noted.

INPUT OFFSET CURRENT 1000

Normanlized Input Offset Current

1000
Normanlized Input Bias Current

INPUT OFFSET CURRENT

100 10 1 0.1 0.01 0.001 55 25 5 35 65 95 125 Temperature (C)

100 10 1 0.1 0.01 0.001 10 5 0 Input Voltage (V) 5 10

RMS INPUT NOISE VOLTAGE(1) 1k 1k

PEAK TO PEAK INPUT NOISE VOLTAGE(1)

Input Noise Voltage (Vrms)

100

Input Noise Voltage (Vp-p)

100 IB = 1Hz 10Hz 10

IB = 10Hz 1MHz 10

1 103 104 105 106 107 108 109 Source Resistance () NOTE: (1) Includes contribution from source resistance.

1 103 104 105 106 107 108 109 Source Resistance () NOTE: (1) Includes contribution from source resistance.

TOTAL INPUT NOISE VOLTAGE(1) 100k

Total Input Noise Voltage (nVHz)
100

COMMON-MODE REJECTION

10k 1k RS = 1M 100 10 1 0.1 .01 0.1 1 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) NOTE: (1) Includes contribution from source resistance. RS = 100

Common-Mode Rejection (dB)

90 80 70 60 50 40 5 10 Common-Mode Input Voltage (V)

3554

TYPICAL PERFORMANCE CURVES (CONT)

At TC = +25C and 15VDC, unless otherwise noted.

QUIESCENT SUPPLY CURRENT 60

6

MAXIMUM POWER DISSIPATION Case 5 4 Ambient 3 2 JC = 15C/W 1 0 JA = 45C/W

Quiescent Supply Current (mA)

50 40 30 20 10 0 5 10 15 20 Supply Voltage (V) TA = +125C TA = +25C

TA = 55C

Internal Power Dissipation (W)

50

100

150

Temperature (C)

APPLICATIONS INFORMATION
WIRING PRECAUTIONS The 3554 is a wideband, high frequency operational amplifier that has a gain-bandwidth product exceeding 1GHz. The full performance capability of this amplifier will be realized by observing a few wiring precautions and high frequency techniques. Of all the wiring precautions, grounding is the most important and is described in an individual section. The mechanical circuit layout also is very important. All circuit element leads should be as short as possible. All printed circuit board conductors should be wide to provide low resistance, low inductance connections and should be as short as possible. In general, the entire physical circuit should be as small as practical. Stray capacitances should be minimized especially at high impedance nodes such as the input terminals of the amplifier. Pin 5, the inverting input, is especially sensitive and all associated connections must be short. Stray signal coupling from the output to the input or to pin 8 should be minimized. A recommended printed circuit board layout is shown with the Typical Circuits. It may also be used for test purposes as described below. When designing high frequency circuits low resistor values should be used; resistor values less than 5.6k are recommended. This practice will give the best circuit performance as the time constants formed with the circuit capacitances will not limit the performance of the amplifier. GROUNDING As with all high frequency circuits, a ground plane and good grounding techniques should be used. The ground plane should connect all areas of the pattern side of the printed

circuit board that are not otherwise used. The ground plane provides a low resistance, low inductance common return path for all signal and power returns. The ground plane also reduces stray signal pick up. An example of an adequate ground plane and good high frequency techniques is the Settling Time Test Circuit Layout shown with the Typical Circuits. Each power supply lead should be bypassed to ground as near as possible to the amplifier pins. A combination of a 1F tantalum capacitor in parallel with a 470pF ceramic capacitor is a suitable bypass. In inverting applications it is recommended that pin 6, the noninverting input, be grounded rather than being connected to a bias current compensating resistor. This assures a good signal ground at the noninverting input. A slight offset error will result, however, because the resistor values normally used in high frequency circuits are small and the bias current is small, the offset error will be minimal. If point-to-point wiring is used or a ground plane is not, single point grounding should be used. The input signal return, the load signal return, and the power supply common should all be connected at the same physical point. This will eliminate any common current paths or ground loops which could cause signal modulation or unwanted feedback. It is recommended that the case of the 3554 not be grounded during use (it may, if desired). A grounded case will add a slight capacitance to each pin. To an already functional circuit, grounding the case will probably require slight compensation readjustment and the compensation capacitor values will be slightly different from those recommended in the typical performance curves. There is no internal connection to the case. Proper grounding is the single most important aspect of high frequency circuitry.

3554

GUARDING The input terminals of the 3554 may be surrounded by a guard ring to divert leakage currents from the input terminals. This technique is particularly important in low bias current and high input impedance applications. The guard, a conductive path that completely surrounds the two amplifier inputs, should be connected to a low impedance point which is at the input signal potential. It blocks unwanted printed circuit board leakage currents from reaching the input terminals. The guard will also reduce stray signal coupling to the input. In high frequency applications, guarding may not be desirable as it increases the input capacitance and can degrade performance. The effects of input capacitance, however, can be compensated by a small capacitor placed across the feedback resistor. This is described further in the following section. COMPENSATION The 3554 uses external frequency compensation so that the user may optimize the bandwidth or slew rate or settling time for his particular application. Several typical performance curves are provided to aid in the selection of the correct compensation capacitance value. In addition, several typical circuits show recommended compensation in different applications. The primary compensation capacitor, CF, is connected between pins 1 and 3. As the performance curves show, larger closed-loop gain configurations require less capacitance and an improved gain-bandwidth product will be realized. Note that no compensation capacitor is required for closed-loop gains above 55V/V and when the load capacitance is less than 100pF. When driving large capacitive loads, 470pF and greater, an additional capacitor, C8, is connected between pin 8 and ground. This capacitor is typically 1000pF. It is particularly necessary in low closed loop voltage gain configurations. The value may be varied to optimize performance and will depend upon the load capacitance value. In addition, the performance may be optimized by connecting a small resistance in series with the output and a small capacitor from pin 1 to 5. See the Typical Circuits for the XGain = 10V/V circuit. The flat high frequency response of the 3554 may be preserved and any high frequency peaking avoided by connecting a small capacitor in parallel with the feedback resistor. This capacitor will compensate for the closed-loop, high frequency, transfer function zero that results from the time constant formed by the input capacitance of the amplifier, typically 2pF, and the input and feedback resistors. Using small resistor values will keep the break frequency of this zero sufficiently high, avoiding peaking and preserving the phase margin. Resistor values less than 5.6k are recommended. The selected compensation capacitor may be a trimmer, a fixed capacitor, or a planned PC board capacitance. The capacitance value is strongly dependent on circuit

layout and closed-loop gain. It will typically be 2pF for a clean layout using low resistances (1k) and up to 10pF for circuits using larger resistances. SETTLING TIME Settling time is a complete dynamic measure of the 3554s total performance. It includes the slew rate time (a large signal dynamic parameter) and the time to accurately reach the final value (a small signal parameter that is a function of bandwidth and open loop-gain). The settling time may be optimized for the particular application by selection of the closed-loop gain and the compensation capacitance. The best settling time is observed in low closed-loop gain circuits. A performance curve shows the settling time to three different error bands. Settling time is defined as the total time required from the signal input step for the output to settle to within the specified error band around the final value. This error band is expressed as a percentage of the magnitude of the output transition. SLEW RATE Slew rate is primarily an output, large signal parameter. It has virtually no dependence upon the closed-loop gain or the bandwidth. It is dependent upon compensation. Decreasing the compensation capacitor value will increase the available slew rate as shown in the performance curve. Stray capacitances may appear to the amplifier as compensation. To avoid limiting the slew rate performance, stray capacitances should be minimized. CAPACITIVE LOADS The 3554 will drive large capacitive loads (up to 1000pF) when properly compensated. See the section on Compensation. The effect of a capacitive load is to decrease the phase margin of the amplifier. With compensation the amplifier will provide stable operation even with large capacitive loads. The 3554 is particularly well suited for driving 50 loads connected via coaxial cables due to its 100mA output drive capability. The capacitance of the coaxial cable, 29pF/foot of length for RG-58, does not load the amplifier when the coaxial cable or transmission line is terminated in the characteristic impedance of the transmission line. OFFSET VOLTAGE ADJUSTMENT The offset voltage of the 3554 may be adjusted to zero by connecting a 20k linear potentiometer between pins 4 and 8 with the wiper connected to the positive supply. A small, noninductive potentiometer is recommended. The leads connecting the potentiometer to pins 4 and 8 should be extremely short to avoid stray capacitance and stray signal pickup. Stray coupling from the output, pin 1, to pin 4 (negative feedback) or to pin 8 (positive feedback) should be avoided or oscillation may occur.

3554

10

The potentiometer is optional and may be omitted when the guaranteed offset voltage is considered sufficiently low for the particular application. For each microvolt of offset voltage adjusted, the offset voltage temperature drift will change by 0.004V/C. HEAT SINKING The 3554 does not require a heat sink for operation in most environments. The use of a heat sink, however, will reduce the internal thermal rise and will result in cooler operating temperatures. At extreme temperature and under full load conditions a heat sink will be necessary as indicated in the Maximum Power Dissipation curve. A heat sink with 8 holes for the 8 amplifier pins should be used. Burr-Brown has heat sinks available in three sizes 3C/W, 4.2C/W and 12C/W. A separate product data sheet is available upon request. When heat sinking the 3554, it is recommended that the heat sink be connected to the amplifier case and the combination not connected to the ground plane. For a single-sided printed circuit board, the heat sink may be mounted between the 3554 and the nonconductive side of the PC board, and insulating washers, etc., will not be required. The addition of a heat sink to an already functional circuit will probably require slight compensation readjustment for optimum performance due to the change in stray capacitances. The added stray capacitance from the heat sink to each pin will depend on the thickness and type of heat sink used.

SHORT CIRCUIT PROTECTION The 3554 is short circuit protected for continuous output shorts to common. Output shorts to either supply will destroy the device, even for momentary connections. Output shorts to other potential sources are not recommended as they may cause permanent damage. TESTING The 3554 may be tested in conventional operational amplifier test circuits; however, to realize the full performance capabilities of the 3554, the test fixture must not limit the full dynamic performance capability of the amplifier. High frequency techniques must be employed. The most critical dynamic test is for settling time. The 3554 Settling Time Test Circuit Schematic and a test circuit layout is shown with the Typical Circuits. The input pulse generator must have a flat topped, fast settling pulse to measure the true settling time of the amplifier. The layout exemplifies the high frequency considerations that must be observed. The layout also may be used as a guide for other test circuits. Good grounding, truly square drive signals, minimum stray coupling and small physical size are important. Every 3554 is thoroughly tested prior to shipment assuring the user that all parameters equal or exceed their specifications.

11

3554

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