Tea 1532

TEA1532(A)P; TEA1532(A)T
GreenChipII SMPS control IC

Rev. 02 4 February 2005 Product data sheet
1. General description
The GreenChipII is the second generation of green Switched Mode Power Supply (SMPS) controller ICs. Its high level of integration allows the design of a cost effective power supply with a very low number of external components. The TEA1532(A)P; TEA1532(A)T can also be used in xed frequency, Continuous Conduction Mode (CCM) converter designs for low voltage, high current applications. At low power (standby) levels, the system operates in cycle skipping mode which minimizes the switching losses during standby. The special built-in green functions allow the efciency to be optimum at all power levels. This holds for quasi-resonant operation at high power levels, as well as xed frequency operation with valley switching at medium power levels. At low power (standby) levels, the system operates in cycle skipping mode with valley detection. The proprietary high voltage BCD800 process makes direct start-up possible from the rectied universal mains voltage in an effective and green way. A second low voltage BICMOS IC is used for accurate, high speed protection functions and control. The TEA1532(A)P; TEA1532(A)T enables highly efcient and reliable supplies to be designed easily.
2. Features
2.1 Distinctive features
s s s s Universal mains supply operation (70 V to 276 V AC) High level of integration, resulting in a very low external component count Fixed frequency Continuous Conduction Mode (CCM) operation capability Quasi-Resonant (QR) Discontinuous Conduction Mode (DCM) operation capability.
2.2 Green features

s Valley or zero voltage switching for minimum switching losses in QR operation s Cycle skipping mode at very low loads; input power < 300 mW at no-load operation for a typical adapter application s On-chip start-up current source.
2.3 Protection features

s Safe restart mode for system fault conditions s Zero current switch-on in QR mode
Philips Semiconductors
s s s s s s
Undervoltage protection (foldback during overload) IC OverTemperature Protection (OTP) (latched) Low and adjustable OverCurrent Protection (OCP) trip level Soft (re)start Mains voltage-dependent operation-enabling level TEA1532AP and TEA1532AT: General purpose input for latched or safe restart protection and timing, e.g. to be used for overvoltage protection (OVP), output short-circuit protection or system OTP. s TEA1532P and TEA1532T: General purpose input for latched protection and timing, e.g. to be used for OVP, output short-circuit protection or system OTP. s Brown-out protection.
3. Applications
s Printer adapters and chargers. The device can also be used in all applications that demand an efcient and cost-effective solution up to 250 W.
4. Ordering information
Table 1: Ordering information Package Name TEA1532T TEA1532AT TEA1532P TEA1532AP DIP8 SO8 Description plastic small outline package; 8 leads; body width 3.9 mm plastic dual in-line package; 8 leads (300 mil) Version SOT96-1 SOT97-1 Type number
9397 750 14319
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 4 February 2005
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5. Block diagram
VCC
SUPPLY MANAGEMENT DCM AND CCM DETECTION
START-UP CURRENT SOURCE Iprot(dem) VALLEY clamp
DRAIN
internal UVLO start supply GND 2 S1 Vm
5 OSCILLATOR LOGIC
80 mV
DEM
SLOPE COMPENSATION DRIVER Osc_Rdy Duty_Max 4

Islopecomp 1 POWER-ON RESET
5.6 V
50 mV
LOGIC Iss S Q LEB blank

0.5 V
DRIVER
CTRL
soft start S2
UVLO
Q OCP
control detect
MAXIMUM ON-TIME PROTECTION 6 DCM and CCM BROWN-OUT PROTECTION SENSE
0.63 V
S3
(1) 2.5 V
PROTECT
3
300
Icharge S
5.6 V
Idischarge
3V
protect detect
OVERTEMPERATURE PROTECTION
VCC < 4.5 V
TEA1532T TEA1532AT TEA1532P TEA1532AP
coa014
(1) Switch S3 is not controlled in the TEA1532T and TEA1532P (xed as drawn).
Fig 1. Block diagram
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6. Pinning information
6.1 Pinning
VCC GND PROTECT CTRL
1 2 3 4
001aaa829
8 7
DRAIN
VCC GND
1 2
DRAIN
DRIVER TEA1532T TEA1532AT 6 SENSE 5 DEM
7 DRIVER TEA1532P TEA1532AP 6 SENSE PROTECT 3 CTRL 4

001aaa828
DEM
Fig 2. Pin conguration: TEA1532(A)T (SOT96-1)
Fig 3. Pin conguration: TEA1532(A)P (SOT97-1)
6.2 Pin description

Table 2: Symbol VCC GND PROTECT CTRL DEM SENSE DRIVER DRAIN Pin description Pin 1 2 3 4 5 6 7 8 Description supply voltage ground protection and timing input control input input from auxiliary winding for demagnetization timing programmable current sense input MOSFET gate driver output drain of the external MOS switch, input for start-up current and valley sensing
7. Functional description
The TEA1532(A)P; TEA1532(A)T is the controller of a compact yback converter, with the IC situated at the primary side. An auxiliary winding of the transformer provides demagnetization detection and powers the IC after start-up; see Figure 4.
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Vi CVIN
1 CVCC
2 TEA1532T 7
TEA1532AT TEA1532P 6 3 TEA1532AP

4 5
coa015
Fig 4. Typical conguration
The TEA1532(A)P; TEA1532(A)T can operate in multi modes; see Figure 5.
f (kHz) Cycle skip 63
coa017
fixed
FF-CCM
QR
P (W)
Fig 5. Multi mode and FF-CCM operation
In QR mode, the next converter stroke is started only after demagnetization of the transformer current (zero current switching), while the drain voltage has reached the lowest voltage to minimize switching losses (green function). The primary resonant circuit of primary inductance and drain capacitor ensures this quasi-resonant operation. The design can be optimized in such a way that zero voltage switching can extend over most of the universal mains range. To prevent very high frequency operation at lower loads, the quasi-resonant operation changes smoothly in xed frequency Pulse Width Modulation (PWM) control.
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Product data sheet
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In xed frequency continuous conduction mode, which can be activated by grounding pin DEM, the internal oscillator determines the start of the next converter stroke. In both operating modes, a cycle skipping mode is activated at very low power (standby) levels.
7.1 Start-up, mains enabling operation level and undervoltage lock out
Refer to Figure 10 and Figure 11. Initially, the IC is self supplying from the rectied mains voltage via pin DRAIN. Supply capacitor CVCC (at pin 1) is charged by the internal start-up current source to a level of about 4 V or higher, depending on the drain voltage. Once the drain voltage exceeds the Vm (mains-dependent operation-enabling level), the start-up current source will continue charging capacitor CVCC (switch S1 will be opened); see Figure 1. The IC will activate the power converter as soon as the voltage on pin VCC passes the Vstart level. At this moment the IC supply from the high voltage pin is stopped (green function). The IC supply is taken over by the auxiliary winding of the yback converter. The moment the voltage on pin VCC drops below VUVLO (undervoltage lock out), the IC stops switching and performs a safe restart from the rectied mains voltage. In the safe restart mode the driver output is disabled and pin VCC voltage is recharged via pin DRAIN.
7.2 Supply management

All (internal) reference voltages are derived from a temperature compensated, on-chip band gap circuit.
7.3 Current control mode

Current control mode is used for its good line regulation behavior. The on-time is controlled by an internal control voltage, which is compared with the primary current information. The primary current is sensed across an external resistor. The driver output is latched in the logic, preventing multiple switch-on. The internal control voltage is inversely proportional to the external pin CTRL voltage, with an offset of 1.5 V. This means that a voltage range from 1 V to approximately 1.5 V on pin CTRL will result in an internal control voltage range from 0.5 V to 0 V (a high external control voltage results in a low duty cycle).
Vsense(max) (V)
coa016
0.52 V Cycle skip active
25 mV 1V (typ) 1.5 V (typ) VCTRL (V)
Fig 6. The Vsense(max) voltage as a function of VCTRL
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7.4 Oscillator
The xed frequency of the oscillator is set by an internal current source and capacitor.
7.5 Cycle skipping

At very low power levels, a cycle skipping mode activates. An internal control voltage (Vsense(max)) lower than 25 mV will inhibit switch-on of the external power MOSFET until this voltage increases to a higher value; see Figure 6.
7.6 Demagnetization (QR operation)

The system will be in Discontinuous Conduction Mode (DCM) (QR operation) when resistor RDEM is applied. The oscillator will not start a new primary stroke until the previous secondary stroke has ended. Demagnetization features a cycle-by-cycle output short-circuit protection which immediately reduces the frequency (longer off-time), thereby reducing the power level. Demagnetization recognition is suppressed during the rst tsupp time (typical 1.5 s). This suppression may be necessary in applications where the transformer has a large leakage inductance and at low output voltages or start-up.
7.7 Continuous Conduction Mode (CCM)

It is also possible to operate the IC in the so-called Fixed Frequency Continuous Conduction Mode (FF CCM). This mode is activated by connecting pin DEM to ground and connecting pin DRAIN to the rectied Vi voltage; see Figure 13.
7.8 OverCurrent Protection (OCP)

The primary current in the transformer is measured accurately by the internal cycle-by-cycle source current limit circuit using the external sense resistor Rsense. The accuracy of the current limit circuit allows the transformer core to have a minimum specication for the output power required. The OCP circuit limits the sense voltage to an internal level (the primary peak current in the transformer is also limited). The OCP detection is suppressed during the leading edge blanking period, tleb generated by the Leading Edge Blanking (LEB) circuit, to prevent false triggering caused by the switch-on spikes.
7.9 Control pin protection

If pin CTRL becomes open-circuit or is disconnected, a fault condition is assumed and the converter will stop switching immediately. Operation recommences when the fault condition is removed.
7.10 Adjustable slope compensation

A slope compensation function has been added at pin CTRL; see Figure 7. The slope compensation function prevents sub-harmonic oscillation in CCM at duty cycles over 50 %. The CTRL voltage is modulated by sourcing a (non-constant) current out of pin CTRL and by adding externally a series resistor Rslopecomp. This increases the CTRL voltage proportionally with the on-time, which therefore limits the OCP level. A longer on-time results in a higher CTRL voltage, this increase in CTRL voltage will decrease the
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on-time. Slope compensation can be adjusted by changing the value of Rslopecomp. Slope compensation prevents modulation of the on-time (duty cycle) while operating in FF CCM. A possible drawback of sub-harmonic oscillation can be output voltage ripple. The source current of pin CTRL is always active. In QR mode, the Rslopecomp resistor is replaced by a short, so the modulation of the CTRL voltage is almost negligible.
Slope compensation current
Rslopecomp
CTRL 4
1 5.6 V
RCTRL
control detect
0.63 V
001aaa830
Fig 7. Slope compensation
7.11 Minimum and maximum on-time

The minimum on-time of the SMPS is determined by the LEB time (typical 400 ns). The IC limits the on-time to a maximum time which is dependent on the mode of operation: QR mode: When the system requires an on-time of more than 25 s, a fault condition is assumed, the IC stops switching and enters the safe restart mode. CCM: The driver duty cycle is limited to 70 %. So the maximum on-time is correlated to the oscillator time which results in an accurate limit of the minimum input voltage of the yback converter.
7.12 PROTECT and timing input

The PROTECT input (pin 3) is a multi-purpose (high-impedance) input, which can be used to switch off the IC and create a relatively long timing function. As soon as the voltage on this pin rises above 2.5 V, switching stops immediately. For the timing function, a current of typically 50 A ows out of pin PROTECT and charges an external capacitor until the activation level of 2.5 V is reached. This current source is only activated when the converter is not in regulation, which is detected by the voltage on pin CTRL (VCTRL < 0.63 V). A (small) discharge current is also implemented to ensure that the capacitor is not charged, for example, by spikes A MOSFET switch is added to discharge the external capacitor and ensure a dened start situation. For the TEA1532AP and the TEA1532AT, the voltage on pin CTRL determines whether the IC enters latched protection mode, or safe restart protection mode:
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When the voltage on pin CTRL is below 0.63 V, the IC is assumed to be out of
regulation (e.g. the control loop is open). In this case activating pin PROTECT (VPROTECT > 2.5 V) will cause the converter to stop switching. Once VCC drops below VUVLO, capacitor CVCC will be recharged and the supply will restart. This cycle will be repeated until the fault condition is removed (safe restart mode).
When the voltage on pin CTRL is above 0.63 V, the output is assumed to be in
regulation. In this case activating pin PROTECT (VPROTECT > 2.5 V), by external means, will activate the latch protection of the IC: The voltage on pin VCC will cycle between Vstart and VUVLO, but the IC will not start switching again until the latch protection is reset. The latch is reset as soon as VCC drops below 4.5 V (typical value) (this only occurs when the mains has been disconnected). The internal overtemperature protection will also trigger this latch; see also Figure 1. For the TEA1532P and the TEA1532T the IC always enters the latched mode protection independent of the voltage on pin CTRL. A voltage higher than 3 V on pin PROTECT will always latch the IC. This is independent of the state of the IC.
7.13 Valley switching

Refer to Figure 8. A new cycle starts when the power switch is activated. After the on-time (determined by the sense voltage and the internal control voltage), the switch is opened and the secondary stroke starts. After the secondary stroke, the drain voltage shows an 1 oscillation with a frequency of approximately ----------------------------------------2 L p Cd where Lp is the primary self inductance of the transformer and Cd is the capacitance on the drain node. As soon as the oscillator voltage is high again and the secondary stroke has ended, the circuit waits for the lowest drain voltage before starting a new primary stroke. This method is called valley detection. Figure 8 shows the drain voltage, valley signal, secondary stroke signal and the oscillator signal. In an optimum design, the reected secondary voltage on the primary side will force the drain voltage to zero. Thus, zero voltage switching is possible, preventing large capacitive 1 2 switching losses P = -- C V f , and allowing high frequency operation, which 2 results in small and cost effective magnetics.
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primary stroke
secondary stroke
secondary ringing
drain
valley
secondary stroke
(2)
(1)
oscillator
mgu235
(1) Start of new cycle at lowest drain voltage. (2) Start of new cycle in a classical PWM system at high drain voltage.
Fig 8. Signals for valley switching
7.14 Brown-out protection

During the so called brown-out test, the input voltage is slowly decreased. Since the on-time depends on Vi, long on-times at low Vi can damage the (external) power device. This is prevented by stopping the converter when the input voltage drops too low. When the voltage on pin DEM drops below 50 mV during the on-time (QR mode), the maximum on-time is set to 25 s. The maximum on-time will be reached while Vi is low. Subsequently, the IC stops switching and VCC drops below VUVLO. Capacitor CVCC will only be recharged and the supply will restart only when voltage Vi is high enough (Vm, also see Section 7.1). In addition to this, a Vi level at which the converter has to enter a safe restart can be set with a demagnetization resistor. During the primary stroke, the rectied mains input voltage is measured by sensing the current drawn from pin DEM. This current depends on the mains voltage, according to the following formula: V aux N V mains I ( DEM ) -------------- ------------------------R DEM R DEM N aux Where: N = ----------Np The latter function requires an on-time of at least 2 s. This on-time ensures that a reliable demagnetization current can be measured.
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When pin DEM is grounded (CCM), the brown-out protection is disabled. In this case the duty cycle is limited to 0.7, so at low mains voltage the on-time is limited and therefore the dissipation in the FET is limited.
7.15 OverTemperature protection (OTP)

The IC provides accurate OTP. The IC will stop switching when the junction temperature exceeds the thermal shutdown temperature. When VCC drops to VUVLO, capacitor CVCC will be recharged to the Vstart level, however switching will not restart. Subsequently, VCC will drop again to VUVLO, etc. Operation only recommences when VCC drops below a level of about 4.5 V (typically, when Vmains is disconnected for a short period).
7.16 Soft start-up (pin SENSE)

To prevent transformer rattle at start-up or during hiccup, the transformer peak current is slowly increased by the soft start function. This can be achieved by inserting a resistor and a capacitor between pin SENSE (pin 6) and sense resistor Rsense. An internal current source charges the capacitor to Vsense = Iss Rss (about 0.5 V maximum). The start level and the time constant of the increasing primary current level can be adjusted externally by changing the values of Rss and Css. V ocp ( I ss R ss ) I primary(max) = ----------------------------------------R sense = R ss C ss During the start-up phase, the charging current Iss will ow as long as the voltage on pin SENSE is below approximately 0.5 V. If the voltage on pin SENSE exceeds 0.5 V, the soft start current source will start limiting current Iss. At Vstart, the Iss current source is completely switched off; see Figure 9. Since the soft start current Iss is subtracted from pin VCC charging current, the Rss value will affect VCC charging current level by a maximum of 60 A (typical).
Iss
0.5 V
start-up 6 SENSE Rss
Vocp
Css
Rsense
mgu237
Fig 9. Soft start-up
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7.17 Driver
The driver circuit to the gate of the power MOSFET has a current sourcing capability of typically 170 mA and a current sink capability of typically 700 mA at VCC of 9.5 V. At VCC = 15 V, the current sourcing capability is typically 300 mA and the current sink capability typically 1.2 A. This permits fast turn-on and turn-off of the power MOSFET for efcient operation. A low driver source current has been chosen to limit the V/t at switch-on. This reduces Electro Magnetic Interference (EMI) and also limits the current spikes across Rsense.
8. Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are measured with respect to ground (pin 2); positive currents ow into the chip; pin VCC may not be current driven. The voltage ratings are valid provided other ratings are not violated; current ratings are valid provided the maximum power rating is not violated. Symbol Voltages VCC VPROTECT VCTRL VDEM VSENSE VDRAIN Currents ICTRL IDEM ISENSE IDRIVER IDRAIN General Ptot total power dissipation Tamb < 70 C SO8 package DIP8 package Tstg Tj ESD VESD electrostatic discharge voltage human body model machine model
[1] [2]
Parameter supply voltage voltage on pin PROTECT voltage on pin CTRL voltage on pin DEM voltage on pin SENSE voltage on pin DRAIN current on pin CTRL current on pin DEM current on pin SENSE current on pin DRIVER current on pin DRAIN
Conditions continuous continuous current limited current limited
Min 0.4 0.4 0.4 0.4 0.4
Max +20 +5 +5 +650 50 +250 +10 +2 5
Unit V V V V V V mA A mA A mA
d < 10 %
1000 1
d < 10 %
0.8 -
55 20
0.5 0.75 +150 +145
W W C C
storage temperature junction temperature class 1 pins 1 to 7 pin 8 (DRAIN)

[1] [1] [2]
2000 1500 200
V V V
Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10 resistor.
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9. Thermal characteristics
Table 4: Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air; SO8 package in free air; DIP8 package Typ 150 95 Unit K/W K/W
10. Characteristics
Table 5: Characteristics Tamb = 25 C; VCC = 15 V; all voltages are measured with respect to ground (pin 2); currents are positive when owing into the IC; unless otherwise specied. Symbol IDRAIN Parameter supply current drawn from pin DRAIN Conditions VDRAIN > 100 V VCC = 0 V with auxiliary supply VB Vm breakdown voltage mains-dependent operation-enabling level start-up voltage lock-out undervoltage hysteresis voltage high charging current low charging current restart current supply current under normal operation demagnetization comparator threshold voltage continuous conduction mode detection threshold voltage negative clamp voltage positive clamp voltage suppression of transformer ringing at start of secondary stroke minimum on-time maximum on-time maximum duty-cycle QR mode IDEM = 500 A IDEM = 250 A Vstart VUVLO VDRAIN > 100 V; VCC < 3 V VDRAIN > 100 V; 3 V < VCC < VUVLO VDRAIN > 100 V; VUVLO < VCC < Vstart no load on pin DRIVER 1.0 650 60 1.2 100 1.4 300 100 mA A V V Min Typ Max Unit Start-up current source (pin DRAIN)
Supply voltage management (pin VCC) Vstart VUVLO Vhys Ich(h) Ich(l) Irestart Ioper 10.3 8.1 2.0 1.2 1.2 650 1.1 11 8.7 2.3 1 0.75 550 1.3 11.7 9.3 2.6 0.8 0.45 450 1.5 V V V mA mA A mA
Demagnetization management (pin DEM) Vth(DEM) Vth(CCM) Vclamp(neg) Vclamp(pos) tsupp 50 80 0.5 0.5 1.1 80 50 0.45 0.7 1.5 110 20 0.40 0.9 1.9 mV mV V V s
Pulse width modulator ton(min) ton(max) max 20 67 tleb 25 70 30 73 ns s %
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Table 5: Characteristics continued Tamb = 25 C; VCC = 15 V; all voltages are measured with respect to ground (pin 2); currents are positive when owing into the IC; unless otherwise specied. Symbol Oscillator fosc oscillator frequency (xed frequency) minimum voltage for maximum duty cycle maximum voltage for minimum duty cycle slope compensation current Control detect level trip level trip level for latch voltage level on pin VCC which resets the latch charge current discharge current valley recognition voltage change delay from valley recognition to switch-on maximum source voltage for OCP propagation delay from detecting Vsense(max) to switch-off blanking time for current and winding short-circuit protection soft start current brown-out protection current minimum on-time for enabling the brown-out protection. source current sink current VCC = 9.5 V; VDRIVER = 2 V VCC = 9.5 V VDRIVER = 2 V VDRIVER = 9.5 V Vo(max) maximum output voltage VCC > 12 V 400 300 700 11.5 12 mA mA V Vsense < 0.5 V A constant Ibrown-out is drawn from pin DEM.
[3] [2] [1]
Parameter
Conditions VCTRL < 1 V
Min 50
Typ 63
Max 75
Unit kHz
Duty cycle control (pin CTRL) Vmin Vmax Islopecomp/t VCTRL(detect) Vtrip Vtrip(latch) VCC(latch)(reset) Icharge Idischarge V/tvalley tvalley-swon 1.2 0.56 2.37 2.85 VCC(latch) < 2.3 V VCTRL < 0.63 V 57 43 1.0 1.5 1 0.63 2.5 3 4.5 50 100 150 0.8 0.70 2.63 3.15 43 +43 V V A/s V V V V A nA V/s ns
Protection and timing input (pin PROTECT)
Valley switch (pin DRAIN)
Overcurrent and winding short-circuit protection (pin SENSE) Vsense(max) tPD V/t = 0.1 V/s V/t = 0.5 V/s 0.48 0.52 140 0.56 185 V ns
tleb Iss Ibrown-out ton(min)(brown-out)
330 45 68 1.5
400 60 60 2
470 75 52 2.5
ns A A s
Brown-out protection (pin DEM)
Driver (pin DRIVER) Isource Isink 170 88 mA
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Table 5: Characteristics continued Tamb = 25 C; VCC = 15 V; all voltages are measured with respect to ground (pin 2); currents are positive when owing into the IC; unless otherwise specied. Symbol Tprot(max) Tprot(hyst) Parameter maximum temperature protection level hysteresis for the temperature protection level
[4]
Conditions
Min 130 -
Typ 140 8
Max 150 -
Unit C C
Temperature protection
[1] [2] [3] [4]
TEA1532AP and TEA1532AT: safe restart; TEA1532P and TEA1532T: latch. Guaranteed by design. Vi detection level. Set by the demagnetization resistor RDEM; see Section 7.14. Valid for VCC > 2 V.
11. Application information

A converter with the TEA1532(A)P; TEA1532(A)T consists of an input lter, a transformer with a third winding (auxiliary), and an output stage with a feedback circuit. Capacitor CVCC buffers the IC supply voltage, which is powered via the internal current source, that is connected to the rectied mains, during start-up and via the auxiliary winding during operation. A sense resistor Rsense converts the primary current into a voltage at pin SENSE. The value of Rsense denes the maximum primary peak current. Figure 10 shows a yback conguration using the discontinuous conduction mode. Pin PROTECT is used in this example for external overvoltage protection and open loop or output short-circuit protection. If this pin is not used, it must be tied to ground. Figure 13 shows a yback conguration using the continuous conduction mode. Pin PROTECT is used in this example for external overtemperature protection and open loop or output short-circuit protection.
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Vmains Vi
VCC GND PROTECT CTRL
DRAIN power MOSFET Rss Css Rsense
DRIVER 2 TEA1532T 7 3 4
TEA1532AT TEA1532P 6 SENSE TEA1532AP

5 DEM
RCTRL
RDEM
coa011
Fig 10. Flyback conguration using the discontinuous conduction mode
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Vi
Vi VDRAIN
VO
Vstart VCC
VUVLO
VDRIVER
2.5 V VPROTECT
Start-up sequence
Normal operation
OVP (TEA1532A)
Normal operation
Output short-circuit (TEA1532A)
Brown-out(1)
001aaa840
(1) In CCM, the brown-out protection is implemented by the maximum duty cycle in combination with pin PROTECT.
Fig 11. Typical waveforms 1
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Vi
Vi VDRAIN
VO
Vstart VCC VUVLO
VDRIVER
2.5 V VPROTECT(1)
Start-up sequence
Normal operation
Protection active(2)
001aaa841
(1) When VPROTECT is forced above 3 V, the protection is always latched. So the IC is not started at Vstart unless the VCC voltage drops below the VCC(reset) level. This is the same action used for external OTP compensation described in Section 7.15. (2) External OTP for TEA1532T, TEA1532P, TEA1532AT and TEA1532AP; OVP and output short circuit for TEA1532P and TEA1532T.
Fig 12. Typical waveforms 2
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Vmains Vi
VCC GND PROTECT(1) CTRL Rslopecomp RCTRL
8 DRAIN power MOSFET Rss Css Rsense
DRIVER 2 TEA1532T 7 3 4
TEA1532AT SENSE TEA1532P 6 TEA1532AP

5 DEM
coa013
(1) Pin PROTECT is used in this example for external OTP and open loop or output short-circuit protection. Slope compensation is determined by the value of Rslopecomp.
Fig 13. Flyback conguration using the continuous conduction mode
12. Test information

12.1 Quality information
The General Quality Specication for Integrated Circuits, SNW-FQ-611 is applicable.
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13. Package outline

SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
A X
c y HE v M A
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 w M L detail X (A 3) A
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8o o 0
ISSUE DATE 99-12-27 03-02-18
Fig 14. Package outline SOT96-1 (SO8)

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DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
D seating plane
ME
A2
A1
c Z e b1 w M (e 1) b2 5 MH
b 8
pin 1 index E
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.14 0.068 0.045 b1 0.53 0.38 0.021 0.015 b2 1.07 0.89 0.042 0.035 c 0.36 0.23 0.014 0.009 D (1) 9.8 9.2 0.39 0.36 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 1.15 0.045
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT97-1 REFERENCES IEC 050G01 JEDEC MO-001 JEITA SC-504-8 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 15. Package outline SOT97-1 (DIP8)

Product data sheet
21 of 27
14. Soldering
14.1 Introduction
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for ne pitch SMDs. In these situations reow soldering is recommended. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing.
14.2 Through-hole mount packages

14.2.1 Soldering by dipping or by solder wave
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specied maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
14.2.2 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 C and 400 C, contact may be up to 5 seconds.
14.3 Surface mount packages

14.3.1 Reow soldering
Reow soldering requires solder paste (a suspension of ne solder particles, ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
below 225 C (SnPb process) or below 245 C (Pb-free process)

for all BGA, HTSSON..T and SSOP..T packages
Product data sheet
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for packages with a thickness 2.5 mm for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
14.3.2 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specically developed. If wave soldering is used the following conditions must be observed for optimal results:
Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be xed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated ux will eliminate the need for removal of corrosive residues in most applications.
14.3.3 Manual soldering

Fix the component by rst soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the at part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
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Product data sheet
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14.4 Package related soldering information

Table 6: Mounting Through-hole mount Through-hole-surface mount Surface mount Suitability of IC packages for wave, reow and dipping soldering methods Package [1] CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL PMFP [4] BGA, HTSSON..T [5], LBGA, LFBGA, SQFP, SSOP..T [5], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [7], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [10], WQCCN..L [10]
[1] [2]
Soldering method Wave suitable suitable [3] not suitable not suitable Reow [2] not suitable suitable Dipping suitable
not suitable [6]
suitable
suitable not not recommended [7] [8] recommended [9]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales ofce. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. Hot bar soldering or manual soldering is suitable for PMFP packages. These transparent plastic packages are extremely sensitive to reow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is denitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is denitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[3] [4] [5]
[6]
[7] [8] [9]
[10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on ex foil. However, the image sensor package can be mounted by the client on a ex foil by using a hot bar soldering process. The appropriate soldering prole can be provided on request.
9397 750 14319
Product data sheet
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15. Revision history

Table 7: Revision history Release date 20050204 Data sheet status Product data sheet Change notice Doc. number 9397 750 14319 Supersedes TEA1532_1 Document ID TEA1532_2 Modications:
Products TEA1532AT and TEA1532AP added: Updated Section 4 Ordering information Updated Section 6 Pinning information Changed product numbers in Figure 1, Figure 4, Figure 7, Figure 10, and Figure 13

TEA1532_1
Added note to Figure 1 Modied Figure 6. Preliminary data sheet 9397 750 13113 -
20040528
9397 750 14319
Product data sheet
25 of 27
16. Data sheet status

Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualication Denition This data sheet contains data from the objective specication for product development. Philips Semiconductors reserves the right to change the specication in any manner without notice. This data sheet contains data from the preliminary specication. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specication without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specication. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notication (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
17. Denitions
Short-form specication The data in a short-form specication is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values denition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specication is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specied use without further testing or modication.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production), relevant changes will be communicated via a Customer Product/Process Change Notication (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specied.
19. Trademarks
GreenChip is a trademark of Koninklijke Philips Electronics N.V.
18. Disclaimers
Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
20. Contact information

For additional information, please visit: http://www.semiconductors.philips.com For sales ofce addresses, send an email to: [email protected]
9397 750 14319
Product data sheet
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21. Contents
1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 8 9 10 11 12 12.1 13 14 14.1 14.2 14.2.1 14.2.2 14.3 14.3.1 14.3.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Distinctive features . . . . . . . . . . . . . . . . . . . . . . 1 Green features . . . . . . . . . . . . . . . . . . . . . . . . . 1 Protection features . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Start-up, mains enabling operation level and undervoltage lock out . . . . . . . . . . . . . . . . . . . . 6 Supply management. . . . . . . . . . . . . . . . . . . . . 6 Current control mode . . . . . . . . . . . . . . . . . . . . 6 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Cycle skipping. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Demagnetization (QR operation) . . . . . . . . . . . 7 Continuous Conduction Mode (CCM). . . . . . . . 7 OverCurrent Protection (OCP) . . . . . . . . . . . . . 7 Control pin protection . . . . . . . . . . . . . . . . . . . . 7 Adjustable slope compensation . . . . . . . . . . . . 7 Minimum and maximum on-time. . . . . . . . . . . . 8 PROTECT and timing input . . . . . . . . . . . . . . . 8 Valley switching. . . . . . . . . . . . . . . . . . . . . . . . . 9 Brown-out protection. . . . . . . . . . . . . . . . . . . . 10 OverTemperature protection (OTP) . . . . . . . . 11 Soft start-up (pin SENSE). . . . . . . . . . . . . . . . 11 Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal characteristics. . . . . . . . . . . . . . . . . . 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 15 Test information . . . . . . . . . . . . . . . . . . . . . . . . 19 Quality information . . . . . . . . . . . . . . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Through-hole mount packages . . . . . . . . . . . . 22 Soldering by dipping or by solder wave . . . . . 22 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 22 Surface mount packages . . . . . . . . . . . . . . . . 22 Reow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23 14.3.3 14.4 15 16 17 18 19 20 Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . 23 24 25 26 26 26 26 26
Koninklijke Philips Electronics N.V. 2005

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 4 February 2005 Document number: 9397 750 14319
Published in The Netherlands
This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.

Tea 1532

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Tea 1532

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TEA1532(A)P; TEA1532(A)T

GreenChipII SMPS control IC

2.2 Green features

2.3 Protection features

9397 750 14319

Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet

Rev. 02 4 February 2005

SUPPLY MANAGEMENT DCM AND CCM DETECTION

START-UP CURRENT SOURCE Iprot(dem) VALLEY clamp

internal UVLO start supply GND 2 S1 Vm

SLOPE COMPENSATION DRIVER Osc_Rdy Duty_Max 4

LOGIC Iss S Q LEB blank

MAXIMUM ON-TIME PROTECTION 6 DCM and CCM BROWN-OUT PROTECTION SENSE

VCC < 4.5 V

TEA1532T TEA1532AT TEA1532P TEA1532AP

Fig 1. Block diagram

9397 750 14319

Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet

Rev. 02 4 February 2005

VCC GND PROTECT CTRL

DRIVER TEA1532T TEA1532AT 6 SENSE 5 DEM

7 DRIVER TEA1532P TEA1532AP 6 SENSE PROTECT 3 CTRL 4

Fig 2. Pin conguration: TEA1532(A)T (SOT96-1)

Fig 3. Pin conguration: TEA1532(A)P (SOT97-1)

6.2 Pin description

9397 750 14319

Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet

Rev. 02 4 February 2005

TEA1532AT TEA1532P 6 3 TEA1532AP

Fig 4. Typical conguration

The TEA1532(A)P; TEA1532(A)T can operate in multi modes; see Figure 5.

f (kHz) Cycle skip 63

Fig 5. Multi mode and FF-CCM operation

Product data sheet

Rev. 02 4 February 2005

7.2 Supply management

7.3 Current control mode

0.52 V Cycle skip active

25 mV 1V (typ) 1.5 V (typ) VCTRL (V)

Fig 6. The Vsense(max) voltage as a function of VCTRL

9397 750 14319

Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet

Rev. 02 4 February 2005

7.5 Cycle skipping

7.6 Demagnetization (QR operation)

7.7 Continuous Conduction Mode (CCM)

7.8 OverCurrent Protection (OCP)

7.9 Control pin protection

7.10 Adjustable slope compensation

Product data sheet

Rev. 02 4 February 2005

Slope compensation current

Fig 7. Slope compensation

7.11 Minimum and maximum on-time

7.12 PROTECT and timing input

Product data sheet