MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>

PS21245-E
TRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2001
0.50.2
3.25MAX
1.90.05
0
.
5
M
A
X
10.2
0
.
6

0
.5
I
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Detail B
(t=0.7)
Detail A
1.75MAX
0
.
5
M
A
X
0.80.2
0
.
6

0
.5
I
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Detail C
(t=0.7)
Type name , Lot No.
HEAT SINK SIDE
B C
A
2
-
4
.5
0.2
1 UP
2 VP1
3 VUFB
4 VUFS
5 VP
6 VP1
7 VVFB
8 VVFS
9 WP
10 VP1
11 VPC
12 VWFB
13 VWFS
14 VN1
15 VNC
16 CIN
17 CFO
18 FO
19 UN
20 VN
21 WN
22 P
23 U
24 V
25 W
26 N
(71)
1
2
.
8

1
1
6

1
o
r
8

0
.5
3
1

0
.5
2
8

0
.5
3.80.2
1
3
.
4

0
.5
2
1
.
4

0
.5
3
~
5

1
1
.
5

0
.5
790.5
272.8(=75.6)
2.80.3
670.3
100.3 100.3 100.3 200.3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1819 2021
22 23 24 25 26
4
5

TERMINAL CODE
PS21245-E
INTEGRATED POWER FUNCTIONS
4th generation (planar) IGBT inverter bridge for 3 phase
DC-to-AC power conversion.
APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21245-E
TRANSFER-MOLD TYPE
INSULATED TYPE
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control circuit under-voltage (UV) protection.
Note : Bootstrap supply scheme can be applied.
For lower-leg IGBTS : Drive circuit, Control circuit under-voltage protection (UV), Short circuit protection (SC).
Fault signaling : Corresponding to a SC fault (Low-side IGBT) or a UV fault (Low-side supply).
Input interface : 5V line CMOS/TTL compatible, Schmitt Trigger receiver circuit.
Dimensions in mm
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21245-E
TRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2001
Z
Drive circuit
C
B
U

C
B
U
+
C
B
V

C
B
V
+
C
B
W

C
B
W
+
(15V line)
(5V line) (Note 1, 2)
VD
VNC
VNC
W
AC line input
AC line output
V
U
Input signal
coditioning
Level shifter
Drive circuit
Protection
circuit (UV)
Input signal
coditioning
Input signal
coditioning
Input signal conditioning Fo logic Protection
circuit
Protection
circuit (UV)
Protection
circuit (UV)
Control supply
Under-Voltage
protection
Drive circuit Drive circuit
FO CFO
P
N1 N
Fault output (5V line)
(Note 3, 5)
High-side input (PWM)
(5V line) (Note 1,2)
Low-side input (PWM)
M
(Note 6)
Bootstrap circuit
For detailed description
of the boot-strap circuit
construction, please
contact Mitsubishi
Electric
DIP-IPM
C
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment).
C4
C3
C3 : Tight tolerance, temp-compensated electrolytic type
C4 : 0.22~2F R-category ceramic capacitor for noise filtering.
(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
Note1: To prevent the input signals oscillation, an RC coupling at each input is recommended. (see also Fig. 6)
2: By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 6)
3: This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1k resistance.
(see also Fig. 6)
4: The wiring between the power DC link capacitor and the P/N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22F, high voltage type) is recommended to be mounted close to
these P and N1 DC power input pins.
5: Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF tFO=1.8ms (Typ.))
6: High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
H-side IGBTS
L-side IGBTS
CIN
(Note 4)
Fig. 3
Inrush current
limiter circuit
Level shifter Level shifter
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0s.
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
Drive circuit
Drive circuit
Protection circuit
W
V
U
B
C
VNC
CIN
A
P
N1 N
C
R
Shunt Resistor
External protection circuit
DIP-IPM
L-side IGBTS
H-side IGBTS
SC Protection
Trip Level
IC (A)
tw (s)
2
0
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
Collector current
waveform
(Note 1)
(Note 2)
Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21245-E
TRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2001
Power Terminals
Control Terminals
Tc
Heat sink boundary
DIP-IPM
Heat sink
Tc
400
20~+100
40~+125
1500
VD = 13.5~16.5V, Inverter part
Tj = 125C, non-repetitive, less than 2 s
(Note 2)
60Hz, Sinusoidal, AC 1 minute, connection
pins to heat-sink plate
VCC(PROT)
TC
Tstg
Viso
V
V
V
V
mA
V
20
20
0.5~+5.5
0.5~VD+0.5
15
0.5~VD+0.5
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS,
VWFB-VWFS
Applied between UP, VP, WP-VPC, UN, VN,
WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
Control supply voltage
Control supply voltage
Input voltage
Fault output supply voltage
Fault output current
Current sensing input voltage
VD
VDB
VCIN
VFO
IFO
VSC
450
500
600
20
40
56
20~+150
Applied between P-N
Applied between P-N
TC = 25C
TC = 25C, instantaneous value (pulse)
TC = 25C, per 1 chip
(Note 1)
VCC
VCC(surge)
VCES
IC
ICP
PC
Tj
Condition Symbol Parameter Ratings Unit
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
V
V
V
A
A
W
C
MAXIMUM RATINGS (Tj = 25C, unless otherwise noted)
INVERTER PART
Condition Symbol Parameter Ratings Unit
CONTROL (PROTECTION) PART
Symbol Ratings Unit
Self protection supply voltage limit
(short circuit protection capability)
Module case operation temperature
Storage temperature
Isolation voltage
V
C
C
Vrms
TOTAL SYSTEM
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150C (@ TC 100C) however, to en-
sure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) 125C (@ TC 100C).
Parameter Condition
Note 2 : TC MEASUREMENT POINT
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21245-E
TRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2001
V
V
V
V
V
ms
2.15
2.25
3.00
1.30

0.90
2.60
1.90
1
10
2.2
4.5
0.067
15.0
15.0

0.8
1.2

0.5

1.8
1.4
3.0
Applied between : UP, VP, WP-VPC, UN, VN, WN-VNC
tdead
VD
VDB
VFOH
VFOL
VFOsat
VSC(ref)
UVDBt
UVDBr
UVDt
UVDr
tFO
Vth(on)
Vth(off)
mA
V
Tj = 25C
Tj = 125C
IC = 20A, Tj = 25C
IC = 20A, Tj = 125C
VCE(sat)
VEC
ton
trr
tc(on)
toff
tc(off)
ICES
Condition Symbol Parameter
Limits
Inverter IGBT part (per 1/6 module)
Inverter FWD part (per 1/6 module)
Case to fin, (per 1 module)
thermal grease applied
Rth(j-c)Q
Rth(j-c)F
Rth(c-f)
Min.
C/W
THERMAL RESISTANCE
Typ. Max.

Unit
Tj = 25C, IC = 20A, VCIN = 5V
Condition Symbol Parameter
Limits
Min. Typ. Max.

0.10

Unit
ELECTRICAL CHARACTERISTICS (Tj = 25C, unless otherwise noted)
INVERTER PART
Collector-emitter saturation
voltage
FWD forward voltage
Junction to case thermal
resistance
Contact thermal resistance
VD = VDB = 15V
VCIN = 0V
Switching times
VCC = 300V, VD = VDB = 15V
IC = 20A, Tj = 125C, VCIN = 5V 0V
Inductive load (upper-lower arm)
Collector-emitter cut-off
current
VCE = VCES
1.55
1.65
2.20
0.80
0.10
0.50
1.60
1.00

V
s
s
s
s
s
V
V
V
V
V
Limits
CONTROL (PROTECTION) PART
13.5
13.5

4.9

0.8
2.5
0.45
10.0
10.5
10.3
10.8
1.0
0.8
2.5
Note 3 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC trip-
level is less than 34 A.
4 : Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulse-
width tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 10
-6
tFO [F].
Total of VP1-VPC, VN1-VNC
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
Control supply voltage
Control supply voltage
Condition Symbol Parameter
Min. Typ. Max.
Unit
VD = VDB = 15V,
VCIN= 5V
VSC = 0V, FO = 10k 5V pull-up
VSC = 1V, FO = 10k 5V pull-up
VSC = 1V, IFO = 15mA
Relates to corresponding input signal for blocking arm
shoot-through. 20C TC 100C
Tj = 25C, VD = 15V (Note 3)
16.5
16.5
8.50
1.00

1.2
1.8

0.55
12.0
12.5
12.5
13.0

2.0
4.0
Circuit current
ID
Trip level
Reset level
Trip level
Reset level
Fault output voltage
Arm shoot-through blocking time
Short circuit trip level
Supply circuit under-voltage
protection
Tj 125C
CFO = 22nF (Note 4) Fault output pulse width
ON threshold voltage
OFF threshold voltage
s
V
V
C/W
C/W
mA
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21245-E
TRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2001
V
V
V
V/s
s
kHz
V
V
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
Input ON threshold voltage
Input OFF threshold voltage
Applied between P-N
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
Relates to corresponding input signal for blocking arm shoot-through
TC 100C, Tj 125C
Applied between UP, VP, WP-VPC
Applied between UN, VN, WN-VNC
400
16.5
16.5
1

VCC
VD
VDB
VD, VDB
tdead
fPWM
VCIN(ON)
VCIN(OFF)
Condition Symbol Parameter
Limits
Min. Typ. Max.
0
13.5
13.5
1
2.5

Unit
RECOMMENDED OPERATION CONDITIONS
300
15.0
15.0

5
0~0.65
4.0~5.5
Measurement point
DIP-IPM
Place to contact
a heat sink
Heat sink
Heat sink
(Note 5)
3mm
Note 5: Measurement point of heat-sink flatness
Mounting screw : M4
Weight 19.6N
Weight 9.8N. 90deg bend
(Note 5)
Condition Parameter
Limits
Mounting torque
Terminal pulling strength
Bending strength
Weight
Heat-sink flatness
Min.
MECHANICAL CHARACTERISTICS AND RATINGS
Typ. Max.
0.98
10
2

50
Unit
1.18

54

1.47

100
Nm
s
times
g
m

EIAJ-ED-4701
EIAJ-ED-4701

MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>

PS21245-E
TRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2001
Fig. 4 THE DIP-IPM INTERNAL CIRCUIT
DIP-IPM
UOUT
VOUT
WOUT
VNO
CFO
GND
Fo
WN
VN
UN
VCC
HVIC 3
HVIC 2
HVIC 1
LVIC
CFO CIN
CIN
N
W
V
U
P
HO IN
COM
VB
VS
VCC
HO IN
COM
VB
VS
VCC
HO IN
COM
VB
VS
VCC
Fo
WN
VN
UN
WP
VPC
VP
UP
VNC
VN1
VP1
VP1
VP1
VWFS
VVFS
VUFS
VWFB
VVFB
VUFB
IGBT1
IGBT2
IGBT3
IGBT4
IGBT5
IGBT6
Di1
Di2
Di3
Di4
Di5
Di6
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21245-E
TRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2001
Error output Fo
Output current Ic(A)
Control supply voltage VD
Protection circuit state
Control input
a6 a1 a3
a5
a2
RESET
UVDt
UVDr
SET
a4
Error output Fo
Sense voltage of the
shunt resistor

SC reference voltage
CR circuit time constant DELAY

Output current Ic(A)
Internal IGBT gate
Protection circuit state
N-side control input
a5
a8
a4
a3
a1
a2
SC
RESET
SET
a7
a6
Fig. 5 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS
[A] Short-Circuit Protection (N-side only)
(For the external shunt resistor and CR connection.)
a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit current detection (SC trigger).
a3. Hard IGBT gate interrupt.
a4. IGBT turns OFF.
a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO.
a6. Input H : IGBT OFF state.
a7. Input L : IGBT ON state.
a8. IGBT OFF state.
[B] Under-Voltage Protection (N-side, UVD)
a1. Normal operation : IGBT ON and carrying current.
a2. Under voltage trip (UVDt).
a3. IGBT OFF in spite of control input condition.
a4. FO timer operation starts.
a5. Under voltage reset (UVDr).
a6. Normal operation : IGBT ON and carrying current.
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21245-E
TRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2001
CPU
5.1k
5V line
1nF
1nF
UP,VP,WP,UN,VN,WN
Fo
DIP-IPM
4.7k
VPC, VNC(Logic)
Error output Fo
Output current Ic(A)
Control supply voltage VDB
Protection circuit state
Control input
a6
a1
a2 a4
a5
a3
RESET
UVDBt
UVDBr
SET RESET
High-level (no fault output)
[C] Under-Voltage Protection (P-side, UVDB)
a1. Control supply voltage rises : After the voltage level reachs UVDBr, the circuits start to operate when the next input is applied.
a2. Normal operation : IGBT ON and carrying current.
a3. Under voltage trip (UVDBt).
a4. IGBT OFF in spite of control input condition, but there is no FO signal output.
a5. Under-voltage reset (UVDBr).
a6. Normal operation : IGBT ON and carrying current.
Fig. 6 RECOMMENDED CPU I/O INTERFACE CIRCUIT
Note : RC coupling at each input (parts shown dotted) may change depending on the
PWM control scheme used in the application and on the wiring impedances of
the applications printed circuit board.
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21245-E
TRANSFER-MOLD TYPE
INSULATED TYPE
Sep. 2001
HO
HO
DIP-IPM
C1: Tight tolerance temp-compensated electrolytic type; C2,C3: 0.22~2 F R-category ceramic capacitor for noise filtering
C3
C3
C3
C3
C2
C2
C2
C1
C1
C1
HO
IN
IN
15V line
5V line
5V line
IN
COM
COM
COM
UOUT
VOUT
WOUT
VNO
CFO
GND
Fo
WN
VN
VCC
C
B
A
C4(CFO)
CFO
R1
C5
Shunt
resistor
CIN
CIN
N1
N
W
V
U
P
VS
VS
VS
VB
VB
VB
VCC
VCC
VCC
Fo
WN
VN
UN
UN
WP
VP
UP
VNC
VN1
VPC
VP1
VP1
VP1
VWFS
VVFS
VUFS
VWFB
VVFB
VUFB
M
C
P
U
U
N
I
T
The long wiring of GND might generate
noise on input signals and cause IGBT to
be malfunctioned.
If this wiring is too long, the SC level
fluctuation might be larger and cause SC
malfunction.
If this wiring is too long, short
circuit might be caused.
Fig. 7 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE
Note 1 : To prevent the input signals oscillation, an RC coupling at each input is recommended, and the wiring of each input should be as short
as possible. (Less than 2cm)
2 : By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler
or transformer isolation is possible.
3 : FO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately
5.1k resistance.
4 : FO output pulse width should be decided by connecting an external capacitor between CFO and VNC terminals (CFO). (Example : CFO
= 22 nF tFO = 1.8 ms (typ.))
5 : Each input signal line should be pulled up to the 5V power supply with approximately 4.7k resistance (other RC coupling circuits at
each input may be needed depending on the PWM control scheme used and on the wiring impedances of the systems printed circuit
board). Approximately a 0.22~2F by-pass capacitor should be used across each power supply connection terminals.
6 : To prevent errors of the protection function, the wiring of A, B, C should be as short as possible.
7 : In the recommended protection circuit, please select the R1C5 time constant in the range 1.5~2s.
8 : Each capacitor should be put as nearby the pins of the DIP-IPM as possible.
9 : To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 pins should be as short as possible. Approxi-
mately a 0.1~0.22F snubber capacitor between the P&N1 pins is recommended.