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    Lab 5 Minimization of Boolean Functions

    Uploaded by

    Muhammad Hassan Javed
    This document provides instructions for a lab assignment on minimizing Boolean functions and implementing logic circuits. The objectives are to understand Boolean function minimization, simulate circuits using Verilog, and implement basic logic circuits in hardware. Students are asked to minimize two Boolean functions F(A,B,C) and G(A,B,C) in pre-lab tasks. In the lab tasks, students implement the minimized functions in hardware using available gates and write Verilog code to simulate the gate-level designs. Evaluation is based on pre-lab analysis, lab performance, modern tool usage, ethics and safety, and individual/team work.

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    © All Rights Reserved
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    Lab 5 Minimization of Boolean Functions

    Uploaded by

    Muhammad Hassan Javed
    184 views9 pages
    This document provides instructions for a lab assignment on minimizing Boolean functions and implementing logic circuits. The objectives are to understand Boolean function minimization, simulate circuits using Verilog, and implement basic logic circuits in hardware. Students are asked to minimize two Boolean functions F(A,B,C) and G(A,B,C) in pre-lab tasks. In the lab tasks, students implement the minimized functions in hardware using available gates and write Verilog code to simulate the gate-level designs. Evaluation is based on pre-lab analysis, lab performance, modern tool usage, ethics and safety, and individual/team work.

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    This document provides instructions for a lab assignment on minimizing Boolean functions and implementing logic circuits. The objectives are to understand Boolean function minimization, simulate circuits using Verilog, and implement basic logic circuits in hardware. Students are asked to minimize two Boolean functions F(A,B,C) and G(A,B,C) in pre-lab tasks. In the lab tasks, students implement the minimized functions in hardware using available gates and write Verilog code to simulate the gate-level designs. Evaluation is based on pre-lab analysis, lab performance, modern tool usage, ethics and safety, and individual/team work.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    184 views9 pages

    Lab 5 Minimization of Boolean Functions

    Uploaded by

    Muhammad Hassan Javed
    This document provides instructions for a lab assignment on minimizing Boolean functions and implementing logic circuits. The objectives are to understand Boolean function minimization, simulate circuits using Verilog, and implement basic logic circuits in hardware. Students are asked to minimize two Boolean functions F(A,B,C) and G(A,B,C) in pre-lab tasks. In the lab tasks, students implement the minimized functions in hardware using available gates and write Verilog code to simulate the gate-level designs. Evaluation is based on pre-lab analysis, lab performance, modern tool usage, ethics and safety, and individual/team work.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 9

    Department of Electrical Engineering

    Faculty Member:____________________ Dated: ________________

    Semester:__________________________ Section: ________________

    Group No.:

    EE-221: Digital Logic Design

    Lab 5: Minimization of Boolean Functions

    PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7


    Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
    Performance of data in Tool Usage Safety and Team marks
    Lab Report Work Obtained

    5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks

    EE-221: Digital Logic Design Page 1


    Lab 5: Minimization of Boolean Functions

    This Lab has been divided into two parts.

    The first part is the hardware implementation of a Boolean function given to you. But you have
    to first minimize the Boolean functions to minimum number of literals.

    In next part you will simulate the same circuit using Verilog.

    Objectives:

     Understand Minimization of Boolean Functions


     Simulate Basic Circuits using Verilog
     Hardware Implementation of Basic Logic Circuits

    Lab Instructions

     This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session.
     The lab report will be uploaded on LMS three days before scheduled lab date. The students will get
    hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it with
    teacher/lab engineer for necessary evaluation. Alternately each group to upload completed lab
    report on LMS for grading.
     The students will start lab task and demonstrate design steps separately for step-wise evaluation (
    course instructor/lab engineer will sign each step after ascertaining functional verification)
     Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will
    simplify trouble-shooting process.
     After the lab, students are expected to unwire the circuit and deposit back components before
    leaving.
     The students will complete lab task and submit complete report to Lab Engineer before leaving lab
     There are related questions at the end of this activity. Give complete answers.
    .

    EE-221: Digital Logic Design Page 2


    Pre-Lab Tasks: (To be done before coming to the lab) (2 marks)
    1. Write the Boolean expression of the following two functions. Simplify the expression using algebraic
    manipulation and draw the logic diagram.

    F (A, B, C) = ∑ (2, 3, 7)

    A B C Minterms
    0 0 0 m0 = A’B’C’
    0 0 1 m1 = A’B’C
    0 1 0 m2 = A’BC’
    0 1 1 m3 = A’BC
    1 0 0 m4 = AB’C’
    1 0 1 m5 = AB’C
    1 1 0 m6 = ABC’
    1 1 1 m7 = ABC
    1.F (A, B, C) = ∑ (2, 3, 7)

    = A’BC’+A’BC+ABC

    = A’B(C+C’)+ABC

    = A’B+ABC

    =B(A’+AC)

    =B(A’+A)(A’+C)

    =B(A’+C)

    EE-221: Digital Logic Design Page 3


    G (A, B, C) = ∑ (4, 5, 7)

    A B C Minterms
    0 0 0 m0 = A’B’C’
    0 0 1 m1 = A’B’C
    0 1 0 m2 = A’BC’
    0 1 1 m3 = A’BC
    1 0 0 m4 = AB’C’
    1 0 1 m5 = AB’C
    1 1 0 m6 = ABC’
    1 1 1 m7 = ABC

    2.G (A, B, C) = ∑ (4, 5, 7)

    = AB’C’+ AB’C+ABC

    =AB’(C’+C)+ABC

    =AB’+ABC

    =A(B’+BC)

    =A(B’+B)(B’+C)

    =A(B’+C)

    EE-221: Digital Logic Design Page 4


    2. Mention the number of literals and gates needed for implementing the above function in hardware.
    (1 Mark)

    1.We require three literals and two gates for this purpose for function F.

    2. We require three literals and two gates for this purpose for function G.

    EE-221: Digital Logic Design Page 5


    Lab Tasks (3 marks)
    Lab Task 1:

    Implement the Boolean functions in hardware you simplified in your Pre-Lab Task. Make truth table and
    Schematic. Mention what and how many gates you would be using? The following gates are available to you.

    Truth Table:

    A B C F A B C G
    0 0 0 0 0 0 0 0
    0 0 1 0 0 0 1 0
    0 1 0 1 0 1 0 0
    0 1 1 1 0 1 1 0
    1 0 0 0 1 0 0 1
    1 0 1 0 1 0 1 1
    1 1 0 0 1 1 0 0
    1 1 1 1 1 1 1 1

    EE-221: Digital Logic Design Page 6


    Schematic:

    EE-221: Digital Logic Design Page 7


    Lab Task 2:
    Write Verilog code for the minimized functions at gate-level and perform simulation. Attach the
    relevant snapshots below.
    Verilog Code :
    module lab_5 ( out1,out2,a,b,c);
    input a, b,c;
    output out1,out2;
    wire wire1,wire2,wire3,wire4,wire5;
    not not1(wire1,a);
    not not2(wire2,b);
    or or1(wire3,wire1,c);
    or or2(wire4,wire2,c);
    and and1(out1,wire3,b);
    and(out2,wire4,a);
    endmodule
    module lab5;
    reg in1,in2,in3;
    wire out1,out2;
    lab_5 t1(out1,out2,in1,in2,in3);
    initial
    begin
    #100 in1=1'b0;in2=1'b0; in3=1'b0;
    #100 in1=1'b0;in2=1'b0; in3=1'b1;
    #100 in1=1'b0;in2=1'b1; in3=1'b0;
    #100 in1=1'b0;in2=1'b1; in3=1'b1;
    #100 in1=1'b1;in2=1'b0; in3=1'b0;
    #100 in1=1'b1;in2=1'b0; in3=1'b1;
    #100 in1=1'b1;in2=1'b1; in3=1'b0;
    #100 in1=1'b1;in2=1'b1; in3=1'b1;
    end
    endmodule

    EE-221: Digital Logic Design Page 8


    EE-221: Digital Logic Design Page 9

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