Library Files

Liberty, db, LEF, DEF,

Cap-table, CDB, GDS
 Liberty (.lib)
Contains the timing and functional Information
LIB (Liberty Timing File) :

● Liberty Timing File or .lib file is an ASCII representation of the timing and
power parameters associated with any cell in a particular semiconductor
technology.
● The timing and power parameters are obtained by simulating the cells
under a variety of conditions and the data is represented in the .lib format.
● LIB file is used as input to all Cadence timing tools that can read and
calculate delay from it.
● The file begins with library information common to the entire library of
cells used in the design. The library information includes a header section,
models, and timing properties.
Example of a LIB file :
Figure 5.1 and 5.2 on page 4 & 5 shows a very simple .lib file example.

First we can divide the .lib file into 2 basic scopes.

1. Library information scope.

2. Cell information scope.

Library information common to the entire library of cells used in the design is
main part of the Library information scope.

And in Cell information scope, each cell type in the design which contained
information for every model, pin, and path.
 Example of a LIB file :

Library Header

Library
Scope
{ Properties

Wireload Model

Figure 5.1
 Example of a LIB file :

Cell Header

Cell
Scope
{ Cell Models

Figure 5.2
 Timing Library types :
Based on process corner and timing, library can be categorized into 3 classes:

1. Fast Lib
2. Slow Lib
3. Typical Lib

Process corners represent the parameter variations within which a circuit that has been etched onto the
wafer must function correctly.

In Silicon technology, the performance of the CMOS transistors that we use to create digital logic take a
certain finite amount of time for propagation. The propagation depends on three factors :

1. Process
2. Voltage
3. Temperature

So based on that 3 parameters different types of library has been created.

Basic Differences among those libraries :
❏ Nominal voltage
❏ Nominal temperature
❏ Cell leakage Power
❏ Capacitance
❏ Power
❏ Timing

Slow Fast typical

Figure 5.3 : A part of basic differences among slow,fast & typical libraries.
 Summary of LIB :

LIBRARY SCOPE

Nominal derating default

slew and
library Nominal temperat Operating factors values for Lookup
delay
and delay process ure and condition units and fanout, table
threshold capacitan
model property nominal s wire-load templates
points ce, slew
voltage models
Summary of LIB :

CELL SCOPE

Internal
Output pin
Input Pin Output pin Power
Area timing
information information of all
information
pins

Direction,capac
Direction,
itance,function,
capacitance
timing,internal
 db
Contains the timing and functional Information
.db files:
● .db files contains the same information that .lib does
● Only difference in between .lib and .db is, .lib file is
written in ASCII format and .db file is written in binary
format
● Typically synopsys uses .db files and cadence uses .lib
files
Library Exchange Format
(LEF)
LEF ( Library Exchange Format):
LEF is a specification file for representing the physical layout of an IC in an ASCII
format.It contains library information for a class of designs.

It mainly contains

● Layer information
● Via information
● Placement site type and origin
● Macro cell definitions

Basically for starting a design in a tool, tool requires those informations first.

The LEF file is an ASCII representation of those informations.

Note: In lib and lef there are completely different library information.
LEF ( Library Exchange Format):
● We can also simplify Library Exchange Format (LEF) as a physical library,
which contains the pin information, metal layer information, size of
standard cells etc.
LEF doesn’t contain the internal information of a standard cell.
LEF is actually the abstract view of a standard cell.
● In abstract view there is no base layer information.
● To reduce the complexity LEF file can be divided into two parts:

Note: When reading in LEF files, always read in the technology LEF file first.
Managing LEF Files:
A technology LEF file contains all the technology information of a design
structures, such as placement and routing design rules, process information for
layers and limits of an ASIC design targeted to specific process technology.

Basic Syntax Example of a technology LEF file

Managing LEF Files:
A cell library LEF file contains the macro and standard
cell information for a design.

Basic Syntax Example of a cell library LEF

 LEF File Syntax:
Version: VERSION 5.6

● The version statement indicates which LEF syntax is used to generate the
LEF file. i.e. VERSION 5.6, VERSION 5.7

Bus Bit Characters: BUSBITCHARS “[]”

● BUSBITCHARS is used to specify the bus bits.

● Must be enclosed in double quotation marks. i.e. BUSBITCHARS "[]" ;

● If BUSBITCHARS is not specified in the LEF file, the default value is “[]”.
LEF File Syntax:
Divider Character: [DIVIDERCHAR "character" ;]

● This specifies the character which is used to express hierarchy.

● Character must be enclosed in double quotation. i.e. DIVIDERCHAR "/"

Units:

● Defines the measurement units in the LEF file.

UNITS
DATABASE MICRONS 2000 ;
END UNITS
● Values defined in the LEF file will be multiplied with
UNITS. i.e.
WIDTH 0.23 ; Actual value is 0.23 x 2000 = 460 DBUs(Database Unit)=~
.23u
LEF File Syntax:
Manufacturing Grid: [MANUFACTURINGGRID value ;]

● Defines the geometry alignment.

● If it is defined then the cells are placed in location which is aligned to the
manufacturing grid. i.e. MANUFACTURINGGRID 0.005 ;

Property Definition:

● Defines all the properties used in the design.

● All the properties must be defined in
PROPERTYDEFINITIONS statement.
LEF File Syntax:
Layer: Different types of layers are defined.

● Cut(via cut) layers are defined by assigning names and design rules.
● Defines the Implant layer in the design. For each layer, name, space and
width are defined. Space and width are the factors that affect the legal cell
placement.
● Masterslice(non-routing) layers are defined as well in the layer part. Master
slice layers are basically polysilicon layers.
LEF File Syntax:
Via: This statement defines Via’s which are
used for signal routing. By default, via is
using three layers: cut layers, Routing,
Masterslice.

Via Rule: Defines which vias to use at the

intersection of special wires of the same net.
LEF File Syntax:
Via Rule Generate: This statement is used to
define special wiring.In order to generate
the via arrays, via rule generate defines the
formulas.

Site: Defines a placement site which gives

the placement grid for a family of macros,
core, block etc.
LEF File Syntax:
Macro: This syntax defines the detail
about macros like name, PAD detail,
class size, location of endcap cells
(like top, right, bottom etc.) symmetry,
site name, obstruction detail.
LEF File Syntax:
Non-default Rule: Defines the design rule spacing, wiring width and via size for
signal nets.
Design Exchange Format
(DEF)
Design Exchange Format (DEF):
What is DEF?

Design Exchange Format (DEF) is a specification file for representing logical

connectivity and physical layout of an IC in ASCII format.
Design Exchange Format (DEF):
DEF file contains all physical aspects of a design, such as-

● Die size
● Row information
● Tracks information
● Connectivity
● Physical location of cells and macros
● Floorplanning information
● Blockages information
● Pin information
● Signal & power routing etc
DEF file syntax:
Same as LEF syntax
DEF file syntax:
Design: DESIGN designName ;

● Specify the name of the design.

Unit: [UNITS DISTANCE MICRONS dbuPerMicron ;]

● Defines the database units per micron (dbuPerMicron) to convert DEF

distance units into micron.

Note: LEF dbuPerMicron is not same as DEF dbuPerMicron. The LEF dbuPerMicron
must be greater than or equal to the DEF dbuPerMicron, otherwise you can get
round-off errors.
DEF file syntax:
Property Definition:

● Defines all the properties used in the design.

● All the properties must be defined in PROPERTYDEFINITIONS statement.

Die Area:

● Defines die area of the design.

Row:

● Defines row information of the design

DEF file syntax:
Tracks:

● Defines the routing grid for a standard cell-based

design.
● Routing grid is generated while floorplan is initialized

GCell Grid:

● The design is divided into small boxes, each small box is considered as
GCell.
● This statement defines the gcell grid for
a standard cell based design.
DEF file syntax:
Via:

● Defines the names and geometries

of all vias in the design.
● Both the fixed and generated vias
are listed.

Regions:

● A region is a physical area to which a component or group is assigned

● Specifies the number of regions
defined in the design.
DEF file syntax:
Components:

● Every design components are defined

in this component section.

Pins:

● All the pin information, pin name with corresponding net name are defined.

Blockages:

● All the placement and routing blockages are

defined here.
DEF file syntax:
Special Nets:

● Every single special nets identified by net

name and special pins on the net are
described.

Nets:

● Defines netlist connectivity for nets containing regular pins.

● Nets and special nets can appear more than once in a DEF file.
DEF file syntax:
Scan Chain:

● Scan chains are a collection of flip-flop cells that contain both scan-in and
scan-out pins. These pins are defined in the Pins section.
● Those chains are defined here.
End
Captable :
● Cap table is a table for capacitance values and have a basic and extended cap
tables for all capacitances such as coupling, fringe and area capacitance.

Cap table contains:

* Resistance &
* Capacitance of every Metal layer in the Design
● These two values used to model the interconnect parasitic of a design.
● It also contains the following basic informations of metal layer :
○ MinWidth
○ MinSpace
○ Thickness
○ Width Deviation
○ Thickness ratio
Example :
● Here we can see the different
attributes of layer Metal 1.
● For Nominal temperature
captable gives us exact
information of capacitance
value using vector table.
● From lowest width & height of
metal layer to maximum width
& height ,captable provides
large number of data so that
accurate delay measurement
can be possible.
Example (Basic Cap Table) :
● From the figure we can see that for a
fixed width and spacing ,basic captable
gives us 4 types of capacitance value.
Extended Captable :
Covers the case of non-default rules.The basic purpose of extended cap table is to produce
accurate R & C values in extraction so that we can get proper delay calculation from our
design.

In extended captable basic info of capacitance for each metal layer has given with
some limited spacing and width values in cap table.

If the extraction engine is not able to see a value for capacitance for a particular net
while extracting (means if the capacitance value is not within the range of given values of
spacing and width defined in basic cap table) it calculates from the extended cap table.
Example (Extended Captable) :
CDB file (Celtic Database file) :
For signal integrity analysis beside lib files the tool required the .cdb files also.

Signal Integrity (SI) is a set of measure of the quality of an electrical signal.

Some of the main issues of concern for signal integrity are

* Ringing
* Crosstalk
* Ground bounce
* Distortion
* Signal loss
* Power supply noise
Vendor usually provide them and it is a binary file format.
GDS (Graphic Database System) :

★ It’s a binary file format representing planer

geometric shapes, text labels and other
information.
★ GDS files are usually the final output product of
the IC design cycle and are given to IC foundries
for IC fabrication.
★ For over 25 years GDSII has been the industry
standard database for IC layout. While other
formats have been proposed to replace it (OASIS
format seems to be gaining some traction) GDSII
remains by far the main way of describing the
physical layout for the masks used to build a
chip.
GDS :
➔ It is an integer database. The basic unit of measurement is a nanometer.
➔ Since four byte signed integers are used to describe a coordinate then the
integer coordinates can range from from minus 231 to plus 231-1. (two's
complement).
➔ The database is made binary for compact size and faster reading. That
means any software for reading or writing GDSII has to be able to extract
each byte and interpret the bits.
 GDS :

➔ In final gds only metal,

via, power and pin
connection layer merge
with standard cells gds
and complete the
All
database file format layers
information
which is the industry
standard for data
exchange of or IC
layout art work
integrated circuit.
➔ Each number denotes
standard cells layer.

GDS of a standard cell in calibre

SDC (Standard Design Constraint ) :

What is SDC?
There is a common format, for constraining the design, which is supported by
almost all the tools, and this format is called SDC - Standard Design Constraints
format.
Why we need SDC?
Standard Design Constraint is a format used to specify the design intent,
including the timing, power and area constraints for a design.
The rules that are written are referred to as constraints and are essential to
meet designs goal in terms of Area, Timing and Power to obtain the best
possible implementation of a circuit.
SDC (Standard Design Constraint ) :

What is the file format of SDC?

The file is saved with an .sdc extension.SDC syntax is a TCL based format, that
is, all commands follow the TCL syntax.

Can we grouped SDC constraints?

Yes Design constraints can be grouped as

1. Timing constraints and

2. Physical Constraints.
Timing Constraints :
Timing Constraints are set for meet the designs performance goals.
We can set timing constraints either globally or to a specific set of paths in our
design.
Timing constraints can be applied to :
➔ Specify the required minimum speed of a clock
➔ Define the maximum and minimum delay for a specific path
➔ Provide the external load at a specific port
➔ Set the input and output port timing information
➔ Identify paths that require more than one clock cycle to propagate the
data.
➔ Identify paths that are considered false and excluded from the analysis
Physical Constraints :
Physical Constraints define the size, shape, utilization, and pin/pad placement
of a design.

We can specify these constraints based on the utilization, aspect ratio, and
dimensions of the die.

The pin/pad placement depends on the external physical environment of the

design, such as the placement of the device on the board.
physical constraints can be :
➔ I/O assignments
◆ Set location, attributes, and technologies for I/O ports
➔ Location and region assignments
◆ Set the location of Core, RAM, and Memory macros
Timing Constraints Parameters: