General Description Features: Preliminary Datasheet LP4060A
General Description Features: Preliminary Datasheet LP4060A
General Description Features: Preliminary Datasheet LP4060A
Order Information
LP4060A - □ □ □ □ □ Typical Application Circuit
Vin
4 3
VCC BAT
F: Pb-Free 1
LED R CHRG
1uF + 2 5
Package Type GND PROG
Applications
Portable Media Players/MP3 players
Cellular and Smart mobile phone Marking Information
PDA/DSC Please see website.
Bluetooth Applications
LP4060
PROG (PIN 5): Charge Current Program, Charge Current Monitor and Shutdown Pin. The charge
current is programmed by connecting a 1% resistor, RPROG, to ground. When charging in
constant-current mode, this pin servos to 1V. In all modes, the voltage on this pin can be used to
measure the charge current using the following formula:
IBAT=(VPROG/RPROG) x 830
The PROG pin can also be used to shutdown the charger. Disconnecting the program resistor from
ground allows a 3µA current to pull the PROG pin high. When it reaches the 1.94V shutdown
threshold voltage, the charger enters shutdown mode, charging stops and the input supply current
drops to 25µA. This pin is also clamped to approximately 2.4V. Driving this pin to voltages beyond
the clamp voltage will draw currents as high as1.5mA. Reconnecting RPROG to ground will return the
charger to normal operation.
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired.
Note 2: The LP4060A are guaranteed to meet performance specifications from 0℃ to 70℃.
Specifications over the -40℃ to 85℃ operating temperature range are assured by design,
characterization and correlation with statistical process controls.
Note 3: See Thermal Considerations.
Note 4: Supply current includes PROG pin current (approximately 100µA) but does not include any current
delivered to the battery through the BAT pin (approximately 100mA).
Note 5: This parameter is not applicable to the LP4060AX.
Note 6: ITERM is expressed as a fraction of measured full charge current with indicated PROG resistor.
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Layout Considerations
Follow the PCB layout guidelines for optimal performance of LP4060A.
For the main current paths as indicated in bold lines, keep their traces short and wide.
Put the input capacitor as close as possible to the device pins (VIN and GND).
Connect all analog grounds to a command node and then connect the command node to the power
ground behind the output capacitors.
SOT23-5