The Implication of Synchronous Rectifiers

to the Design of Isolated, Single-Ended

Forward Converters
By Christopher Bridge

ABSTRACT
Synchronous rectification is a commonly used technique to improve the efficiency of DC/DC converters
with low (<=5V) output voltages and high output currents. Control of the synchronous rectifiers in
forward converters has been accomplished in many different ways, from self-driven to complexly
controlled techniques. Most existing control techniques allow the synchronous rectifier’s body diode to
conduct for some small time interval, thus degrading efficiency. The focus of this design review is a new
control technique that virtually eliminates body diode conduction in synchronous rectifiers.
Measurement results from a 30W resonant reset forward converter will complement the paper.

reported[2]. As a result, the only major decision

I. INTRODUCTION the designer is left with is how to control the
Forward converters have traditionally been synchronous rectifiers.
used for low output voltage DC/DC converters,
particularly for the telecom input voltage range II. FORWARD CONVERTER WITH DIODE
of 36 to 75V. The reasons behind this topology RECTIFICATION
choice are many and varied. The forward
converter has only a single primary side switch, A. Transformer Reset Options
which is ground referenced, and several Before discussing synchronous rectification,
transformer reset methods are available. The it would be beneficial to look at the forward
control loop dynamics are well understood by converter using conventional diode rectification.
extending the control models of standard buck The basic power stage of a forward converter
converters. Although the forward topology has with diode rectification is shown in Fig. 1.
been quite popular, it has limitations. As the
output voltage is decreased, the efficiency of the +
forward topology becomes limited by the output +

rectifier’s loss. The rectifier loss, which is

essentially the forward drop of the rectifier times RESET
DR VOUT

the output load current, becomes the dominant

loss in the converter in high current, low voltage
applications. Although there have been good VIN DF

improvements in Schottky diode technology, +

VDSQ1
synchronous rectification is needed to realize
higher efficiency. Q1

Manufacturers of power MOSFETs have

responded by marketing very low on resistance, Fig. 1. Forward converter with diode rectification.
low voltage devices in compact packages.
MOSFETs suitable for synchronous rectification
with less than 3mΩ on resistance have been

7-1
 Therefore, in the R-C-D clamp, the
magnetizing current will cycle between negative
and positive peak values, which are not
necessarily equal to one half of the peak-to-peak
magnetizing current. In the traditional Third
Winding Reset technique, the magnetizing
current is first reset to zero by the third winding,
but resonance between the magnetizing
(a) RESONANT RESET inductance and the COSS of Q1 will drive the
magnetizing current negative. This negative
magnetizing current will play an important role
when synchronous rectification is applied to the
forward converter.
Waveforms that show the primary MOSFET
Q1 drain-to-source voltage and the transformer
magnetizing current for an R-C-D Clamp
forward converter are shown in Fig. 3.
(b) R-C-D CLAMP
VC

VI

VDRAIN

Impk

IM
IMC
0 L
(c) THIRD WINDING

Fig. 2. Possible reset mechanisms. Imng

t0 t1 t2 t3 t4 t5 t0
There are several possible reset mechanisms,
as shown in Fig. 2. These are (a) Resonant Reset, Fig. 3. Primary MOSFET Q1 drain-to-source
(b) R-C-D Clamp, and (c) Third Winding. voltage and the transformer magnetizing current
While all of these techniques allow for for an R-C-D clamp forward converter.
resetting the transformer magnetizing current Two time intervals are of particular interest.
during the off time of the main switch Q1, the First is the interval from t1 to t2, where the
method and the amplitude to which magnetizing transformer leakage inductance resonates with
current is reset is different for each topology. In the primary side capacitances and second, the
the Resonant Reset technique, the magnetizing dwell interval from t5 to t0.
current is reset to negative amplitude through the At t1, the drain voltage on the primary side
resonant capacitance, which is primarily equal to MOSFET reaches the input voltage. At this time,
the COSS of Q1 added to the junction capacitance the current on the secondary side is flowing
of DF [1]. This negative value is equal to one-half through the forward diode DF and the
the peak-to-peak magnetizing current. The R-C- transformer has zero volts across both the
D clamp is very similar, except that it is the primary and secondary windings. Right after t1,
clamp voltage that drives the transformer the freewheeling diode DR starts to conduct some
magnetizing current negative. current and the current in DF starts decreasing so
that the total current flowing in the two diodes is

7-2
equal to the inductor current. As soon as DR
begins to conduct current, the transformer
secondary is shorted by the conduction of both VI=48V
diodes. With the transformer secondary shorted, IO=1.0A
the magnetizing current is constant while the
total transformer leakage inductance resonates
with the primary side capacitances. During this VDRAIN
50V/div
resonance, the transformer primary current
decreases from a peak value of the peak
magnetizing current plus the reflected inductor
current to the peak magnetizing current. The ILM
secondary current changes from the peak 200mA/div
inductor current to basically zero current. Since
the primary and secondary currents change
during the resonance seen on the primary side, 200ns/div
the current transfer from DF to DR is complete
after a half-resonant cycle is seen on the primary Fig. 4. Primary MOSFET Q1 drain-to-source
side MOSFET drain voltage. At t2, the voltage voltage and transformer magnetizing current.
across DF starts to resonate, as DF is reverse
biased. Put another way, the transfer of current
VI=30V
between the rectifiers is controlled by the total IO=0.5A
transformer leakage inductance and the primary VDRAIN
50V/div
side capacitances. As seen by the secondary side,
this adds a delay between the primary side gate IPRIMARY
drive signal and the voltage across DF 500mA/div
resonating.
The dwell time interval from t5 to t0 will be
very important when synchronous rectification is ISECONDARY
used in the forward converter topology. As 500mA/div
described earlier, the transformer has negative
magnetizing current at this time, i.e. current is
flowing out of the dotted terminal in Fig. 1.
Recognizing that this current cannot flow on the 200ns/div

primary side, the magnetizing current must flow Fig. 5. Primary MOSFET Q1 drain-to-source
on the secondary side through DF. At t5, the voltage and transformer primary and secondary
primary side switch drain voltage has resonated currents.
down to the input line voltage, and is clamped by
the forward diode conducting the magnetizing
B. Rectifier Reverse Recovery and Conduction
current. The forward diode conducts the
Losses
magnetizing current throughout the dwell time
Prior to Q1 being switched on, the inductor
interval, until the primary side MOSFET is
current is flowing mostly through DR, which has
switched on at t0.
stored junction charge. Because this charge
Experimental waveforms from[1] for the
cannot be removed instantaneously, the anode-
primary side MOSFET drain voltage and the
to-cathode voltage will remain constant as Q1 is
transformer magnetizing current are shown in
switched on. The input voltage is then placed
Fig. 4. Fig. 5 shows both the transformer’s
across the transformer leakage inductance and
primary and secondary currents as well as the
the current in DR decreases at a rate determined
drain-to-source voltage of the primary side
by the input voltage and leakage inductance.
MOSFET.
The input voltage magnitude and the transformer
7-3
leakage inductance determine the dI/dt in DR and III. SELF-DRIVEN SYNCHRONOUS
therefore also determine the reverse recovery of RECTIFICATION
DR. After the stored charge is removed from DR, The self-driven drive scheme is the simplest
the transformer leakage inductance resonates synchronous rectifier drive scheme and is
with the junction capacitance of DR. pictured in Fig. 6.
The forward diode also experiences reverse The two diodes DF and DR are replaced with
recovery. This occurs at t2 in Fig. 3, immediately MOSFETs QF and QR. In the self-driven
after the current is commutated from DF to DR. technique, the voltage across the transformer
As discussed earlier, the dI/dt in both DF and DR secondary is used to drive the gates of the
is set by the resonance between the transformer synchronous rectifiers QR and QF. Although not
leakage inductance and the primary side resonant shown in Fig. 6, separate windings on the
capacitance. As the current is decaying to zero in secondary side of the transformer can be used to
the forward diode DF, the dI/dt is decreasing in drive the forward synchronous rectifier QF and/
magnitude, which makes the reverse recovery of or the freewheeling synchronous rectifier QR[3,4].
DF less severe than the reverse recovery of DR. This is usually done to allow a different turns
Schottky diodes naturally have excellent reverse ratio from the primary winding to the gate drive
recovery characteristics, and when these are used winding(s), allowing synchronous rectification to
for DF, the reverse recovery will be barely be used for higher or lower output voltages.
noticeable; however, when MOSFETs are used
in place of DR and DF, the poor reverse recovery
characteristics of the body diodes will become
apparent.

+
+

RESET
VOUT
QR

VIN
+
VDSQ1
QF
Q1

Fig. 6. Forward converter with self-driven synchronous rectifiers.

7-4
 change over line variations, meaning that the
A. Implications and Trade-Offs of Self-Driven dwell time interval will be 0.5 ·DMAX. It becomes
Synchronous Rectification for Resonant Reset clear then, even for converters operating at a
Forward Converters. maximum of 50% duty cycle that the dwell time
Fig. 7 displays the waveforms for a resonant interval will be as high as 25% of the entire
reset forward converter with self-driven switching cycle.
synchronous rectifiers operating in continuous Looking again at Fig. 7, during the dwell
conduction mode. Shown are the drain-to-source time interval, the body diodes of both QF and QR
voltages of QF and QR, as well as the primary are conducting. The forward MOSFET is
side MOSFET Q1 drain-to-source voltage. conducting the reflected negative magnetizing
VDSQ1 current, while the freewheeling MOSFET carries
VDSQF = VGSQR the difference of the inductor and the forward
VDSQR = VGSQF MOSFET currents. Conduction of the QR body
diode for this long time interval is very
undesirable as the losses will be high. Also, since
the body diode is carrying a large current, the
reverse recovery will be severe when the primary
DWELL
TIME
side MOSFET Q1 is turned on. The forward
0V
INTERVAL MOSFET will also experience conduction losses
during the dwell time interval due to the
conduction of the magnetizing current through
the body diode. However, since the magnetizing
0V current is usually much smaller than the load
current, this loss isn’t as high as in the
0.7 V freewheeling switch.
A second problem with self-driven
synchronous rectification is the RDS(on) variation
0V
over the line voltage range. Low voltage
0.7 V
MOSFETs suitable for self-driven synchronous
rectification typically have an RDS(on) rated at
Fig. 7. Typical waveforms for self-driven VGS = 4.5V, and an absolute maximum VGS of
synchronous forward converters with resonant ±20V. The gate of the forward synchronous
reset. rectifier QF is driven with a voltage proportional
The first problem with self-driven to the line voltage, while the freewheeling
synchronous rectification is the conduction MOSFET gate is driven by a constant voltage
intervals for the body diodes of QF and QR. In an during the reset of the power transformer. The
optimum converter, the resonant reset will occur designer must select a turns ratio NP/NS for the
during the entire off-time of the primary side main power transformer low enough for the
MOSFET Q1, meaning that at low input line, the forward synchronous rectifier to be driven into
Q1 drain voltage will just return to the input its ohmic region at low line. The design tradeoff
voltage before Q1 is turned on again. At low line, occurs at high line, where it is possible to exceed
the converter will be operating at the maximum the maximum gate-to-source rating of the
steady state duty cycle, DMAX, for the converter. forward synchronous rectifier MOSFET. For the
Assuming that the converter is to be designed standard telecom input rage of 36 to 75V, a
over a 2:1 input range, and that the duty cycle reasonable choice for the turns ratio NP/NS is
will be inversely proportional to the input line approximately 6:1. At low line, this will give
voltage, the steady state operating duty cycle at approximately 6V VGS on the forward
high line will be 0.5 ·DMAX. In resonant reset synchronous rectifier that will increase to
converters, the reset time interval does not approximately 12.5V at high line. A close

7-5
examination of the MOSFET datasheet shows a Therefore, over a 2:1 line voltage change, the
significant RDS(on) change over this VGS range. average current required to drive the forward
For some MOSFETs this change can be as high synchronous rectifiers will also change 2:1.
as 10%. If the transformer turns ratio NP/NS is Since the freewheeling synchronous rectifier is
higher than 6:1, the RDS(on) variation will also be driven with a constant gate-to-source voltage, the
higher because the RDS(on) increase significantly charge and average current required is constant
at gate-to-source voltages less than 6V. over the line voltage.
In self-driven synchronous rectification, the Another drawback of using self-driven
gates of the synchronous rectifiers are driven synchronous rectifiers in place of diode
directly from the transformer. The current to turn rectification is the loading of the resonant reset
the rectifiers on and off comes efficiently from circuit. Fig. 8a shows the capacitances of the
the input line. The average current to drive the resonant circuit, and Fig. 8b shows the
forward synchronous rectifier will vary equivalent resonant capacitances and inductances
proportionally to the switching frequency and reflected to the primary side.
proportionally to the gate-to-source voltage.

+
+
L
CXMFR M QR VOUT

CGSQR

+
VIN VDSQF

COSSQF

COSSQ1
(a)

NP/NS

COSSQF CGSQR LM
RP
N2 N2 CXMFR

LLK

VDSQ1

+
Q1 COSS
(b)

Fig. 8. Capacitances of the resonant circuit (a) and equivalent resonant capacitances and inductance
reflected to the primary side (b).

7-6
 During the reset time interval, the VDS of QF
PWM
has a resonant half-sine wave voltage on it. It can CONTROL

be seen that the gate-to-source capacitance of QR

and the COSS of QF will load the resonant reset
circuit. The net effect of this loading is to extend Q1 VGS

the time duration of the reset time interval,

assuming the transformer magnetizing VGS QR
inductance is kept constant. If the duty cycle
needs to be kept constant after adding the self-
driven synchronous rectifiers, the magnetizing VGS QF

inductance may have to be decreased, which will

result in a shorter reset time, and a higher peak
reset voltage. Decreasing the magnetizing
inductance will also increase the circulating VDS QF

losses, as more energy will be stored in the

transformer.
VDS QR

IV. CONTROL-DRIVEN SYNCHRONOUS Fig. 9. Control-driven synchronous rectification

RECTIFICATION waveforms.
After examining the self-driven technique, Why not drive the forward synchronous
attention turns to control-driven synchronous rectifier QF with the PWM CONTROL signal,
rectification. Control-driven techniques are and the freewheeling synchronous rectifier QR
generally more complex than self-driven; with an inverted PWM CONTROL signal? The
however, control-driven techniques can answer lies first in the time delay between the
overcome all the limitations of self-driven PWM CONTROL signal and changes in the
techniques. Body diode conduction can be power stage voltages and currents. When the
eliminated and using precise timing circuitry can PWM CONTROL signal originates on the
minimize reverse recovery losses. Furthermore, secondary side, it is too far time advanced from
the gate drive voltage can be set to an optimum changes in the power stage voltage and currents.
level to minimize RDS(on) while minimizing the However, if the PWM CONTROL signal is
gate charge required. The gate drive voltage can primary side referenced, it must be brought
be regulated independent of the line voltage. All across the isolation boundary. Depending on
of these benefits come with the cost of added how the PWM CONTROL is transmitted from
control complexity. the primary to the secondary side, the resulting
Knowing the limitations of self-driven signal on the secondary side may be too far time
synchronous rectification, begin by drawing the advanced or time retarded. Also, as described
desired waveforms for the synchronous rectifier previously, it would be desirable to allow both
gates with respect to the available control synchronous rectifier channels to conduct during
signals. Fig. 9 shows the two synchronous the dwell time interval. Unfortunately this
rectifier gate-to-source voltages, drain-to-source requires overlapping gate drive signals. The time
voltages, as well as the primary side drain-to- interval when both rectifiers are conducting will
source voltage and PWM CONTROL signals. vary with line voltage and any changes in
Note that the PWM CONTROL signal could parasitic capacitances and inductances. Possibly
be either primary or secondary side referenced, it the optimal solution then, is to use power stage
makes no difference to the waveforms in Fig. 9. information to determine when the forward
synchronous rectifier should be turned on.
Examining Fig. 9 closely, QF should be turned
on exactly when its drain-to-source voltage
reaches zero volts. This would allow the
7-7
magnetizing current to be conducted by the take the output signal from. Finally, the AND
channel instead of the body diode, eliminating gate ensures that the delay is applied to the turn-
the conduction loss of the body diode. If QF is on (rising) edge only. Control of the delay from
turned on at this time, it will remain on when the IN to OUT is performed by the digital control
primary side MOSFET Q1 is turned on, and the bus applied to the MUX address input. If the
turn off of QF will need to be synchronized to the control bus is set to all ones, a maximum delay is
turn off of Q1. seen from IN to OUT. Conversely, if the control
Control of QR needs to be synchronized to bus is set to all zeros, there is practically no
the rectified transformer voltage. As soon as the delay from IN to OUT. Several different delay
transformer voltage that is rectified by QF falls to blocks can be constructed, giving either a turn-on
zero volts, QR needs to be turned on. Ideally, the delay only, a turn-off delay only or symmetric
gate-to-source voltage of QR would be turn-on and turn-off delays. Not shown in Fig. 10
approaching its threshold voltage as the drain-to- is a voltage sensing circuit and digital controller.
source voltage of QR is falling to zero. This For different implementations of the delay cell,
would allow for minimum body diode different voltage sensing circuits and digital
conduction of QR during this time interval. The controllers will be used.
turn off of QR is a very different situation. In the DELAY LINE WITH 2n ELEMENTS
self-driven technique, the channel of QR is turned
IN
off as the resonant voltage across the drain-to- 2n
source of QF falls below the threshold voltage of 2n MUX

QR. The current that was flowing through the DELAY BUS OUT
channel of QR now must flow through the body n
diode, and when Q1 is turned on, a high loss CONTROL BUS
reverse recovery will take place. With control-
driven synchronous rectification, the goal is to IN
minimize this body diode conduction by actively
controlling the turn off of QR. OUT
tDELAY

V. CONTROL-DRIVEN IMPLEMENTATION
Fig. 10. Delay block.
To minimize conduction and reverse
recovery losses, the synchronous rectifiers
A. Control-Driven QR Implementation
require precise timing circuitry. Although there
The control-driven circuit design starts with
are several ways to generate these control
the freewheeling MOSFET QR, which should be
signals, a feedback system to actively control the
turned on as soon as its drain-to-source voltage
timing of the gate drive signals will be used. The
falls to zero. One simple way to accomplish this
key advantages are that the circuit will adjust for
would be to use a comparator to sense when the
component variation, particularly the
drain-to-source voltage of QR crosses zero volts.
uncontrolled capacitances in the synchronous
The problem with this method arises when the
rectifier MOSFETs, and timing delays and the
delay through the comparator, logic, and gate
temperature dependence of MOSFET thresholds
driver are considered. Even with very fast
are also corrected for by this feedback loop.
circuitry, this delay can amount to 50ns or more,
To control the gate timing, the programmable
during which the body diode is conducting and
delay block pictured in Fig. 10 will be used. This
incurring high conduction losses. One logical
delay block is comprised of three main elements;
answer to the inherent time delay from sensing
a delay line, a multiplexer (MUX), and a logic
the falling drain-to-source voltage to when the
AND gate. An input signal to the delay line is
MOSFET is turned on is to use information from
delayed several nanoseconds for each delay
the last switching cycle to predict when to turn
element. In order to generate a controlled turn-on
on the MOSFET. In this anticipatory way, the
delay, the MUX selects which delay element to
7-8
MOSFET gate voltage can start increasing maximum turn-on delay and minimum turn-off
before the drain-to-source voltage has fallen. By delay. With the delays set to these values, the
timing the gate voltage to rise to the MOSFET body diode of QR will conduct, and the feedback
threshold voltage when the drain-to-source loops will start to adjust the delays to minimize
voltage is falling to zero volts, the body diode its conduction. Fig. 12 (a) and (b) shows the
should never conduct. gate-to-source and drain-to-source voltages of
Fig. 11 shows the control circuitry to turn QR QR during the turn-on of QR. Fig. 12 (a) shows
on and off. It uses two multiplexers, two the circuit operation when the turn-on of QR is
counters, one delay line and glue logic to control delayed too long, and Fig. 12 (b) shows optimal
the turn-on and turn-off so that body diode timing delay.
conduction is minimized. The circuit description To adjust the turn-on delay, a NOR gate with
will begin with the turn-on delay portion. The an approximate input threshold of 2V is used to
PWM CONTROL signal drives the primary side detect when the gate-to-source voltage and drain-
MOSFET Q1 and is also fed into the delay line. to-source voltage of QR are both simultaneously
When the power supply is first started, the low. A high output from the NOR gate indicates
LOAD input to the counters is high which sets to the controller that the delay was too long, and
the turn-on delay counter to all ones, and sets the the controller will decrease the delay for the next
turn-off delay counter to all zeros. With the switching cycle.
counters initialized in this state, the output from
the control circuit to the gate driver results in

DELAY LINE
PWM CONTROL
PWM CONTROL IN TURN-OFF
DELAY MUX
Q [15:0]
INPUT
FROM
CONTROL

QR_CONT

TO GATE
SET1 DRIVER

2V THRESHOLD S TURN-ON
VGS_QR D Q DELAY MUX
TURN-ON COUNTER
DFF
CLK Q UP/ DN
R
PWM CONTROL CLK Q [3:0]
VDS_QR
LOAD LOAD SETS Q = 1
GND
PWM CONTROL
INPUTS
FROM
SET1
POWER TURN-OFF COUNTER
STAGE
S
BODY DIODE D Q UP/ DN
COMPARATOR
DFF PWM CONTROL CLK Q [3:0]
VDS_QR
CLK Q LOAD LOAD SETS Q = 0
+ R

–300 mV
GND
PWM CONTROL

Fig. 11. QR control circuitry.

7-9
 VDSQR
this current is quite high, and ringing is usually
VGSQR seen on the drain-to-source voltage of QR. If a
NOR GATE OUTPUT comparator is used for detecting the body diode
conduction during the turn-on of QR, there could
V
be false triggering due to the ringing drain-to-
source voltage. During the turn-off of QR, the
current is constant through the QR MOSFET
device, as the current is flowing through either
2V
the channel or the body diode. There is very little
0V t ringing during the turn-off, and a comparator is
used for improved accuracy. The threshold of the
(a) NON-OPTIMAL
comparator must be slightly negative to prevent
V false triggering of the comparator when the
MOSFET channel is conducting.
The drain-to-source voltage during channel
2V conduction is approximately equal to
0V t -ILOAD·RDS(on), and allotting for noise, the
comparator threshold is set to approximately
(b) OPTIMAL
-300mV. The comparator compares the drain-to-
Fig. 12. QR turn-on waveforms. source voltage of QR to this fixed threshold and a
high output from the comparator indicates to the
The NOR gate output is latched, inverted,
controller that the body diode is conducting and
and is fed into the turn-on delay counter’s
the delay needs to be increased. This is exactly
UP/DOWN input. This signal tells the counter to
opposite from the turn-on scenario, because the
either count up or count down. If the NOR gate’s
turn-off delay counter is set to all zeros at start-
output was high, then the counter will count
up. Fig. 13 (a) and (b) show the turn-off
down, decreasing the delay, while a low NOR
waveforms for QR and the comparator output.
output will result in the counter counting up,
increasing the delay. The counter effectively VDSQR
VGSQR
holds this delay information for the next cycle. COMPARATOR OUTPUT
The feedback loop will then adjust the turn-on
delay to be shorter until the NOR gate no longer V
has an output pulse. When the converter is
operating at a constant load and line, the turn-on
delay for the next cycle will be slightly too long,
the NOR gate will give a high output pulse, and
the delay will be shortened. In this way, the 0V t

circuit dithers the delay between two values, one -0.3V

(a) NON-OPTIMAL
too long, and one very close to optimum.
The turn-off controller operates in a very V

similar manner to the turn-on controller. The

differences reside in the voltage sensing circuit
and the direction that the counter counts. A high
speed comparator is used to sense when the body
t
diode is conducting. For improved accuracy, a
comparator is used to detect body diode (b) OPTIMAL

conduction instead of the NOR gate. During the Fig. 13. QR turn-off waveforms.
turn-on interval, current is commutating from the
forward synchronous rectifier to the Fig. 13 (a) shows the circuit operation when
freewheeling synchronous rectifier. The dI/dt of the delay is set too short, and Fig. 13 (b) shows

7-10
optimal timing delay. As in the turn-on of QR, B. Control-Driven QF Implementation
the delay for the turn-off dithers between a value Control of the forward synchronous rectifier
that is too long and an optimum value. QF is quite different than the freewheeling
The question arises: can the turn-on or turn- synchronous rectifier QR. One main difference is
off delays be set too short, causing cross- that the goal is to turn on QF after the
conduction? The answer lies in a careful study of transformer is reset, which is independent of
the comparator performance and the delay per either the rising or falling edge of the PWM
element of the delay line. Comparators can only CONTROL signal. This is unlike the
respond to differential input voltages that are freewheeling synchronous rectifier, where the
present for a sufficient amount of time to slew goal was to simply adjust the timing of both the
internal nodes. Suppose the comparator can rising and falling edges of the PWM CONTROL
detect body diode conduction for 5ns. During the signal as needed to minimize body diode
next cycle, the delay is adjusted to reduce the conduction in QR
diode conduction by one bit on the delay line. Of With the understanding that the goal is to
course, the comparator will not respond to the turn on QF after the transformer is reset, a good
next-cycle body-diode conduction because it will starting point is the circuitry required to turn on
be approximately 5ns minus the delay time per QF as shown in Fig. 14.
element on the delay line. The key to avoiding First, a high-speed body diode comparator is
cross conduction is to set the delay per element used to detect when the body diode of QF starts
less than the minimum detectable pulse width of to conduct, which signals the end of the
the comparator. transformer reset time interval. Unfortunately, as
shown in Fig. 15, this comparator will also detect
body diode conduction right after the primary
side MOSFET Q1 is turned off.
DELAY LINE

PWM_CONTROL IN
Q [15:0]
PWM_CONTROL TURN-OFF DELAY MUX
INPUT
FROM
CONTROL
2V THRESHOLDS
SET1
VGS_QF TURN-OFF COUNTER MUX_OUTPUT
S
D Q UP/ DN
VDS_QR
DFF PWM_CONTROL CLK Q [3:0]
GND CLK Q LOAD LOAD SETS Q = 0
R
LOAD
INPUTS
FROM
POWER PWM_CONTROL PRE-CONDITION LATCH
STAGE
S
SET1 D Q
LOW SPEED
COMPARATOR DFF QF CONTROL LATCH
+
CLK Q
2.5 V R S
SET0 D Q QF_CONT
VDS_QF LOAD
GND DFF
TO GATE
MUX_OUTPUT CLK Q
R DRIVER
HIGH-SPEED BODY DIODE
COMPARATOR
+
LOAD
300 mV LOAD
GND

Fig. 14. QF control circuitry.

7-11
 The control for the turn-off of QF is quite
similar to the turn-on of QR. The turn-off circuit
uses the predictive control technique, using a
delay line, multiplexer and a counter as the
controller. The differences between the control
of the turn-off of QF and the turn-on of QR start
VDS QF with the type of logic gate used for the feedback
2.5 V
loop. As shown in Fig. 14, the gate-to-source
COMP OUTPUT voltage of QF is inverted and fed into a 2-input
AND gate. The other input to the AND gate is
HIGH SPEED
BODY DIODE connected to the drain-to-source voltage of QR.
COMP OUTPUT Both the inverter and the AND gate have
PRECONDITION
approximately 2V input thresholds. This AND
LATCH Q gate will synchronize the falling edge of QF’s
gate-to-source voltage with the falling edge of
Fig. 15. QF pre-condition latch waveforms. QR’s drain-to-source voltage.
Using the comparator alone would turn on QF
VGSQF
for the entire off time of Q1, and the transformer V
VDSQR
would never be allowed to reset. To avoid this, a AND OUTPUT
low speed comparator is used to detect when the
drain-to-source voltage of QF has risen above 2V

2.5V. When the drain-to-source voltage of QF 0V

has risen above 2.5V, a pre-condition latch is set,

which then enables the output of the high-speed
body diode comparator. As soon as the drain-to- 2V
source voltage of QF falls past the –300mV 0V
threshold of the body diode comparator, QF is
turned on by setting the QF control latch. As
soon as the high-speed comparator output goes
high, the pre-conditioning latch is reset, and the t
(a)
turn-on circuitry is in the proper state for the next
turn-on event. During the inherent delay from the
body diode comparator detecting the conduction
VDSQR
of the body diode, to the channel of QF turning
VGSQF
on, the body diode conducts the magnetizing V
AND OUTPUT
current of the transformer. Although during this
time interval there is conduction loss in the QF
body diode, this is minimal compared to the loss 2V

incurred if QF was held off for the entire dwell 0V

time period. To eliminate this loss completely,

one would have to use the same predictive
control that was used for the turn-on of QR. 2V

Although this is possible in theory, it is quite 0V

difficult because there is no PWM CONTROL

edge present when the transformer has
completely reset. t
(b)

Fig. 16. QF turn-off waveforms.

7-12
 A counter that has its output initially set to
all zeros controls the turn-off circuit. With the VI. PROTOTYPE CIRCUIT
counter’s output set to all zeros, virtually zero A prototype converter was constructed to
delay is set between the falling edge of the PWM verify the theoretical predictions. The tested
CONTROL signal and the gate-to-source voltage converter operates from a 36V to 75V input line
of QF. The resulting gate-to-source voltage of and converts this input to a 2.5V output at up to
QF, drain-to-source voltage of QR and the AND 12A. The converter’s block diagram is shown in
gate output are shown in Fig. 16 (a). Fig. 17.
The AND gate in the QF turn-off circuit acts The operating frequency is fixed at 500kHz
much like the NOR gate did in the QR turn-on by a secondary side voltage mode controller. The
control circuit, giving a command to the counter Resonant Reset method is used to reset the
that directs the counter to count up or down. In power transformer. The breadboard is designed
the case of the QF turn-off circuit, a high output so that both self-driven synchronous rectification
from the AND gate directs the counter to count and the control-driven techniques can be
up at the next clock cycle. When the counter investigated.
increments up one count value for the next cycle, A block diagram of the secondary side
the delay between falling edge of the PWM control circuitry is shown in Fig. 18.
CONTROL and the gate-to-source voltage of QF The signals from the power stage are shown
is increased, and the output pulse from the AND on the left; these are level shifted down to 0V to
gate will be narrower. This feedback effect will 3.3V signals for the logic. The power stage
continue until the gate-to-source of QF and the signals are input into Alteraâ MAX7000A
drain-to-source of QR are synchronized. When electrically programmable logic devices (EPLD),
the delay is optimum, the waveforms are as which contain all the control logic for the
shown in Fig. 16 (b). synchronous rectifiers. This allows for maximum
As described in the QR control flexibility when developing the logic to process
implementation, the circuit will dither between the power stage signals and to output the desired
two delay values, one that is optimum and one gate drive signals. To level shift between the 0 to
slightly longer than optimum. 3.3V logic signals and the 8V gate drive rail,
high-speed 4 transistor level shifters are used.
TPS2812 8-pin IC gate drivers were used with
both drivers in each package paralleled for
higher output current drive.
1.2 mH
PULSE P8205T PAYTON 9225

+ +
3300 pF QR 2.5 V
6 1
VIN 2xFDS6670A 12 A

3300 pF 1.6 W
Q1
IRF630S 1.6 W

PULSE 2xFDS6680
PA0115
VDSQF VGSQF VGSQR VGSQR

PRIMARY
SECONDARY SIDE CONTROL
CONTROL

Fig. 17. Simplified prototype schematic.

7-13
 PWM
CONTROL DELAY LINE AND 3.3 V TO 8 V TPS2812
VGSQF
VDSQF LOGIC FOR QF LEVEL SHIFTER DRIVER
(FIGURE 14)
LOAD

DELAY LINE AND

3.3 V TO 8 V TPS2812
LOGIC FOR QR VGSQR
VDSQR LEVEL SHIFTER DRIVER
(FIGURE 11)

Fig. 18. Secondary side control block diagram.

To minimize the RDS(on) of the synchronous signal and the falling edge of the drain-to source
rectifiers, while reducing the gate charge voltage of Q1. Likewise, the delay for the turn-
required, an 8V power rail is used for the gate off of Q1 is significant and not the same as the
drivers. The outputs of the gate drivers were also turn-on delay.
level shifted down and input back into the logic
devices. No gate drive resistors were used for VDSQ1 20 V / div
either synchronous rectifier.
PWM CONTROL 5 V / div
The three counters required for both the QR
and QF control circuits are 4 bits wide, which
results in a delay line with 16 elements. These
delay lines are implemented with 16 bit bus
drivers, part number 74AHC16244, with all
sixteen drivers connected in series. The outputs
from the 16 drivers are fed into the EPLDs that
contain the multiplexers and all other logic.
Since the delay lines are CMOS integrated
circuits, the delay per element of the delay line
can be adjusted by simply changing the supply
voltage. For this circuit, setting the supply
voltage to the delay line IC to approximately
2.7V set the delay per element to approximately
4ns. Using 4ns per delay line element is a
tradeoff between dynamic range, meaning the
maximum delay that can be commanded, the 500 ns / div
closed loop accuracy of the feedback loop, and
the incremental power loss. Fig. 19. Resonant reset waveforms.
Waveforms for self-driven synchronous
VII. MEASUREMENT RESULTS rectification are shown in Fig. 20. These
waveforms were taken at an input voltage of 48V
A. Waveforms and a load current of 3A. Note the delay from the
Fig. 19 shows the primary MOSFET drain- PWM CONTROL signal to the drain-to-source
to-source voltage and the PWM CONTROL voltages of QF and QR. During the dwell time
signal. The control signal is taken before the interval, the body diode conduction of QF and QR
primary side gate driver. Note the inherent delay is clearly visible. Since these waveforms were
between the rising edge of the PWM CONTROL taken at 48V, the dwell time interval is a small

7-14
portion of the PWM period. At high line of 75V, VDSQF 5 V / div VDSQR 5 V / div
the dwell time extends considerably, increasing
the losses in both QR and QF.
The waveforms for control-driven synch-
ronous rectification are shown in Fig. 21. From
the top to the bottom are the drain-to-source of
QR, drain-to-source of QF, gate-to-source of QF,
and gate-to-source of QR. Both gates are
controlled with the predictive delay circuitry
described in this paper. A couple of interesting
points can be observed. First, the gate-to-source
voltage of QF has a resonant voltage present
during the off time of QF. This is due to the
resonant drain-to-source voltage on QF coupling
through the gate-to-drain capacitance of QF.The
resulting voltage seen on the gate is due to the
resonant current through the driver’s pull down
resistance. The gate drive waveforms have the 500 ns / div
VGSQF 10 V / div
necessary overlap to minimize the loss when QF VGSQR 10 V / div
conducts the transformer magnetizing current
Fig. 21. Control-driven synchronous
during the dwell period.
rectification waveforms.

VDSQR 5 V / div
VDSQR 5 V / div
VGSQR 2 V / div
VDSQF 5 V / div
VGSQF 2 V / div
PWM CONTROL 5 V / div

20 ns / div
500 ns / div
Fig. 22.QR turn-on waveforms.
Fig. 20. Self-driven synchronous rectification
waveforms.

7-15
 Notice the magnified waveforms at each VGSQF 2 V / div
synchronous rectifier turn-on and turn-off
VDSQF 5 V / div
transition, starting with QR. In Fig. 22, the drain-
to-source voltage of QR as well as the gate-to-
source voltage of both QR and QF is shown. As
the drain-to-source voltage of QR falls, QF is
being turned off, and QR is being turned on. The
timing for the turn-on of QR and the turn-off of
QF is being actively controlled by the feedback
loops. Note that minimal body diode conduction
exists on the drain-to-source voltage of QR.
The turn-off waveforms for QR are shown in
Fig. 23. During the turn-off of QR, the high-
speed comparator senses body diode conduction
and the feedback loop adjusts the gate timing to
eliminate this conduction. The drain-to-source
voltage waveform shows virtually no body diode
conduction whatsoever. This waveform shows an
optimum turn-off of QR. 50 ns / div
The turn-on waveforms for QF are shown in
Fig. 24. The turn-on of QF is controlled without Fig. 24. QF turn-on waveforms.
using the predictive delay circuit, so body diode
conduction is expected due to propagation
delays. A high-speed comparator detects QF’s
body diode conduction and turns on the gate.
The resulting body diode conduction interval is
seen to be approximately 50ns. VGSQF 2 V / div

VDSQR 5 V / div VDSQF 2 V / div

VGSQR 2 V / div VGSQR 5 V / div

20 ns / div 20 ns / div

Fig. 23. QR turn-off waveforms. Fig. 25. QF turn-off waveforms.

7-16
 The turn-off waveforms for QF are shown in Fig. 26 shows the measured efficiency over a
Fig. 25. The predictive delay circuit shown in 2A to 12A load range for the three control
Fig. 14 controls the turn-off of QF to minimize techniques, all at the nominal 48V input.
the body diode conduction. Note that there is 90
minimal body diode conduction seen on the
drain-to-source voltage of QF.
86
B. Efficiency

EFFICIENCY (%)
A major goal of this topic is to compare the
efficiency of the two control methods, self-
driven and control-driven. It becomes clear that 82
there is a third possibility, where control-driven
techniques are used for QR, and the self-driven
technique is used for QF. This “hybrid” control 78
scheme has merits of simpler control which CONTROL-DRIVEN
would use less circuitry, as well as the gate HYBRID
SELF-DRIVEN
charge for QF would be recycled to the load 74
instead of dissipated in the driver. The 2 4 6 8 10 12
drawbacks to this hybrid control technique are LOAD (A)
the body diode conduction loss of QF during the
dwell period, which in some applications may be Fig. 26. Efficiency vs. load current.
offset by the recycled gate charge of QF. The As might be predicted, the highest to lowest
efficiency of all three control techniques will be efficiency tracks the most sophisticated to least
explored over line and load variation. sophisticated control technique respectively. The
First, the setup for measuring efficiency is control-driven technique has the highest
critical to drawing conclusions from the efficiency, which peaks at 88.8% at 10A load
efficiency data. For the purposes of this paper, current and at full load is measured at a
the principal concern is power stage efficiency, respectable 88.3%. The hybrid control technique
including the synchronous rectifier gate drive also has excellent efficiency, measured at 88.5%
power. For this reason, the primary bias and gate at 10A load decreasing to 88.0% at 12A load.
drive current are ignored and not included in the The efficiency difference is due to the body
efficiency calculations. Therefore, for the self- diode conduction of QF during the dwell period.
driven technique, the efficiency is measured by The change in dissipated power between the
only including the power stage input current, control-driven and hybrid techniques is 400mW
while for both the hybrid and control-driven at full load. It needs to be recognized that the
technique the 8V synchronous rectifier gate- majority of this power is dissipated in the QF
drive bias current was included. Of course, the MOSFET, which only serves to increase the
8V bias current for the hybrid control is lower temperature rise and adversely affects reliability.
than the control-driven technique since only the Interestingly, the self-driven efficiency at
freewheeling MOSFETs are driven. For these light load is measured to be higher than either the
efficiency measurements, a lab power supply is control-driven or hybrid techniques. This can be
used for the synchronous rectifier gate drive explained by two effects, the recycling of gate
power supply. It is assumed that a suitable bias charge to the output and to the resonant tank
supply can be derived off the output choke or circuit. The synchronous rectifier gate charge
main power transformer in most applications. power is roughly independent of line and load,
which adversely affects efficiency at light loads.
Since the self-driven technique recycles this
charge, the light load efficiency is higher than
the control-driven and hybrid techniques.

7-17
Secondly, the forward body diode drop in the conduction of the QF body diode. This efficiency
synchronous rectifiers is lower at light load change represents a loss of 500mW at 72V line
currents, resulting in lower conduction losses. and 10A load current. As stated previously, this
Clearly, the recycled gate charge is offsetting the additional power loss is concentrated in the QF
additional body diode loss at these light loads. MOSFET.
Efficiency over a 2:1 line voltage change
with a fixed output current of 10A is shown in VIII. CONCLUSIONS
Fig. 27. The control-driven synchronous rectification
90 technique can deliver the highest efficiency of
the three techniques considered in this paper.
However, to obtain this efficiency, precise gate
88
timing is required for the synchronous rectifiers.
A unique predictive control technique that
EFFICIENCY (%)

86 automatically adjusts the gate timing for the

synchronous rectifiers was developed and
presented. This new control circuitry maximizes
84 the efficiency of the forward converter with
control-driven synchronous rectification. Texas
82 Instruments has filed for patent protection for the
CONTROL-DRIVEN entire content of this topic, including the control
HYBRID
SELF-DRIVEN techniques for both synchronous rectifiers. Two
80 products are in development that use the
36 42 48 54 60 66 72 techniques described in this topic. An 8 pin
LINE (V) synchronous buck driver IC for high current
DC/DC applications is under development with
Fig. 27. Efficiency vs. input line voltage.
the part number UCC37222. The UCC37223, a
It is important to realize that the dwell time secondary side synchronous rectifier driver IC is
interval is critical to the efficiency as the line also in development.
voltage is changed. The losses in the self-driven
technique will increase significantly as the line REFERENCES
voltage is increased, as the body diode of QR will
conduct for a longer time period every switching [1] Christopher D. Bridge, “Clamp Voltage
cycle. As the line voltage is increased with the Analysis for RCD Forward Converters”,
hybrid control technique, the body diode of QR APEC 2000.
will not conduct, but the body diode of QF will [2] STMicroelectronics Datasheet Part No.
conduct for a longer time period every switching STV160NF03L.
period during the dwell period. For the control-
driven technique, no change in losses due to [3] Philips Technical Note “25 Watt DC/DC
body diode conduction over line voltage Converter Using Integrated Planer
variation is expected. All of these predictions are Magnetics”.
supported with the data. We can see that the [4] Ionel Dan Jitaru, “High-Efficiency
efficiency is highest at low line for all three Rectification Techniques for Low Output
techniques. Switching losses, which increase as Voltage and High Output Voltage
the line voltage is increased, are the dominant Applications”, APEC Professional Seminar,
reason the efficiency decreases as the line 1999.
voltage is increased. The hybrid efficiency is
almost identical to the control-driven efficiency
at low line, but the efficiency drops
approximately 0.8% at high line due to the
7-18
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