What is ITF file in VLSI?

ITF - Interconnect Technology File. This file contains a description of the process crosssection
and connectivity section. It also describes the thicknesses and physical attributes of the
conductor and dielectric layers.

TLU+ File
It stands for Table Look Up file. TLU+ file is a binary file which is a kind model contains
advanced process effect that can be used to extract RC value from interconnects. The file
contains metal capacitance at different spacing and width in the form of a lookup table which
provides high accuracy and run-time.

The LEF (Library Exchange Format) file is the abstract view of cells. It only gives the idea about
PR boundary, pin position and metal layer information of a cell. To get the complete
information about the cell, DEF (Design Exchange Format) file is required.

The difference between logical exclusive and physical exclusive

There are usually multiple clocks in digital circuits. Some of these clocks are synchronized with
each other and need timing check, some are asynchronous and do not need timing check, and
some are mutually exclusive and need to be excluded. These relationships need to be declared
in the sdc to tell the tool which ones need to be checked and which ones are not.
The command set_clock_group in sdc is used to declare the relationship between clocks. The
specific usage is as follows:
1. Asynchronous clock, no timing check
For example, in the circuit shown in the figure below, if the two clocks C1 and C2 are
asynchronous, then there is generally no need to check this path.

At this point, you can use the following command to tell the tool:
set_clock_group -asynchronous -group C1 -group C2

2. logical exclusive
If there are two clocks in a circuit, but there is a selection signal to control the two clocks, as
shown below:
Such two clocks should be declared as logical exclusive. The command is as follows:
create_clock -period 10 -name C1 -waveform {0 5} [get_ports C1]
create_clock -period 20 -name C2 -waveform {0 12} [get_ports C2]
set_clock_groups -logically_exclusive -group C1 -group C2

3. physical exclusive
If two clocks are defined on the same port, it is impossible for the two clocks to exist at the
same time at the physical level. At this time, they need to be declared as physical exclusive.
For example, in the following circuit, since C1 and C2 are interactive between F3 and F4, and
between F1 and F2, it can only be C1-C1 or C2-C2, and C1-C2 or C2-C1 cannot appear.

At this time, you need to create two generated clocks at the output of MUX, and then declare
them as physical exclusive

create_clock -period 10 -name C1 -waveform {0 5 } [get_ports C1]

create_clock -period 20 -name C2 -waveform {0 12} [get_ports C2]

create_generated_clock -name GC1 -divide_by 1 \

-source [get_pins mux1/A] [get_pins mux1/Z] -combinational
create_generated_clock -name GC2 -divide_by 1 \
-source [get_pins mux1/B] [get_pins mux1/Z] -combinational -add

set_clock_groups -physically_exclusive -group GC1 -group GC2

So the difference between logical exclusive and physical exclusive is:

If two clocks exist at the same time, and there is a selector controlling the two signals, then
they are logical exclusive
If two clocks cannot appear in the circuit at the same time (for example, defined at the same
point), then they are physically exclusive

Question：
In the second figure, if you declare C1 C2 as physical exclusive, what will happen?
Although both logical exclusive and physical exclusive can ensure that there is no timing check
between C1 and C2,
But in the case of logical exclusive, the tool will calculate the crosstalk between C1 and C2, and
in the case of physical exclusive, it will not calculate the crosstalk
In the second figure, C1 and C2 have their own separate traces. There may be crosstalk
between them, so they cannot be declared as physical exclusive.

Finally, attach an explanation of the difference between logical exclusive and physical exclusive
in a textbook:
PVT

RC corners
In below 90nm or in deep submircron nodes:
The contribution of interconnect delay in a timing path become significant and Coupling
Cap component (Cc) in net delay can significantly alter slack values at an endpoint of a timing
path.

So, RC corners have to be split up as per the contribution of each component Ground
Capacitance (Cg) and Coupling capacitance (Cc).

So on top of the 2 conventional RC corners Cmax and Cmin, foundry came up with 2 more RC
corners.

RC worst (also known as Delay corner) - Cc is min, Cg * R is max

RC best (also known as XTALK corner) - Cc is max. Cg * R is min

5 types of RC corners:
Cbest
Cworst
RCworst
RCbest
Typical

Cworst (Cmax corners):

Refers to corners which results max cap.
Corner has largest path delay for paths with short interconnect nets and can be used for max-
path analysis.

RCworst (RC max corners):

Refers to corners which maximizes interconnect RC product.
Corner has largest path delay for paths with long interconnects and can be used for max-path
analysis.

Cbest (Cmin corner):

Refers to corners with min cap

Interconnect Resistance is larget than the Typical corner.
Results in smallest delay for paths with short nets and can be used for min-path analysis.

RCbest (min interconnect RC product):

Refers to corners with min interconnect RC product.
Corresponds to min Resistance and larger than typical capacitance.
Results in smallest delay for paths with long interconnects and can be used for min-path
analysis.
So there are 2 types of parasitics
1) C based
2) RC based

C-based means worst and best caps

RC-based means worst and best R in adjustment with C (RC product)

Based on experience, it was found that C-based extraction provides worst and best case over
RC for internal timing paths because Capacitance dominates short wire. However, for large
design, inter-block timing paths were often worst with RC worst parasitic since R dominates
for long wires.
 Clock Tree Exceptions
• Non- Stop Pin
• Exclude Pin
• Float Pin
• Stop Pin
• Don’t Touch Subtree
• Don’t Buffer Nets
• Don’t Size Cells
Non- Stop Pin:
• Nonstop pins trace through the endpoints that are normally considered as endpoints of the
clock tree.
• Example :
• The clock pin of sequential cells driving generated clock are implicit non-stop pins.
• Clock pin of ICG cells.

Fig2: Non Stop pin

Exclude pin:
• Exclude pin are clock tree endpoints that are excluded from clock tree timing calculation and
optimization.
• The tool considers exclude pins only in calculation and optimizations for design rule constraints.
• During CTS, the tool isolates exclude pins from the clock tree by inserting a guide buffer before
the pin.
• Examples:
• Implicit exclude pin-
• Non clock input pin of sequential cell.
• Multiplexer select pin.
• Three-state enable pin.
• Output port.
• Incorrectly defined clock pin [if pin don’t have trigger edge info.].
• Cascaded clock.

Fig3: Exclude pin

• In the above figure, beyond the exclude pin the tool never perform skew or insertion delay
optimization but does perform design rule fixing.
Float Pin:
• Float pins are clock pins that have special insertion delay requirements and balancing is done
according to the delay.[Macro modelling].

Fig4: Float pin

Stop Pin:
• Stop pins are the endpoints of clock tree that are used for delay balancing.
• CTS, the tool uses stop pins in calculation & optimization for both DRC and clock tree timing.
• Example:
• Clock sink are implicit stop pins.

Fig5: Stop pin

 The optimization is done only upto the stop pin as shown in the above figure.
Don’t Touch Sub-tree:
• If we want to preserve a portion of an existing clock tree, we put don’t touch exception on the
sub-tree.

Fig6: Don’t touch subtree

• CLK1 is the pre-existing clock and path 1 is optimized with respect to CLK1.
• CLK2 is the new generated clock. Don’t touch sub-tree attribute is set w.r.t C1.
• Example:
• If path1 is 300ps and path2 is 200ps, during balancing delay are added in path2.
• If path1 is 200ps and path2 is 300ps, during balancing delay can’t be added on path1 because
on path1 don’t touch attribute is set and we get violation.
Don’t Buffer Net:
• It is used in order to improve the results, by preventing the tool from buffering certain nets.
Note: Don’t buffer nets have high priority than DRC.CTS do not add buffers on such nets.
• Example:
• If the path is a false path, then no need of balancing the path. So set don’t buffer net attribute.
Don’t Size Cell:
• To prevent sizing of cells on the clock path during CTS and optimization, we must identify the
cell as don’t size cells.
Specifying Size-Only Cells:
• During CTS & optimization, size only cells can only be sized not moved or split.
• After sizing, if the cells overlap with an adjacent cell after sizing, the size-only cell might be
moved during the legalization step.

Ignore pins:
• These are also clock endpoints that are excluded from clock tree timing calculations and
optimizations. The tool uses ignore pins only in calculation and optimizations for design
rule constraints. During CTS the tool isolate ignore pins from the clock tree by inserting a
guide buffer before the pin.
• Beyond the ignore pins the tool never performs skew or insertion delay optimization but
it does perform design rule fixing.
 • Ignore pins are:
• Source pins of clock trees in the fanout of another clock
• Non clock inputs pins of sequential cells
• Output ports

******************************************************************************

A netlist consisting of 500k gates and I have to estimate die area and floorplanning. How do I
go about it?
There are 2 methods to estimate die area:

Method 1:
Each cell has got its area according to a specific library. Go through all your cells and multiply
each cell in its corresponding area from your vendor’s library. Then you can take some density
factor – usually for a standard design you should have around 80% density after placement. So
from this data you can estimate your required die area.

Method 2:
One more way of doing it is, Load the design in the implementation tool, try to change the
floorplan ( x & y coordinates ) in a such a way that the Starting utilization will be around 50% -
to- 60%. Again, it depends on the netlist quality & netlist completion status (like Netlist is 75%,
80% & 90% completed).

How to do floor planning for multi Vdd designs?

First we have to decide about the power domains, and add the power rings for each domain,
and add the stripes to supply the power for standard cells.

What is core utilization percentage?

Core utilization percentage indicates the amount of core area used for cell placement. The
number is calculated as a ratio of the total cell area (for hard macros and standard cells or soft
macro cells) to the core area. A core utilization of 0.8, for example, means that 80% of the core
area is used for cell placement and 20 percent is available for routing.

When core utilization area increased to 90%, macros got placed outside core area so does it
mean that increase in core utilization area decreases width and height?
If you go on with 90% then there may be a problem of congestion and routing problem. It
means that you can’t do routing within this area. Sometimes you can fit within 90% utilization
but while go on for timing optimization like upsize and adding buffers will lead to increase in
size. So in this case you can’t do anything so we need to come back to floorplan again. So to be
on safer side we are fixing to 70 to 80% utilization.
Why do we remove all placed standard cells, and then write out floorplan in DEF format.
What’s use of DEF file?
DEF deals only with floorplan size. So to get the abstract of the floorplan, we are doing like this.
Saving and loading this file we can get this abstract again. We don’t need to redo floorplan.

Can area recovery be done by downsizing cells at path with positive slack?
Yes, Area recovery can be done by downsizing cells at path with positive slack. Also deleting
unwanted buffers will also help in area recovery

We can manipulate IR drop by changing number of power straps. I increased power straps
which reduced IR drop, but how many power straps can I keep adding to reduce IR drop? How
to calculate number of straps required. What problems can arise with increase in number of
straps?
We can use tools to calculate IR drop (ex:- Voltagestrom, Redhawk) if drop is high. Based on
that we can add straps. But if you do projects repeatedly you will come to know that this much
straps is enough. In this case you will not need tools. It’s having calculation but it’s not accurate
it’s an approximate one. Number of straps will create problem in routing also it affects area. So
results will be in routing congestion. To number of power straps required for a design click
here.

aprPGConnect, is used for logical connection of all VDD, VSS nets of all modules. so how do we
connect all VDD, VSS to global VDD /VSS nets before placement?
The aprPGConnect, is used for logical connection of all VDD, VSS nets of all modules. For
physical connection you can use the axgCreateStandardcellRails command to create the
standard cell rails and through them connect to the rings or the straps depending upon power
delivery design.

A design has memory and analog IP. How to arrange power and ground lines in floor-plan. Is
it separate digital and analog power lines? It is important to design power-ground plan on
ASIC?
Basically you have to make sure to keep analog and digital rails isolated from one another. All
hard macro and memory blocks need to have a vdd/vss pair ring around them. Memories are
always on the side or corners of your chip. Put a pair of vdd/vss ring around your design. This is
usually called core power ring.

Create a pair of vertical vdd/vss every 100 micron. This is called the power straps and on either
side taps into the core power ring. put a pair of vdd/vss around every analog block and strap
these analog rings (using a pair of vdd/vss) and run them to your package vdd/vss rings.

Keep in mind that in every place a digital vdd/vss crosses analog vdd/vss straps, then you need
to cut the digital vdd/vss on either side of the analog crossing to isolate the analog from digital
noise. you need to dedicate pins on your chip for analog power and ground. Now we come to
 the most time consuming part of this, HOW THICK SHOULD YOU MAKE all these rings/straps.
The answer is this is technology dependent. Look into the packaging documentations, they
usually have guidelines for how to calculate the thickness of you power rings. Some even have
applications that calculate all this for you and makes the cuts for analog/digital crossings.

In my design, core PG ring and strips were implemented by M6/M7,and strips in vertical
orientation is M6.I use default method to connect M6 strips to stand cell connection,M1,the
vias from V12,V23,.. to V56 will block the routing of M2,..M6, it will increase congestion to
some extent. I want to know is there any good method to avoid congestion when add strips or
connect strips to standard cell connection?
In Synopsys ICC, there was a command controlling the standard cell utilization under power
straps. Using this you can have some sort of channels passing through stacked vias, between
standard cells. This limits the detours done because of these stacked vias and allows more
uniform cell placement resulting and a reduced congestion. in Soc Encounter, The command
setPrerouteAsObs can be used to control standard cell density under power strips. But the
100% via connection from M1 to M6 under wide strip metal still block other nets’ routing.

How to control via generation when do special route for standard cell, such as how to reserve
gaps between vias for other net routing?
To remove those stack vias you need to:

▪ Either returns back to floorplan step, where power straps and power/ground preroute vias are
dropped. Normally vias are dropped regularly to reduce power & ground resistance; therefore
maximum numbers of vias are dropped over power/ground nets. Therefore you need to check
your floorplan scripts. They should be after horizontal & vertical power strap generation at M6
& M7.
▪ If the vias to be removed are at specific regions you can delete them at any step, but before
global routing of course to allow global route be aware of resources/obstructions. In this case
as you’ll increase the power/ground resistance you should confirm this methods validity by IR
Drop analysis.
▪ If IR Drop is an issue, another option would be placing standard cell placement percentage
blockages (Magma has percentage blockages which is good at reducing blockages). This is the
safest method as you don’t need to delete those stacked M1-to-M5 vias anymore. However as
you’ll need to reduce placement density this will cost you some unused area.

How to do a good floor plan and power stripes with blocks?

A good floorplan is made when:

▪ Minimum space lost between macros/rows,

▪ Macros placed in order to be close to their related logic,
▪ IR/Electro Migration is good
▪ Routing congestion as minimal.

How to reduce congestion?

By adding placement blockage & routing blockage during the floorplan, Congestion can be
reduced. Placement blockage is to avoid the unnecessary cell placement in between macros &
other critical areas. Routing blockage is used to tell the global router not to route anything on
the particular area. Sometimes people used to change/modify the blockages according to their
needs at each stage of the design.

Normally routing blockages should be placed before global routing to force global router to
respect these blockages. Most Place and Route tools runs the first global routing at placement
step and then updates it incrementally, therefore add blockages before placement. Otherwise if
you want to use it after any global/detail routing is done, you may need to update global
routing first (may be incrementally).

How to find the reason for congestion in particular region? How to reduce congestion?
First analyze placed congested database, and find out the hot spot which is highly congested.

▪ Case -1: “Congestion in Channel between macro”

▪ Reason:- Not enough tracks is available in channels to route macro pins, or channel is highly
congested because of std cell placement.
▪ Solution:- Need to increase channel width between Macros or please make sure that soft
blockage or hard blockage is properly placed.
▪ Case -2: “Congestion in Macro Corners”
▪ Reason: Corners of macro is very prone to congestion because its having connectivity from both
direction
▪ Solution: 1. Place some HALO around each macro (5-7um). 2. Place a hard blockage on macro
corners (corner protection (Hard Placement Blockage) done after standard cell rail creation
otherwise it won’t allow standard cell inside it.
▪ Case -3: “Congestion in center of chip/congestion in module anywhere in chip”
▪ Reason: Congestion in standard cell or module is based on the module local density (local
density is very high 95%-100%).Also depend on module nature (highly connected). Die area
less.
▪ Solution: 1. Module density should be even in whole chip (order os 65-85%). 2. Use density
screen/Partial blockage to control module density in specific areas. 3. Use cell padding 4. If
congestion is too big in that case chip area should be increased based on the congestion map.

What are the reasons for the Routing congestion in a design?

Routing congestion can be due to:

1. High standard cell density in small area.

2. Placement of standard cells near macros.
3. High pin density on one edge of block.
4. Placing macros in the middle of floorplan.
5. Bad Floorplan
6. Placement of complex cells in a design
7. During IO optimization tool does buffering, so lot of cells sits at core area.

What actually happens in power planning? What is the main aim of power planning?
The main aim of power planning is to ensure all the cells in the design are able to get sufficient
power for proper functioning of the design. During the power planning the power rings and
power straps are created to distribute power equally across the design.

Power straps are provided for the regulated power supply throughout the block or chip.
Number of straps depends on the voltage and the current of your design. You must design the
power grid that will provide equal power from all sides of the block. You can also use the early
rail analysis method determine the IR drop in your block and lay the sufficient power stripes.

How power stripes are useful in power planning?

If the chip size is large, therefore core power rings do not able to supply power to standard cells
because of long distance particularly the cells in the center of the chips (or will give high IR drop
to the farthest cells), then you need power stripes. The number of stripes depend of the area of
you chip.

What is the minimum space between two macros? How we can find minimum space of
macros?
The distance between macro = (no. of pins of macros*pitch*2)/no. of available routing layers

For example, the design has 2 macros having the pins of 50 each macro and pitch = 0.50 and
available metals are 8. Then space between macros = ((50+50)*0.5*2)/8 = 12.5

What are the steps needed to be taken care while doing Floorplaning?
▪ Die Size Estimation
▪ Pin/pad location
▪ Hard macro placement
▪ Placement and routing blockage
▪ Location and area of the soft macros and its pin locations
▪ Number of power pads and its location.
Note: For block level Die size and Pin placement comes from TOP

▪ Fly-line analysis is required before placing the macros

▪ While fixing the location of the pin or pad always consider the surrounding environment with
which the block or chip is interacting. This avoids routing congestion and also benefits in
effective circuit timing
▪ Provide sufficient number of power/ground pads on each side of the chip for
effective power distribution.
▪ In deciding the number of power/ground pads, Power report and IR-drop in the design should
also be considered.
▪ Orientation of these macros forms an important part of floorplaning.
▪ Create standard cell placement blockage (Hard Blockage) at the corner of the macro because
this part is more sensitive to routing congestion.
▪ Using the proper aspect ratio (Width /Height) of the chip
For placing block-level pins:
▪ First determine the correct layer for the pins
▪ Spread out the pins to reduce congestion.
▪ Avoid placing pins in corners where routing access is limited
▪ Use multiple pin layers for less congestion
▪ Never place cells within the perimeter of hard macros.
▪ To keep from blocking access to signal pins, avoid placing cells
under power straps unless the straps are on metal layers higher than metal2.
▪ Use density constraints or placement-blockage arrays to reduce congestion.
▪ Avoid creating any blockage that increases congestion.

What are the floorplaning control parameters?

Aspect ratio, Core utilization, Row/Core Ratio, Width and Height are the floorplaning control
parameters.

How can you say a floorplan is good?

A good floorplaning should meet the following constraints:

▪ Minimize the total chip area

▪ Make Routing phase easy (Routable)
▪ Improve the performance by reducing signal delays

What are the inputs for floorplan?

The following are the inputs for Floorplan:

▪ Synthesized Netlist (.v, .vhdl)

▪ Design Constraints (SDC – Synopsys Design Constraints)
▪ Physical Partitioning Information of the design
▪ IO Placement file (optional)
▪ Macro Placement File (optional)
▪ Floorplaning Control parameters

What are the outputs of floorplan?

The following are the outputs for floorplan:

▪ Die/Block Area
▪ I/Os Placed
▪ Macros placed
▪ Power Grid Design
▪ Power Pre-routing
▪ Standard cell placement areas
****************************************************************
Aspect Ratio(Ar) = Horizontal routing resource (H)/Vertical routing resource (V)

Core Utilization (Cu): It indicates the amount of core area used for cell placement. The number
is calculated as a ratio of the total cell area (for hard macros and standard cells or soft macro
cells) to the core area. A core utilization of 0.8, for example, means that 80% of the core area is
used for cell placement and 20 percent is available for routing.
Core Utilization(Cu) = Standard Cell area/(Row area + Channel area)

Row to Core Ratio (Rcr): It indicates the amount of channel space to provide for routing
between the cell rows. The smaller the number, the more space is left for routing. A value of
1.0 leaves no routing channel space.
Rcr = Row area / Core area (H x V)
 Total utilization T(F) of floorplan F is derived using the following equation:
T(F) = (A(m) + A(p) + A(s) ) / A

▪ where A(m) = Area occupied by macros

▪ A(p) = Area occupied by Pads/ Pad fillers
▪ A(s) = Area occupied by Standard Cells
Cell row utilization C(F) of floorplan F is approximated using the following equation:
C(F) = A(s) / A(R -union(B, E, m, p))

▪ Where R= All cell rows

▪ B= All placement blockages
▪ E= Exclusive Regions
******************************************************************

Layout versus schematic(LVS) is a process of checking that the geometry/layout

matches the schematic/netlist.

Design rule checks(DRC) is the process of checking that the geometry in the GDS file
follows the rules given by the foundry.

Logical equivalence checks(LVC) is the process of equivalence check between pre and
post design layout.

Sanity Checks before Floorplan in Physical Design

Sanity checks are an important step for physical design engineers to make sure that the inputs
received for physical design are correct and consistent. Any issues in the input files may cause
problems in the later stages. So it is important to perform the sanity checks in the initial stage
that is when the design is loaded in PnR tool and before the start of the floorplan.

Here is a list of checks which must be performed before the floorplan of design.
 Figure-1: Sanity checks before floorplan

Library Check:

In library check, basically, we validate the libraries before starting the physical design by
checking the consistency between the physical and logical library. It also checks the quality of
both libraries and reports the error if any. The cells used in the design must be present in the
logical as well as in the physical library.

Innovus commands:

checkDesign -physicalLibrary : This command will check the physical library and report that all
the cells used in design have their LEF view or not.

checkDesign -timigLibrary : This command will check the timing library and report that all the
cells used in design have defined in timing library or not.

checkDesign -all : This command will check the missing or inconsistent library and design data.

ICC command:
check_library : Performs consistency checks between the logical and physical library, across the
logical library and within the physical library.

Netlist Check:

Netlist must be checked for consistency. This check analyzes the currently loaded netlist and
reports the inconsistency if any. Netlist check mainly checks:

1. Floating input pins and nets

2. No direct connection between VDD and VSS
3. Multidriven nets
4. combinational loops
5. Unloaded outputs
6. Uncontraints pins
7. Mismatch pin count between instance and reference

Innovus command:

checkDesign -netlist

ICC command:

check_design

SDC Check:
SDC file must be checked before start the design. Some of the common issues in SDC file are as
follow.

1. Unconstrained path
2. Clock is reaching to all synchronous elements
3. Multiclock driven registers
4. Unconstrained endpoint
5. Input/output delay missing for a port
6. Slew or load constraint missing for a port
7. Missing clock definition

Innovus command:

check_timing

ICC command:
check_timing

******************************************************************************

Physical design sanity checks

Sanity Checks in Physical Design Flow

1. check_library
2. check_timing
3. report_constraint
4. report_timing
5. report_qor
6. check_design
7. check_legality

check_library:
check_library validates the libraries i.e., it performs consistency checks between logical and
physical libraries, across logical libraries, and within physical libraries. This command checks
library qualities in three main areas: Physical library quality Logic versus physical library
consistency Logic versus logic library consistency

check_timing
PNR tool wont optimize the paths which are not constrained. So we have to check any
unconstrained paths are exist in the design. check_timing command reports unconstrained
paths. If there are any unconstrained paths in the design, run the report_timing_requirements
command to verify that the unconstrained paths are false paths.

No clock_relative delay specified for input ports ____________

Unconstrained_endpoints. _________________

End-points are not constrained for maximum delay ___________________

report_constraints
It reports to check the following parameters. Worst Negative Slack (WNS) Total Negative Slack
(TNS) Design Rule Constraint Violations

report_timing
report_timing displays timing information about a design. The report_timing command
provides a report of timing information for the current design. By default, the report_timing
command reports the single worst setup path in each clock group.
report_qor
report_qor displays QoR information and statistics for the current design. This command
reports timing-path group and cell count details, along with current design statistics such as
combinational, noncombinational, and total area. The command also reports static power,
design rule violations, and compile-time details.

check_design
check_design checks the current design for consistency. The check_design command checks
the internal representation of the current design for consistency, and issues error and warning
messages as appropriate.

a. inputs/Outputs 300

b. Undriven outputs (LINT-5) 505

c. Unloaded inputs (LINT-8) 162

d. Feedthrough (LINT-29) 174

e. Shorted outputs (LINT-31) 52

f. Constant outputs (LINT-52) 24

g. Cells 152

h. Cells do not drive (LINT-1) 1

i. Connected to power or ground (LINT-32) 118

j. Nets connected to multiple pins on same cell (LINT-33) 33

k. Nets 1226

l. Unloaded nets (LINT-2) 721

Error messages indicate design problems of such severity that the compile command does not
accept the design Warning messages are informational and do not necessarily indicate design
problems. However, these messages should be investigated.
Warnings
Potential problems detected by this command include Unloaded input ports or undriven output
ports Nets without loads or drivers or with multiple drivers
Cells or designs without inputs or outputs

Mismatched pin counts between an instance and its reference

Tristate buses with non-tristate drivers wire loops across hierarchies

check_legality
reports overlap and cells placement related violation like orientation, overlaps etc.

Temperature Inversion in VLSI

If a simple question comes before you that "What will impact on the delay of a standard
cell if temperature varies? " Are you going to answer straightforward the delay of the cell will
increase with temperature OR The delay of the cell will decrease with temperature? If you are
going with either of the above answers, Then you need to spare some moment in this article
and understand the concept of Temperature Inversion.

Figure-1: Trend of cell delay with temperature

What is temperature inversion?

In general, as temperature increases, the delay of standard cells increases because of mobility
degradation at higher temperatures. But in lower technology nodes the impact of temperature
on the delay of the cell is inverse. In lower nodes, the delay of the cell decreases with an
increase in temperature. So in the lower technology node, the effect of temperature on the
delay of the cell is inverted and this effect is called the temperature inversion. The main reason
behind this inversion is in the lower technology node, the effect of the threshold voltage is
dominating over the mobility.

So an appropriate answer to the above question could be we should answer this question with
respect to the technology node. One can say that at the lower technology nodes as
temperature increases the delay of cell decreases. Here lower technology node means the
technology node below 65nm. Why part of this question is important, but we should wait if it is
asked further. In the next part, we will learn why temperature inversion occurs.

Figure-2: Temperature inversion

The following section will explain in detail of factors affecting the delay of cells and their
variation.

Reason for temperature inversion

The delay of a cell is simply the time required to charge/discharge the load capacitance. The
charging and discharging time of the load capacitor depends on the drain current. If the drain
current is high, it will take a lesser time to charge/discharge the load capacitor and so delay will
be lesser and vice-versa. Now let's see the dependency of drain current Id.

The saturation current of MOSFET is,

The drain current Id is directly proportional to the mobility of charge carriers. So as the
temperature increases, the lattice scattering increases, and ultimately the mobility of the
charge carrier decreases which leads to the decrease in drain current Id and so it increases in
the delay of the cell.
Now let's come to the second important factor, the term (Vgs - Vt) in the above equation is
called overdrive voltage. There is a variation in threshold voltage with temperature as per the
following equation,

As temperature increases, the threshold voltage decrease, and overdrive voltage increases. This
overdrive voltage is more dominating in the lower technology node because in the lower
technology node the Vgs and Vt are more closers and so a slight change in Vt will have more
impact on overdrive voltage. But in a higher technology node since Vgs is much larger than Vt
so a slight change in Vt not causes much change in overdrive voltage. Again the Id is
proportional to the squire of overdrive voltage. So changes in overdrive voltage are further
amplified and it is dominating over the mobility in lower technology node.

In a nutshell, In a lower technology node, as temperature increases the threshold voltage

decreases so overdrive voltage and drain current increase which leads decrease in cell delay.
Here overdrive voltage is dominating over the mobility factor. But in higher technology nodes,
overdrive voltage is not much dominating, and delay of the cell varies as per variation in
carrier mobility and we have discussed as temperature increases mobility decreases and so
drain current decreases which lead increase in cell delay.

So There are two major factors that drive the variation in cell delay, mobility and overdrive
voltage. In lower technology nodes overdrive voltage is more dominating which causes the
temperature inversion effect.