Institut für Integrierte Systeme

Integrated Systems Laboratory

Department of Information Technology and Electrical Engineering

VLSI II:
Design of Very Large Scale Integration Circuits
227-0147-00L

Exercise 11

Chip Finishing
Prof. L. Benini
F. Gürkaynak

Last Changed: 2018-05-14 10:35:42 +0200

1 Introduction
In this training we will start with a design that has been completely placed and routed, and look into the finishing
steps that are required in order to ensure that the design can be fabricated.

Student Task 0: Parts of the text that have a gray background, like the current paragraph, indicate steps
required to complete the exercise.

2 Chip Finishing
First, get the files for this exercise.

Student Task 1:
• Open a Linux shell and type
sh > /home/vlsi2/ex11/install.sh .

• Step into the exercise folder that has been installed, and start the cockpit using
sh > icdesign umcL65 -update all &

• Before starting run the initialization script from the ’ex11’ directory
sh > ./init.sh

• Start C ADENCE EDI E NCOUNTER. Restore the design we prepared for this exercise as follows:
Select File→Restore Design... from the menu. Select the
’filter chip routed final.enc’ inside the ’save’ directory. It contains the whole design in
C ADENCE EDI E NCOUNTER’s own format.
• If you want, you can enable multi-cpu acceleration using
sh > setMultiCpuUsage -localCpu max

2.1 Insert Filler Cells

The design you loaded is completely placed and routed, the clock trees have been inserted and the power
design has been done as well. In fact, the design is just a few steps from being taped out.

Student Task 2:
• Switch to the physical view, zoom into the design and examine the standard cell placement (you may
want to hide the metal layers).
• Note that there is some empty space around and between the standard cells that have already
been placed. We do not need this space anymore, and in order to ensure that the design can be
manufactured, we are going to fill this space with so called filler-cells.
sh > source scripts/fillcore-insert.tcl

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 active area
polysilicon
metal 1

large filler cell with P

type MOSCAPs

small empty small filler cell

filler cell with N/P type
MOSCAPs

Figure 1: Layout excerpt after adding the filler cells (with standard cell layout). This standard cell library
provides three different kinds of filler cells: empty fillers, fillers with N/P type MOSCAPs, and fillers
with P type MOSCAPs (which have less leakage).

Some of these filler cells also contain MOSFET based capacitors (MOSCAPs) that help stabilizing the power
and ground nets. A layout excerpt with such filler cells is shown in Figure 1, and their documentation can
be found in the standard cell application note on page 7 (this document is linked into the ’docs’ folder of the
cockpit). More general information about filler cells can be found in the lecture notes in section 9.4.4.
Note that after adding the filler cells your row utilization will be 100%. This means that you will have no room
for further optimizations. Make sure to insert filler cells after all optimizations have been completed. It is
also possible to remove the filler cells with Place →Filler →Delete... or by using the script fillcore-
remove.tcl.

2.2 Checking Connectivity and Geometry Violations

Now that we are completely finished with the layout, we should make sure that it indeed corresponds to the
netlist, and that the physical layout can be fabricated. Note that the these are just sanity checks that we perform
before exporting the layout data from C ADENCE EDI E NCOUNTER. More rigorous design rule checks (DRC)
and layout versus schematic (LVS) checks will be performed afterwards using specialized tools and the design
rules from the fab (this is the topic of the next exercise).

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 Student Task 3:
• Select Verify →Verify Connectivity ... from the menu. The window depicted in Figure
2a) will appear. Run the analysis and check the console for the report summary. There should be
no violations.
• Similarly, lets verify all geometrical shapes. Select Verify →Verify Geometry ... (Figure 2b)
from the menu. Run the analysis and check the report on the console. You should get no violations.
• We are also going to check that there are no process antennas. In principle, a process antenna
is a very long wire which is connected to a MOSFET gate at one end, and otherwise remains
unconnected for several processing steps. Charge may now accumulate on this wire and eventually
lead to an oxide breakdown at the gate it is connected to. Select Verify →Verify Process \
Antenna ... (Figure 2c) from the menu. Run the analysis and check the report on the console.
You should get no violations.
• In order to check the well taps that have been inserted earlier in the back-end, use the command
below (there is no GUI for this). Again, there should be no violations.
sh > verifyWellTap -cell WT3W -rule 30 -report reports/\
filter_chip_wellTap.rpt

a) b)

c)
Figure 2: Verification dialogues for connectivity a), geometry b) and process antennas c) in Cadence EDI
Encounter. Save the reports in the corresponding folder and give them meaningful names. This
makes it easier for you when you need to revisit them later on.

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 Figure 3: Summary report dialogue.

2.3 Design Summary Report

After these sanity checks, you should look at the summary reports of your design in order to make sure that
everything is in order.

Student Task 4: Select File →Report →Summary from the menu. The window depicted in Figure 3
will appear. Select Text Only, and save the report into the corresponding folder. Examine the report that
was generated.

The following parts of the summary report may be of particular interest to you (also to extract useful information
for your report when you are doing an ASIC project):
• Macro Cells in Netlist: Here, all the macros in the design should be listed. Double check that you
instantiated the correct macros.
• IO Cells in Netlist: Information about the instantiated IO cells.
• Clocks in Design: Here, all the clocks in your design should be listed.
• Floorplan/Placement Information: Detailed information about the area / density of the die, the standard
cells and the macros.

Student Task 5: Using the summary report, try to answer the following questions:
• How many macro cells are in the design and how many percent of the die area do they consume.

• How many clock buffer cells with driving strength M4 were instantiated?

• How many IO pad cells of type IUMB does this chip have?

• What is the core area and chip area? What is the core density without counting the physical cells?
Note: physical standard cells are non-functional cells like fillers and welltaps.

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 Student Task 6: Now we perform one last sanity check. Goto the C ADENCE EDI E NCOUNTER console
and enter
sh > report_net -min_fanout 1000

This command checks for nets that have a fanout of more than 1000 nets. You should not have such nets
in your design anymore, since all high-fanout nets (clock, reset, scan-enable) have been declared as non-
standard nets and have been implemented as balanced clock trees at an earlier stage during the back-end.
There is a script that will perform the last verification and reporting steps for you automatically. You can set a
variable DESIGNNAME to assign the base name for all the files generated by this script.
sh > set DESIGNNAME MyBeautifulChip
sh > source scripts/checkdesign.tcl

2.4 Evaluate the Physical Design

Take the time to examine the routing. This is the main feedback you need for a second back-end iteration. Try
to view all metal lines separately to see how congested your routing is. If you see a lot of Metal-8 (turquoise)
you are probably close to the density limit. In our design you should not notice any congestion and Metal-8 will
barely be used. If your design routed without problems and the routing was rather sparse then the next time
you could assign a smaller core area and increase the row utilization. On the other hand if the design barely
routed you have found the limits, in a second iteration you might consider assigning a little more core area
since timing degrades with congestion.
Check the connections of your macro-cells and pads, this may give you an idea how to place the macro-cells
the next time around. You need to get used to evaluating the result of different back-end design runs.

2.5 Generate Output Files

Congratulations, you have completed the last steps of the back-end design. That was not so hard now, was it?

Student Task 7:
• Save your design using File →Save Design ... →Innovus to the save directory and make
sure that you use a name that shows this is a finished design (i.e. chip_final.enc).
• Finally we need to export all data needed for post layout simulation and physical verification (DR-
C/LVS). There is a script that will write out all relevant files to the out/ directory.
sh > source scripts/exportall.tcl

Similar to the checkdesign.tcl file, the variable DESIGNNAME will be used to assign the base name of the
files. If you do not specify a name, final will be used. After you complete this step you will have the following
files:
* lvs.v This is the final netlist that contains everything (also physical and filler cells). Make sure to use this
netlist for LVS checks.
*.v This is the final netlist without physical and filler cells. This netlist is intended for post-layout simulations
only.
*.gds.gz The layout in GDSII (Graphic Design System II) format. This is the standard format for exchanging
layout data, i.e. this is the format we use to deliver our design to the fab (for the mask production).

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*.sdf.gz The SDF (Standard Delay Format) file to be used for post layout simulation.
The ’*.gz’ ending in the latter two indicate that the files have additionally been compressed using GNU Gzip.
Note that you have to use both the verilog netlist and the SDF file in post-layout simulations! The former
contains the connectivity information, and the latter the delays that were extracted from the layout.

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3 How to Deal With Violations?
The design we used up to now was very convenient since it passed all the checks at once and no additional
intervention from our side was necessary. However, in practice it is not uncommon that you get a few violations
due to routing congestion, tight timing constraints, floor planning problems and the like. In the following, we
switch to a different design with a couple of violations that we are going to fix.

Student Task 8:
• Select File→Restore Design... from the menu. Select the ’aes multi final.enc’ inside
the ’save’ directory.
• Examine the design you just loaded by running the final checksa and using the violation browser
(Tools→Violation Browser...). You should find a process antenna violation and six short
circuit violations.
a The filler cells have been alreday placed in the design.

By default, the routing tool NanoRoute already applies a couple of post-route optimizations and ’search-and-
repair’ operations. Depending on the type of the violations, re-running these last iterations of the router can
help fixing some of the issues.

Student Task 9:
• Select Route→NanoRoute→Route... from the menu, make sure that only ’Detail Route’ and
’Fix Antenna’ are selected and click ok. Check the design again for violations after this step.

Some of the violations should be fixed now, but there are still a couple of short circuits. We are now going
to rip up some of the involved nets and re-route them using the so called Engineering Change Order (ECO)
option of the router. The term ECO is explained in more detail in the next section of the exercise. Setting this
option instructs the router to complete partial routes while maintaining the existing wire segments as much as
possible.

Student Task 10:

• Use the violation browser to locate the persisting violations. Then select and delete the violating
wire elements.
• Select Route→NanoRoute→Route... from the menu, make sure that ’Global Route’, ’Detail
Route’, ’Fix Antenna’ and ’ECO Route’ are selected and click ok. Check the design again for
violations after this step.

All the violations should have disappeared. Note that in some cases, even a refinement of the floor plan, the
power design or of the timing constraints is necessary in order to get rid of all violations. For example, it can
happen that an incorrectly placed halo around a macro cell can lead to isolated standard cells, since they are
placed too close to the macro and therefore the router has problems connecting them. Another example is
the placement of the global power grid which can give rise to problems in areas where the connections to the
power ring overlap with the connections to the power pads.

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4 ECO
The term Engineering Change Order (ECO) is used to denote all kinds of (limited) design changes that have
to be incorporated at a very late stage during the back-end. There are different ECO scenarios ranging from
very simple changes (like performing partial re-routes as in the last task) to small changes in the netlist or
even partial changes in the RTL code of the design. For less complex designs (as our semester theses),
netlist changes are usually not incorporated using ECO since the back-end can be re-run in acceptable time.
However, this is different for very large designs where an ECO flow can save a significant amount of time and
money. There are even cases where small fixes have to be applied to a design that has already undergone the
first steps of fabrication. For such scenarios, engineers usually place a couple of spare gates on to the final
design which allows to perform an ECO by changing the routing on the metal layers alone. In the following we
step you through a very simple ECO flow. For this purpose, load again the filter chip design.

Student Task 11:

• Select File→Restore Design... from the menu. Select the
’filter chip routed final.enc’ from the ’save’ directory.

Now assume that we have to tape out this design as soon as possible, but we just realized that the polarity
of the handshake signal ’DataOutReq_SO’ was not specified correctly, i.e. it should be active low instead of
active high. This issue can be solved by adding an inverter just before the pad driver. In order to be able to
make this functional change, we need to extract a netlist from the currently loaded design. Note that this netlist
is not equivalent to the gate level netlist from Synopsys DC that was initially used to start the backend! The
reason for this is that C ADENCE EDI E NCOUNTER itself performed a couple of optimizations and changes to
the initial netlist during the backend flow.

Student Task 12:

• Select File→Save→Netlist..., make sure that only ’Include Intermediate Cell Definition’
is checked, and save the netlist under ’save/filter chip eco.v’.
• Open the netlist using your favorite text editor.

Lets modify the extracted netlist such that it meets our specifications. Note that all the changes that we are
doing at this point need to be described structurally in the HDL, since no synthesis is going to be performed
afterwards. This means that we have to manually insert an inverter cell from the standard cell library.

Student Task 13:

• Locate the pad instance ’pad_OutReq_SO’ and the wire ’OutReq__S’ in the netlist.
• Add an additional wire called ’OutReqECO__S’ right below ’OutReq__S’.
• Add the following inverter instance right after all the wire definitions:
INVM4W n_eco (.Z(OutReqECO__S), .A(OutReq__S));
• Connect ’OutReqECO__S’ to the ’.DO()’ pin of the output pad instance.

After these HDL changes, we have to read in this slightly modified netlist and instruct C ADENCE EDI E N -
COUNTER to perform the correct operations to apply this fix.

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 Student Task 14:
• Load the modified netlist into C ADENCE EDI E NCOUNTER and compare with the existing design:
sh > ecoDesign -noEcoPlace -noEcoRoute save/filter_chip_routed_final.\
enc.dat filter_chip save/filter_chip_eco.v

• Run the commands checkPlace and checkRoute and examine the reports.

You should observe that there is one unplaced instance and one unconnected net and an unconnected terminal
- this is the inverter cell we just added. We now have to place and route these new objects using ECO
aware placement and routing strategies. These strategies work in an incremental manner and try to minimize
additional changes to the existing design.

Student Task 15:

• Use the command ecoPlace to place the inverter and check again the placement using
checkPlace.
• Perform an ECO route as you did in the previous exercise section. Check the routing with
checkRoute.
• Perform a post-route timing analysis (both setup and hold) in order to check whether an incremental
timing optimization is required or not.
• Place again the filler cells.
sh > source scripts/fillcore-insert.tcl

• Perform a final design check to verify that everything is in order.

Congratulations! The design now fullfills the spec and can be taped-out just in time thanks to your quick
intervention :).
There also exist more complicated ECO flows that are able to propagate changes in the RTL description. How-
ever, these flows are also considerably more complex than the one presented here since rigorous equivalence
checking has to be performed among the netlists.

E Discuss any open questions with an assistant.

E

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