SPI Layout Guide An 01 e

Spansion® Serial Peripheral Interface
(SPI) FL Flash Layout Guide

Application Note
1. Introduction
The Spansion serial peripheral interface (SPI) flash devices are high speed synchronous access non-volatile
memory devices. Standard high speed layout practices should be followed when performing printed circuit
board (PCB) design with SPI flash. This application note outlines PCB layout recommendations for Spansion
SPI flash devices, including S25FL-P, S70FL-P, S25FL-S and S70FL-S flash families.
2. Basic SPI Flash Connectivity

All S25FL devices feature one flash die per package and are enabled via a single chip select control input. All
S70FL devices feature two identical die per package which are individually enabled via two chip select control
inputs and all other control inputs and I/O are shared between die. Figures 2.1 and Figure 2.2 illustrate basic
Host to SPI Flash configuration options for S25FL flash and S70FL flash, respectively.
Figure 2.1 Simplified Connection Diagrams for S25FL Single and Multi I/O Configurations
Standard Single I/O Configuration
Host SCK SCK S25FL

SI
SPI Flash
SO
SI SO
W# W#
HOLD# HOLD#
CS# CS#
Multi I/O Configuration
SCK SCK S25FL

Host
SPI Flash
SO/IO0 SI/IO0
SI/IO1 SO/IO1
W#/ACC/IO2 W#/ACC/IO2
HOLD#/IO3 HOLD#/IO3
CS# CS#
Publication Number SPI_Layout_Guide_AN Revision 01 Issue Date July 2, 2010

A pplication Note
Figure 2.2 Simplified Connection Diagrams for S70FL Single and Multi I/O Configurations
Standard Single I/O Configuration
Host SCK SCK S70FL

SI
SPI Flash
SO
SI SO
W# W#
HOLD# HOLD#
CS1# CS1#
CS2# CS2#
Multi I/O Configuration
SCK SCK S70FL

Host
SPI Flash
SO/IO0 SI/IO0
SI/IO1 SO/IO1
W#/ACC/IO2 W#/ACC/IO2
HOLD#/IO3 HOLD#/IO3
CS1# CS1#
CS2# CS2#
Often multiple SPI devices are connected to a single host. Figure 2.3 illustrates such a configuration. Use of a
dual die S70FL device can be viewed as use of Device 1 and Device 2 in Figure 2.3.
Figure 2.3 Simplified Multi- SPI Device Connection Diagram
SO
SI
SCK
SPI SCK SO S1 SCK SO S1 SCK SO S1

Bus Device 1 Device 2 Device 3
Master
CS# W# HOLD# CS# W# HOLD# CS# W# HOLD#
CS1#
CS2#
CS3#
Many SPI flash applications do not utilize the ACC, WP# or HOLD# functions. In those applications where an
input is not utilized, the unused I/O should be pulled up to VCC, or VIO if present, via a suitable resistor, e.g.
4.7 to 10 kohms.
2 Spansion® Serial Peripheral Interface (SPI) FL Flash Layout Guide July 2, 2010
Ap pl ic atio n No t e
3. SPI Flash Packaging

The FL-P and FL-S SPI Flash families provide a user configurable high speed single, dual or quad channel
interface to the host controller. Spansion SPI flash are available in a variety of packages, including SOIC-8
and SOIC-16 leaded packages, USON-8 and WSON-8 leadless packages and FAB024 and FAC024 ball grid
array (BGA) packages. Table 3.1 provides a matrix of package options for all FL-P and FL-S devices.
Table 3.1 Device Availability Matrix

Package \
32 Mbit 64 Mbit 128 Mbit 256 Mbit 512 Mbit 1024 Mbit
Density
SOC008 S25FL032P
S25FL128P
SO3 016 S25FL032P S25FL064P S25FL129P S25FL256S S25FL512S
S25FL128S
SL3 016 S70FL256P
USON S25FL032P
S25FL128P
WSON S25FL032P S25FL064P S25FL129P S25FL256S
S25FL128S
S25FL129P
FAB024 S25FL032P S25FL064P S25FL256S
S25FL128S
S25FL129P
FAC024 S25FL032P S25FL064P S25FL256S
S25FL128S
ZSA024 S70FL256P
other BGA S25FL512S
S70FL01GS
(planned) S70FL512S
3.1 SPI Flash Package Connection Diagrams

Applicable package connection diagrams are provided in each SPI Flash data sheet. These diagrams are
included here in Figure 3.1 through Figure 3.11 for reference.
Figure 3.1 SOC 008 wide – S25FL032P
CS# 1 8 VCC
SO / IO1 2 7 HOLD# / IO3
W#/ACC/IO2 3 6 SCK
GND 4 5 GND
July 2, 2010 Spansion® Serial Peripheral Interface (SPI) FL Flash Layout Guide 3
A pplication Note
Figure 3.2 SO3 016 – S25FL128P
HOLD# 1 16 SCK
VCC 2 15 SI
NC 3 14 PO6
PO2 4 13 PO5
PO1 5 12 PO4
PO0 6 11 PO3
CS# 7 10 GND
SO/PO7 8 9 WP#/ACC
Figure 3.3 016 – S25FL032P/064P/129P
HOLD#/IO3 1 16 SCK
VCC 2 15 SI/IO0
DNC 3 14 DNC
DNC 4 13 DNC
DNC 5 12 DNC
DNC 6 11 DNC
CS# 7 10 GND
SO/IO1 8 9 W#/ACC/IO2
Figure 3.4 SO3 016 – S29FL128S/256S/512S
HOLD#/IO3 1 16 SCK
VCC 2 15 SI/IO0
RESET#/RFU 3 14 VIO/RFU
RFU 4 13 DNC
RFU 5 12 DNC
RFU 6 11 DNC
CS# 7 10 GND
Figure 3.5 SL3 016 – S70FL256P
HOLD#/IO3 1 16 SCK
VCC 2 15 SI/IO0
DNU 3 14 DNU
DNU 4 13 DNC
DNU 5 12 DNC
CS2# 6 11 DNC
CS1# 7 10 GND
A pplication Note
Figure 3.6 USON – S25FL032P
CS# 1 8 VCC
SO/IO1 2 7 HOLD#/IO3
W#/ACC/IO2 3 6 SCK
GND 4 5 SI/IO0
Figure 3.7 WSON – S25FL128P
CS# 1 8 VCC
SO 2 7 HOLD#
WP#/ACC 3 6 SCK
GND 4 5 SI
Figure 3.8 WSON – S25FL032/064/129P, S25FL128/256S
CS# 1 8 VCC
SO/IO1 2 7 HOLD#/IO3
W#/ACC/IO2 3 6 SCK
GND 4 5 SI/IO0
Figure 3.9 FAB024 – S25FL032/064/129P, S25FL128/256S

1 2 3 4 5
A
NC NC RESET#/RFU NC
B
NC SCK GND VCC NC
C
NC CS# NC W#/ACC/IO2 NC
D
NC SO/IO1 SI/IO1 HOLD#/IO3 NC
E
NC NC NC VIO/RFU NC
Note:
RESET# and VIO inputs apply to S25FL-S models only.
Figure 3.10 FAC024 – S25FL032/064/129P, S25FL128/256S

1 2 3 4
A
NC NC NC RESET#/RFU
B
NC SCK GND VCC
C
NC CS# NC W#/ACC/IO2
D
NC SO/IO1 SI/IO0 HOLD#/IO3
E
NC NC NC
F
NC NC NC VIO/RFU
Note:
RESET# and VIO inputs apply to S25FL-S models only.
Figure 3.11 ZSA024 – S70FL256P

1 2 3 4 5
A
NC NC NC NC
B
NC SCK GND VCC NC
C
NC CS#1 CS#2 W#/ACC/IO2 NC
D
NC SO/IO1 SI/IO1 HOLD#/IO3 NC
E
NC NC NC NC NC
A pplication Note
3.2 SPI Flash Package Drawings

Applicable package drawings are provided in each SPI Flash data sheet. These drawings are included here
in Figure 3.12 through Figure 3.18 for reference.
Figure 3.12 SOC 008 – Wide 8-Pin Plastic Small Outline 208 mils Body Width Package
3 4
0.20 C A-B
D
H
A 5 D SEE
DETAIL B WITH
PLATING
9 b1
c c1
3 4
E
E1
(b)
BASE
E1/2 7
E/2 METAL
SECTION A-A
e 0.33 C
b q2
B 5 0.25 M C A-B D
0.07 R MIN.
H
0.10 C GAUGE
PLANE
A
A2 0.10 C
A SEATING
PLANE
SEATING PLANE q1 A
A1 C L2
C L q
L1
DETAIL B
NOTES:
1. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
PACKAGE SOC 008 (inches) SOC 008 (mm) 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
JEDEC 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
SYMBOL MIN MAX MIN MAX PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
A 0.069 0.085 1.753 2.159 . PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
A1 0.002 0.0098 0.051 0.249 FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
A2 0.067 0.075 1.70 1.91 DIMENSIONS ARE DETERMINED AT DATUM H.
b 0.014 0.019 0.356 0.483 4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
b1 0.013 0.018 0.330 0.457 BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
c 0.0075 0.0095 0.191 0.241 MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
c1 0.006 0.008 0.152 0.203 FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
D 0.208 BSC 5.283 BSC
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
E 0.315 BSC 8.001 BSC
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
E1 0.208 BSC 5.283 BSC THE SPECIFIED PACKAGE LENGTH.
e .050 BSC 1.27 BSC 7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
L 0.020 0.030 0.508 0.762 BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
L1 .055 REF 1.40 REF 8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
L2 .010 BSC 0.25 BSC IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
N 8 8 CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
θ 0˚ 8˚ 0˚ 8˚
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
θ1 5˚ 15˚ 5˚ 15˚ THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
θ2 0˚ 0˚ AREA INDICATED.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
3432 \ 16-038.03 \ 10.28.04
Figure 3.13 SO3 016 – 16-Pin Wide Plastic Small Outline Package (300 mil Body Width)
NOTES:
PACKAGE SO3 016 (inches) SO3 016 (mm) 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
JEDEC MS-013(D)AA MS-013(D)AA 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
D 0.406 BSC 10.30 BSC
E 0.406 BSC 10.30 BSC
h 0.10 0.30 0.25 0.75
θ 0˚ 8˚ 0˚ 8˚ THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
θ1 5˚ 15˚ 5˚ 15˚ AREA INDICATED.
θ2 0˚ 0˚ 10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
3601 \ 16-038.03 \ 8.31.6
A pplication Note
Figure 3.14 SL3 016 – 16-Pin Wide Plastic Small Outline Package
NOTES:
PACKAGE SL3016 (inches) SL3016 (mm) 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
JEDEC MS-013(D)AA MS-013(D)AA 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
D 0.406 BSC 10.30 BSC
E 0.406 BSC 10.30 BSC
h 0.10 0.30 0.25 0.75
θ 0° 8° 0° 8° THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
θ1 5° 15° 5° 15° AREA INDICATED.
θ2 0° 0° 10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
3644 \ 16-038.03 Rev C \ 02.03.10 (JK)
Figure 3.15 USON 8-contact (5 x 6 mm) No-Lead Package
NOTES:
QUAD FLAT NO LEAD PACKAGES (UNE) - PLASTIC
1. DIMENSIONING AND TOLERANCING CONFORMS TO
DIMENSIONS
ASME Y14.5M-1994.
SYMBOL MIN NOM MAX NOTE
2. ALL DIMENSIONS ARE IN MILLIMETERS, 0 IS IN DEGREES.
e 1.27 BSC
3. N IS THE TOTAL NUMBER OF TERMINALS.
N 8 3
4. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS
ND 4 5 MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP.
IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER
L 0.55 0.60 0.65
END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE
b 0.35 0.40 0.45 4 MEASURED IN THAT RADIUS AREA.
D2 3.90 4.00 4.10 5. ND REFERS TOT HE NUMBER OF TERMINALS ON D SIDE.
E2 3.30 3.40 3.50 6. MAXIMUM PACKAGE WARPAGE IS 0.05 mm.
D 5.00 BSC 7. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS.
E 6.00 BSC 8. PIN #1 ID ON TOP WILL BE LASER MARKED.
A 0.45 0.50 0.55 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED
HEAT SINK SLUG AS WELL AS THE TERMINALS.
A1 0.00 0.02 0.05
K 0.20 MAX.
θ 0 --- 12 2
3448\ 16-038.28 \ 04.15.05
A pplication Note
Figure 3.16 WSON 8-Contact (6 x 8 mm) No-Lead Package

D A (DATUM A) D2
B PIN #1 ID D2/2
N R0.20 NX L
1 2
E2/2
9.
E
E2
0.30 DIA TYP.

8.
2X 0.10 C
1 2
K
N N-1
2X 0.10 C TOP VIEW
NX b 4.
0.10 C e 0.10. M C A B
C
A (ND-1) X e 0.05. M C
9. 0.05 C
SEATING PLANE 5.
SEE DETAIL "A"
A1 SIDE VIEW DATUM A BOTTOM VIEW
L
L1 10.
e/2
TERMINAL TIP
e 4.
DETAIL "A"
NOTES:
QUAD FLAT NO LEAD PACKAGES (WSNB) - PLASTIC
1. DIMENSIONING AND TOLERANCING CONFORMS TO
DIMENSIONS
ASME Y14.5M-1994.
SYMBOL MIN NOM MAX NOTE
2. ALL DIMENSIONS ARE IN MILLIMETERS, SYM θ IS IN DEGREES.
e 1.27 BSC
3. N IS THE TOTAL NUMBER OF TERMINALS.
N 8 3
4. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS
ND 4 5 MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP.
IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER
L 0.45 0.50 0.55
END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE
b 0.35 0.40 0.45 4 MEASURED IN THAT RADIUS AREA.
D2 4.70 4.80 4.90 5. ND REFERS TOT HE NUMBER OF TERMINALS ON D SIDE.
E2 6.30 6.40 6.50 6. MAXIMUM PACKAGE WARPAGE IS 0.05 mm.
D 6.00 BSC 7. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS.
E 8.00 BSC 8. PIN #1 ID ON TOP WILL BE LASER MARKED.
A 0.70 0.75 0.80 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED
HEAT SINK SLUG AS WELL AS THE TERMINALS.
A1 0.00 0.02 0.05
10. A MAXIMUM 0.15 mm PULL BACK (L1) MAY BE PRESENT.
L1 0.15 MAX. 10
θ 0 --- 12 2
K 0.20 MIN.
3408\ 16-038.28a
Figure 3.17 FAB024 and ZSA024 24-ball Ball Grid Array (6 x 8 mm) Packages
PACKAGE ZSA024 NOTES:

JEDEC N/A 1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
DxE 8.00 mm x 6.00 mm
PACKAGE 2. ALL DIMENSIONS ARE IN MILLIMETERS.
SYMBOL MIN NOM MAX NOTE 3. BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
A --- --- 1.20 PROFILE
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
A1 0.20 --- --- BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
A2 0.70 --- 0.90 BODY THICKNESS DIRECTION.
D 8.00 BSC. BODY SIZE SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
E 6.00 BSC. BODY SIZE "E" DIRECTION.
D1 4.00 BSC. MATRIX FOOTPRINT n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E1 4.00 BSC. MATRIX FOOTPRINT
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
MD 5 MATRIX SIZE D DIRECTION DIAMETER IN A PLANE PARALLEL TO DATUM C.
ME 5 MATRIX SIZE E DIRECTION DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE
n 24 BALL COUNT CROWNS OF THE SOLDER BALLS.
Øb 0.35 0.40 0.45 BALL DIAMETER 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
eE 1.00 BSC. BALL PITCH BALL IN THE OUTER ROW.
eD 1.00 BSC BALL PITCH WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
SD / SE 0.00 SOLDER BALL PLACEMENT OUTER ROW SD OR SE = 0.000.
A1 DEPOPULATED SOLDER BALLS WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3645 16-038.86 Rev A \ 02.26.10
A pplication Note
Figure 3.18 FAC024 24-ball Ball Grid Array (6 x 8 mm) Package
PACKAGE FAC024 NOTES:

JEDEC N/A 1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
DxE 8.00 mm x 6.00 mm NOM
PACKAGE 2. ALL DIMENSIONS ARE IN MILLIMETERS.
SYMBOL MIN NOM MAX NOTE 3. BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
A --- --- 1.20 PROFILE
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
A1 0.25 --- --- BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
A2 0.70 --- 0.90 BODY THICKNESS DIRECTION.
D 8.00 BSC. BODY SIZE SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
E 6.00 BSC. BODY SIZE "E" DIRECTION.
D1 5.00 BSC. MATRIX FOOTPRINT n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E1 3.00 BSC. MATRIX FOOTPRINT
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
MD 6 MATRIX SIZE D DIRECTION DIAMETER IN A PLANE PARALLEL TO DATUM C.
ME 4 MATRIX SIZE E DIRECTION DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE
N 24 BALL COUNT CROWNS OF THE SOLDER BALLS.
Øb 0.35 0.40 0.45 BALL DIAMETER 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
e 1.00 BSC. BALL PITCHL BALL IN THE OUTER ROW.
SD/ SE 0.5/0.5 SOLDER BALL PLACEMENT WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
DEPOPULATED SOLDER BALLS OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
J PACKAGE OUTLINE TYPE OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10 OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3642 F16-038.9 \ 09.10.09
4. Land Patterns Recommendations

Applicable PCB land pattern recommendations for SOC 008, SO3 016, SL3 016, USON, WSON, FAB024,
FAC024 and ZSA024 packages are provided here in Figure 4.1 through Figure 4.6.
Note: All dimensions are in mm.
Figure 4.1 SOC 008 Proposed Land Pattern
Proposed Land Pattern

b3
Description Symbol Max Min
Land Pad l1 0.1 BSC

Tips
Land Pad
l2 0.862 0.762
He Length
Land Pad
b3 0.495 0.483
Width
Overall
He 8.201 8.001
Width
Terminal
Pitch e 1.27 BSC
l2
l1
e
4.305 mm
A pplication Note
Figure 4.2 SO3 016 & SL3 016 Proposed Land Pattern
b3
He
l2
l1
e
9.52 max
Description Symbol Max Min
Land Pad l1 0.1 BSC

Tips
Land Pad
l2 1.37 1.27
Length
Land Pad
b3 0.63 0.51
Width
Overall
He 10.50 10.30
Width
Terminal
Pitch e 1.27 BSC
Figure 4.3 USON Proposed Land Pattern
A pplication Note
Figure 4.4 WSON Proposed Land Pattern
Figure 4.5 FAB024 and ZSA024 Proposed Land Pattern
Figure 4.6 FAC024 Proposed Land Pattern
4.1 BGA Land Pad Recommendations

PCB solder-ball land pads can be either non-solder-mask defined (NSMD) or solder-mask-defined (SMD).
For NSMD configurations, there is a small gap between the solder pad and the solder mask. Solder will flow
into the gap between the pad and the solder mask (reference Figure 4.7). For SMD configurations, the solder
mask covers the outer edge of the solder pad. Solder is prevented from flowing over the edges of the pad by
the solder mask.
A pplication Note
Figure 4.7 SMD vs. NSMD Landing Pad Definition
Solder Solder
Pad Pad
Mask Mask
Mask Opening Pad

Pad Mask
Opening
Board Material Board material
NSMD SMD
NSMD is generally the recommended land pad configuration because it enables a stronger bond between the
solder pad and the solder ball with less stress concentration.
For SMD configurations, it is good practice to make the solder mask opening the same size as the diameter of
the solder ball. On NSMD configurations, the solder pad should be between 80% and 100% of the solder ball
diameter and the solder mask opening should be 0.15 mm larger than the solder pad to provide ample space
for excess solder. Table 4.1 provides dimensional recommendations for SMD and NSMD configurations
suitable for use with the FAB024, FAC024 and ZSC024 packages.
Table 4.1 NSMD and SMD Dimensional Recommendations for BGA Packages
Configuration Opening Recommended Dimension

Solder Pad 0.55 mm
SMD
Solder Mask 0.45 mm
Solder Pad 0.45mm
NSMD
Solder Mask 0.60 mm
5. Printed Circuit Board Design Recommendations

This section contains general layout recommendations.
5.1 Power Supply Decoupling

All S25FL and S70FL SPI Flash have one power supply input pin (VCC) and one ground pin (GND).
Additionally, certain models support a separate I/O supply input pin (VIO) for applications that require I/O
levels to be less than VCC. Use of one 0.1 µF ceramic capacitor, normally in a 0603 or 0402 package, is
recommended for decoupling each power supply input pin. A decoupling capacitor should be placed as close
as possible to the VCC supply input pin, as well as the VIO supply input pin if present.
The routing of the decoupling capacitor should be optimized to achieve low inductance. Power supply trace
lengths from the package pads to the vias should be as short as possible with a trace width of approximately
0.6 mm. It is recommended to avoid sharing the same via with 2 or more decoupling capacitors. Figure 5.1
shows examples of routing the decoupling capacitor.
Figure 5.1 Routing with Decoupling Capacitor

T oo lo ng trac e
` `
` `
G oo d e xam ple s
S hared via
` `
` ` ` `
(i) (ii)
5.2 Clock Signal Routing

For reliable high speed synchronous data transfers, it is essential for the clock signal to have very good signal
integrity. The following recommendations should be taken into consideration when routing the clock signal.
 Run the clock signal at least 3x of the trace width away from all other signal traces. This will help keep clock
signal clean from noise, reference Figure 5.2.
 Use as few vias as possible for the entire path of the clock signal. Each via will create impedance changes
and signal reflections.
 Run the clock trace as straight as possible and avoid using serpentine routing, reference Figure 5.3.
 Keep a continuous ground in the next layer as a reference plane.
 Route the clock trace with controlled impedance, typically a 50 Ohm trace impedance with ± 5% tolerance.
Figure 5.2 Separate Clock from other Traces
3X 3X
S ig n a l trace s
C lo ck trace
A pplication Note
Figure 5.3 Straight Trace Runs for Clock
A void serpen tin e for clock

R un straight trace for clock
5.3 Data Signal Routing

The FL Flash support 1, 2 and 4-bit data bus configurations. In 2 and 4-bit multiple I/O configurations, it is
important that the I/O traces are routed such that they have identical lengths, within ~ 3 mm, to assure
equivalent propagation delays. To assure reliable data transfers for all configurations it is important that the
propagation delays for the clock trace and all data traces are identical.
The data signals should be routed with traces of controlled impedance to reduce signal reflection. Data traces
should have no 90° angle corners. The preferred method for implementing a 90° angle change is to cut the
corner to smooth the trace, reference Figure 5.4. To maximize signal integrity, avoid using multiple signal
layers for data signal routing and ensure all signal traces have a continuous reference plane.
Figure 5.4 Signal Routing at the Corner
S m o o th co rn e r re d uce s
S h a rp co rn e r cau ses re flection
m o re re flectio n
5.4 Via Routing

Vias should not be placed within a land pad as this can cause solder wicking inside the via hole, resulting in
misshapen solder joints and electrical opens. Vias should be placed a minimum of 0.3 mm away from the
solder pad as shown in Figure 5.5.
Figure 5.5 Recommended via Placement
0.
30
m
m
5.5 Escape Path Routing

Maintaining good signal integrity must be a top priority when considering BGA escape path routing. Only one
signal trace should be routed between any two adjacent land pads, reference Figure 5.6.
Figure 5.6 Escape Path Routing (example: FAB024)
6. Summary
The Spansion S25FL serial peripheral flash devices utilize industry standard packages. PCB layout for
Spansion SPI flash requires use of standard high speed board layout principals.
A pplication Note
7. Revision History
Section Description
Revision 01 (July 2, 2010)
Initial Release
App l ic atio n No t e
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
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the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
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Copyright © 2010 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™ and
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Spansion® Serial Peripheral Interface

(SPI) FL Flash Layout Guide

2. Basic SPI Flash Connectivity

Host SCK SCK S25FL

Multi I/O Configuration

SCK SCK S25FL

Publication Number SPI_Layout_Guide_AN Revision 01 Issue Date July 2, 2010

Host SCK SCK S70FL

Multi I/O Configuration

SCK SCK S70FL

Figure 2.3 Simplified Multi- SPI Device Connection Diagram

SPI SCK SO S1 SCK SO S1 SCK SO S1

3. SPI Flash Packaging

Table 3.1 Device Availability Matrix

3.1 SPI Flash Package Connection Diagrams

Figure 3.1 SOC 008 wide – S25FL032P

SO / IO1 2 7 HOLD# / IO3

Figure 3.2 SO3 016 – S25FL128P

Figure 3.3 016 – S25FL032P/064P/129P

Figure 3.4 SO3 016 – S29FL128S/256S/512S

Figure 3.5 SL3 016 – S70FL256P

Figure 3.6 USON – S25FL032P

Figure 3.7 WSON – S25FL128P

Figure 3.8 WSON – S25FL032/064/129P, S25FL128/256S

Figure 3.9 FAB024 – S25FL032/064/129P, S25FL128/256S

Figure 3.10 FAC024 – S25FL032/064/129P, S25FL128/256S

Figure 3.11 ZSA024 – S70FL256P

3.2 SPI Flash Package Drawings

Figure 3.15 USON 8-contact (5 x 6 mm) No-Lead Package

3448\ 16-038.28 \ 04.15.05

Figure 3.16 WSON 8-Contact (6 x 8 mm) No-Lead Package

0.30 DIA TYP.

PACKAGE ZSA024 NOTES:

3645 16-038.86 Rev A \ 02.26.10

Figure 3.18 FAC024 24-ball Ball Grid Array (6 x 8 mm) Package

PACKAGE FAC024 NOTES:

3642 F16-038.9 \ 09.10.09

4. Land Patterns Recommendations

Figure 4.1 SOC 008 Proposed Land Pattern

Proposed Land Pattern

Description Symbol Max Min

Land Pad l1 0.1 BSC

Description Symbol Max Min

Land Pad l1 0.1 BSC

Figure 4.3 USON Proposed Land Pattern

Figure 4.4 WSON Proposed Land Pattern

Figure 4.5 FAB024 and ZSA024 Proposed Land Pattern

Figure 4.6 FAC024 Proposed Land Pattern

4.1 BGA Land Pad Recommendations

Figure 4.7 SMD vs. NSMD Landing Pad Definition

Mask Opening Pad

Configuration Opening Recommended Dimension

5. Printed Circuit Board Design Recommendations

5.1 Power Supply Decoupling

Figure 5.1 Routing with Decoupling Capacitor

5.2 Clock Signal Routing

Figure 5.2 Separate Clock from other Traces

Figure 5.3 Straight Trace Runs for Clock

A void serpen tin e for clock