TW2802/4 Multiple Video Decoder: Preliminary Data Sheet From Techwell, Inc

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TW2802/4 Multiple Video Decoder

For Security Applications
Preliminary Data Sheet from Techwell, Inc.

Information may change without notice
Disclaimer
This document provides technical information for the user. Techwell Inc. reserves the right to
modify the information in this document as necessary. The customer should make sure that
they have the most recent data sheet version. Techwell Inc. holds no responsibility for any
errors that may appear in this document. Customers should take appropriate action to ensure
their use of the products does not infringe upon any patents. Techwell Inc. respects valid
patent rights of third parties and does not infringe upon or assist others to infringe upon such
rights.
Techwell, Inc. 09/09/2003

www.techwellinc.com Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder Preliminary
Table of Contents
TMPSENS (Temporal Sensitivity) ____ 20
Introduction and Features ______________3
Velocity Control _________________ 21
Features ___________________________3 Mask Detection Region____________ 22
Applications _______________________3 Output Format ___________________ 23
Block Diagram _____________________4 ITU-R BT.656 Format ____________ 23
8-bit ITU-R BT.601 Format ________ 24
Pin Diagram _______________________5
Dual ITU-R BT.656 Format in 54MHz 25
Pin Description _____________________5
Host Interface ______________________ 26
Analog Interface Pins _______________5
Digital Data Interface Pins ___________6 Serial Interface ___________________ 26
System Control Pins ________________7 Parallel Interface _________________ 27
Power/Ground Pins_________________7
Interrupt Interface ________________ 28
Functional Description _________________8
Control Register __________________ 29
Video Input Formats ________________8 Register Map____________________ 29
Analog-to-Digital Converter __________8 Recommended Value _____________ 31
Register Description ______________ 33
Sync Processing ____________________9
Video Level Adjustment ____________9 Parametric Information_______________ 71
Horizontal Sync Processing __________9 DC Electrical Parameters___________ 71
Vertical Sync Processing ____________9
AC Electrical Parameters___________ 73
Color Decoding ____________________10
Package Dimension __________________ 75
Decimation Filter _________________10
Y/C Separation ___________________11 Application Information ______________ 77
Luminance Processing ______________12 Video Input Interface ______________ 77
Chrominance Processing ____________13 Clamping / AGC __________________ 77

Chrominance Demodulation_________13
Video Output Interface ____________ 77
ACC (Automatic Color gain control) __14
Chrominance Gain, Offset and Hue Power-Up ________________________ 77
Adjustment ______________________14 Application Schematic ________________ 78
Video Scaling and Cropping _________15 Revision History_____________________ 79
Video Scaling ____________________15
Video Cropping __________________18
Motion Detector ___________________20

Sensitivity Control ________________20
LVLSENS (Level Sensitivity) ________20
SPTSENS (Spatial Sensitivity) _______20
Techwell, Inc. 09/09/2003

Introduction and Features
The TW280X includes four high quality − Four built-in motion detectors for
NTSC/ PAL video decoders, which convert security system
analog composite to digital component − Supports the standard ITU-R BT.656 /
YCbCr for security application. The TW280X 8bit ITU-R BT.601 format
contains four 10-bit A/D and proprietary − Supports two differently scaled output
digital gain/clamp controllers and utilizes mode with 54MHz ITU-R BT.656 format
proprietary techniques for separating lumin- − Supports a two-wire serial or parallel
ance & chrominance to reduce both cross- interface
luminance and cross-chrominance artifacts. − Low power consumption
The high performance dual scalers in each − 128 PQFP package
channel offer two differently scaled video
outputs with 54MHz ITU-R BT.656 format Applications
for security system design. Four built-in Security systems
motion detectors can also increase the
feature of security system.
Device Options
Device Name Features
Features TW2802 2 Channel Video Decoder
TW2804 4 Channel Video Decoder
− Accepts all NTSC (M/N/4.43) / PAL
(B/D/G/H/I/K/L/M/N/60) standard
formats with auto detection VIN1A
H/V Scaler
Color Decoder
VD1[7:0]
− Four 10-bit video CMOS analog to VIN1B
MUX ADC with
Comb Filter
H/V Scaler
VALID1
HS1
digital converters VS1
FLD1
Motion Detector H/V Sync Processor
ACTIV1
− Adjust video level with proprietary NVMD1
automatic clamp and gain control VIN2A Color Decoder

H/V Scaler
VD2[7:0]
MUX ADC with
system VIN2B Comb Filter
H/V Scaler
VALID2
HS2
− Proprietary architecture for locking to Motion Detector H/V Sync Processor

VS2
FLD2
ACTIV2
weak, noisy, or unstable signals NVMD2
− High performance adaptive comb filters VIN3A Color Decoder

H/V Scaler
VD3[7:0]
MUX ADC with
VALID3
for all NTSC/PAL standards VIN3B Comb Filter
H/V Scaler
HS3
− IF compensation filter for improvement

VS3
FLD3
ACTIV3
of color demodulation
NVMD3
− PAL delay lines for correcting PAL VIN4A

MUX ADC
Color Decoder
with
H/V Scaler
VD4[7:0]
VALID4
phase errors VIN4B Comb Filter
H/V Scaler
HS4
VS4
− Programmable hue, saturation, contrast, Motion Detector H/V Sync Processor
FLD4
ACTIV4
NVMD4
brightness and sharpness HSPB
HCSB
HALE
−
Host Interface Clock Generator CLK27O
Dual high quality horizontal and vertical HRDB
HWRH
HDAT
down scaler for each channel IRQ CLK54I
Techwell, Inc. 3 09/09/2003

Block Diagram
H/V Scaler
VIN1A Color Decoder
VD1[7:0]
MUX ADC with
VALID1
VIN1B Comb Filter
H/V Scaler
HS1
VS1
FLD1
ACTIV1
NVMD1
H/V Scaler
VIN2A Color Decoder
VD2[7:0]
MUX ADC with
VALID2
VIN2B Comb Filter
H/V Scaler
HS2
VS2
FLD2
ACTIV2
NVMD2
H/V Scaler
VIN3A Color Decoder
VD3[7:0]
MUX ADC with
VALID3
VIN3B Comb Filter
H/V Scaler
HS3
VS3
FLD3
ACTIV3
NVMD3
H/V Scaler
VIN4A Color Decoder
VD4[7:0]
MUX ADC with
VALID4
VIN4B Comb Filter
H/V Scaler
HS4
VS4
FLD4
ACTIV4
NVMD4
HSPB
HCSB
HALE
Host Interface Clock Generator CLK27O
HRDB
HWRH
HDAT
IRQ CLK54I

Pin Diagram
102
101
100
77
75
73
71
68
66
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
76
74
72
70
69
67
65
VDDO
VDDO
HS4
FLD4
CLK27O
VSS
CLK54I
VD4[0]
VD4[5]
VD4[6]
VSS
VALID4
ACTIVE4
VS4
VDD
VDD
VDD
HDAT[0]
VSS
HDAT[3]
VSS
HDAT[5]
VSS
HDAT[6]
VSS
VD4[1]
VD4[2]
VD4[3]
VD4[4]
VSS
VD4[7]
VSS
VD3[0]
HDAT[1]
HDAT[2]
HDAT[4]
HDAT[7]
NVMD4
103 IRQ VD3[1] 64
104 HWRB VSS 63
105 VDDO VD3[2] 62
106 HRDB VD3[3] 61
107 HALE VDD 60
108 VSS VD3[4] 59
109 HCSB VD3[5] 58
110 HSPB VSS 57
111 VDDAD VD3[6] 56
112 VDDA VD3[7] 55
113 VIN1A VSS 54
114 VIN1B VALID3 53
115
116
VSSA
VSSA
TW280X ACTIVE3
VSS
52
51
117 VIN2A (128QFP) HS3 50
118 VIN2B VS3 49
119 VDDA Analog Pin VDD 48
120 VDDA (4 ADC) FLD3 47
121 VIN3A NVMD3 46
122 VIN3B VDDO 45
123 VSSA VD2[0] 44
124 VSSA VD2[1] 43
125 VIN4A VSS 42
126 VIN4B VD2[2] 41
127 VDDA VD2[3] 40
128 VSSAD VSS 39
ACTIVE1
ACTIVE2
NVMD1
NVMD2
VALID2
VALID1
VD1[7]
VD1[4]
VD1[3]
VD1[1]
VD2[6]
VD2[5]
VD1[6]
VD1[5]
VD1[2]
VD1[0]
VD2[7]
VD2[4]
VDDO
VDDO
RSTB
TEST
FLD2
FLD1
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HS1
HS2
VS2
VS1
26
28
30
32
35
37
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
29
31
33
34
36
38
2
8
9
1
Pin Description
Analog Interface Pins

Name Number Type Description
Composite video input A of Channel 1.
VIN1A 113 A
Must be connected through 2.2uF cap to input.
Composite video input B of Channel 1.
VIN1B 114 A
VIN2A 117 A
VIN2B 118 A
VIN3A 121 A
VIN3B 122 A
VIN4A 125 A
VIN4B 126 A

Digital Data Interface Pins
13,14,16,17,
VD1 [7:0] O Dual scaled video data output for channel 1.
19,20,22,23
34,35,37,38,
VD2 [7:0] O Dual scaled video data output for channel 2.
40,41,43,44
55,56,58,59,
VD3 [7:0] * O Dual scaled video data output for channel 3.
61,62,64,65
76,77,79,80,
VD4 [7:0] * O Dual scaled video data output for channel 4.
82,83,85,86
VALID1 11 O Valid data indicator for channel 1.
VALID2 32 O Valid data indicator for channel 2.
VALID3* 53 O Valid data indicator for channel 3.
VALID4* 74 O Valid data indicator for channel 4.
HS1 8 O Horizontal sync output for channel 1.
HS2 29 O Horizontal sync output for channel 2.
HS3* 50 O Horizontal sync output for channel 3.
HS4* 71 O Horizontal sync output for channel 4.
VS1 7 O Vertical sync output for channel 1.
VS2 28 O Vertical sync output for channel 2.
VS3* 49 O Vertical sync output for channel 3.
VS4* 70 O Vertical sync output for channel 4.
FLD1 5 O Even/odd field flag output for channel 1.
FLD2 26 O Even/odd field flag output for channel 2.
FLD3* 47 O Even/odd field flag output for channel 3.
FLD4* 68 O Even/odd field flag output for channel 4.
ACTIVE1 10 O Active flag output for channel 1.
ACTIVE2 31 O Active flag output for channel 2.
ACTIVE3* 52 O Active flag output for channel 3.
ACTIVE4* 73 O Active flag output for channel 4.
NVMD1 4 O Video loss or Motion detection flag for channel 1.
NVMD2 25 O Video loss or Motion detection flag for channel 2.
NVMD3* 46 O Video loss or Motion detection flag for channel 3.
NVMD4* 67 O Video loss or Motion detection flag for channel 4.
Notes: * Disabled for TW2802

System Control Pins
RSTB 2 I System reset.
CLK54I 89 I 54MHz system clock input.
CLK27O 88 O 27MHz Clock output.
TEST 1 I Test pin. Connect to ground.
HSPB 110 I Select Serial/Parallel host interface.
Chip select for parallel interface.
HCSB 109 I
Slaver address [0] for serial interface.
Address line enable for parallel interface.
HALE 107 I
Serial clock for serial interface.
Read enable for parallel interface.
HRDB 106 I
Ground for serial interface.
Write enable for parallel interface.
HWRB 104 I
Ground for serial interface.
Data bus for parallel interface.
91,92,94,95, HDAT [7] is serial data for serial interface.
HDAT [7:0] I/O
97,98,100,101 HDAT [6:1] is slaver address [6:1] for serial
interface. HCSB is slaver address [0].
Interrupt request by video loss and Motion
IRQ 103 O
detection
Power/Ground Pins
9,21,33,48,60,
VDD P Digital power for internal logic. 2.5V.
72,90,102
6,24,45,
VDDO P Digital power for output driver. 3.3V.
66,84,105
3,12,15,18, 27,
30,36,39,42,51,
VSS 54,57,63,69,75, G Digital ground.
78,81,87,93,96,
99,108
VDDA 112,119,120,127 P Analog power. 2.5V.
VSSA 115,116,123,124 G Analog ground.
VDDAD 111 P Analog digital power. 2.5V.
VSSAD 128 G Analog digital ground.

Functional Description
Video Input Formats

The TW280X supports all NTSC/PAL standard formats and has built-in automatic standard
detection circuit. The following Table 1 shows the identified standards. Automatic standard
detection can be overridden by writing the value into the IFMTMAN and IFORMAT register
(0x01, 0x41, 0x81, 0xC1). Even in no-video status, the device can be forced to free-run in a
particular video standard mode for fast locking by programming IFORMAT register.
Table 1 Input Video Format Supported

Format Line/Fv (Hz) Fh (KHz) Fsc (MHz)
NTSC-M*
525/59.94 15.734 3.579545
NTSC-J
NTSC-4.43* 525/59.94 15.734 4.43361875
NTSC-N 625/50 15.625 3.579545
PAL-BDGHI
625/50 15.625 4.43361875
PAL-N*
PAL-M* 525/59.94 15.734 3.57561149
PAL-NC 625/50 15.625 3.58205625
PAL-60 525/59.94 15.734 4.43361875
Notes: * 7.5 IRE Setup
Analog-to-Digital Converter
The TW280X contains four 10-bit Analog to Digital converters that digitizes the analog video
inputs. As the inputs are digitized at greater than two times that of the Nyquist sampling rate,
only simple external anti-aliasing LPF are needed to prevent out-of-band frequencies. Each
ADC has two analog switches that are controlled by ANA_SW (0x22, 0x62, 0xA2, 0xE2)
registers. The A/D converters can also be put into power-down mode by the ADC_PWDN
(0x78) registers.

Sync Processing
The sync processor of TW280X detects horizontal synchronization and vertical synchronization
signals in the composite. The TW280X utilizes proprietary technology for locking to weak, noisy,
or unstable signals such as those from on air signal and fast forward or backward of VCR
system.
Video Level Adjustment

A patented digital gain and clamp control circuit restores the ac coupled video signal to a fixed
dc level. The clamping circuit provides line-by-line restoration of the video pedestal level to a
fixed dc reference voltage. In no AGC mode, the gain control circuit adjusts only the video sync
gain to achieve desired sync amplitude so that the active video is bypassed regardless of the
gain control. But when AGC mode is enabled, both active video and sync are adjusted by the
gain control. The range of AGC is from –6dB to 18dB approximately.
Horizontal Sync Processing

The horizontal synchronization processing contains a sync separator, a PLL and the related
decision logic. The horizontal sync separator detects the horizontal sync by examining low-pass
filtered video input whose level is lower than a threshold. Additional logic is also used to avoid
false detection on glitches. The horizontal PLL locks onto the extracted horizontal sync in all
conditions to provide jitter free image output. In case the horizontal sync is missing, the PLL is
on free running status that matches the standard raster frequency.
Vertical Sync Processing

The vertical sync separator detects the vertical synchronization pattern in the input video
signals. The field status is determined at vertical synchronization time. When the location of the
detected vertical sync is inline with a horizontal sync, it indicates a frame start or the odd field
start. Otherwise, it indicates an even field.

Color Decoding
Decimation Filter
The digitized composite video data at 2X pixel clock rate first passes through decimation filter.
The decimation filter is required to achieve optimum performance and prevent high frequency
components from being aliased back into the video image. Fig 1 shows the characteristic of the
decimation filter.
-10
Magnitude Response (dB)
-20
-30
-40
-50
-60
0 2 4 6 8 10 12
Frequency (Hertz) 6
x 10
Fig 1 The Characteristic of the Decimation Filter
Techwell, Inc. 10 09/09/2003

Y/C Separation
The adaptive comb filter is used for high quality luminance/chrominance separation from
NTSC/PAL composite video signals. The comb filter improves the luminance resolution and
reduces noise such as cross-luminance and cross-color. The adaptive algorithm eliminates
most of errors without introducing new artifacts or noise. To accommodate some viewing
preferences, additional chrominance trap filters are also available in the luminance path. Fig. 2
and Fig 3 show the frequency response of notch filter for each system NTSC and PAL.
-10
-20
-30
-40
-50
-60
0 1 2 3 4 5 6
Frequency (Hertz) 6
x 10
Fig. 2 The Characteristics of Luminance Notch Filter for NTSC
-10
-20
-30
-40
-50
-60
0 1 2 3 4 5 6
Frequency (Hertz) 6
x 10
Fig 3 The Characteristics of Luminance Notch Filter for PAL
Techwell, Inc. 11 09/09/2003

Luminance Processing
The luminance signal is separated by adaptive comb or trap filter is then fed to a peaking circuit.
The peaking filter enhances the high frequency components of the luminance signal. Fig. 4
shows the characteristics of the peaking filter for four different gain modes. The picture contrast
and brightness adjustment is provided through CONT (0x11, 0x51, 0x91, 0xD1) and BRT (0x12,
0x52, 0x92, 0xD2) registers. The contrast adjustment range is from approximately 0 to 200
percent, and the brightness adjustment is in the range of ±25 IRE. Moreover, a high frequency
coring function is also embedded in TW280X to minimize a high frequency noise. The coring
level is adjustable through the Y_H_CORE (0xF8) register.
5
Manitude Response (dB)
0
0 1 2 3 4 5 6
Frequency (Hertz) 6
x 10
Fig. 4. The Characteristic of Luminance Peaking filter
Techwell, Inc. 12 09/09/2003

Chrominance Processing
Chrominance Demodulation
The chrominance demodulation is done by first quadrature mixing for NTSC and PAL. The
mixing frequency is equal to the sub-carrier frequency of NTSC and PAL. After the mixing, a
LPF is used to remove 2X carrier signal and yield chrominance components. The LPF
characteristic can be selected for optimized transient color performance. In case of a mistuned
IF source, IF compensation filter makes up for any attenuation at higher frequencies or
asymmetry around the color sub-carrier. The gain for the upper chrominance side band is
controlled by IFCMP_MD (0x13, 0x53, 0x93, 0xD3) register. Fig. 5 and Fig. 6 show the
frequency response of IF-compensation filter and chrominance LPF.
10
5
-5
-10
-15
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Frequency (Hertz) 6
x 10
Fig. 5 The Characteristics of IF-compensation Filter
Techwell, Inc. 13 09/09/2003

-5
-10

-15
-20
-25
-30
-35
-40
-45
0 0.5 1 1.5 2 2.5 3 3.5 4
Frequency (Hertz) 6
x 10
Fig. 6 The Characteristics of Chrominance Low Pass Filter
ACC (Automatic Color gain control)

The ACC (Automatic Color gain Control) compensates for reduced amplitudes caused by high
frequency suppression in video signal. The range of ACC is from –6dB to 30dB approximately.
For black & white video or very weak & noisy signals, the color will be off by the internal color
killing circuit. The color killer function can also be always enabled or disabled by programming
CKIL (0x14, 0x54, 0x94, 0xD4) register.
Chrominance Gain, Offset and Hue Adjustment

The color saturation can be adjusted by changing the register SAT (0x10, 0x50, 0x90, 0xD0).
The Cb and Cr gain can be also adjusted independently by programming UGAIN (0x3C) and
VGAIN (0x3D) register. Likewise, the Cb and Cr offset can be programmed through U_OFF
(0x3E) and V_OFF (0x3F) registers. Hue control is achieved with phase shift of the digitally
controlled oscillator. The phase shift can be programmed through HUE (0x0F, 0x4F, 0x8F,
0xCF) register.
Techwell, Inc. 14 09/09/2003

Video Scaling and Cropping

The TW280X provides two methods to reduce the amount of video pixel data, scaling and
cropping. The scaling function provides video image at lower resolution while the cropping
function supplies only a portion of the video image.
Video Scaling
The TW280X includes a high quality horizontal and vertical down scaler. The video images can
be downscaled in both horizontal and vertical direction to an arbitrary size. The luminance
horizontal scaler includes an anti-aliasing filter to reduce image artifacts in the resized image
and a 32 poly-phase filter to accurately interpolate the value of a pixel. This results in more
aesthetically pleasing video as well as higher compression ratios in bandwidth-limited
applications. Fig 7 shows the frequency response of anti-aliasing filter for horizontal scaling and
Fig 8 shows the 32 poly-phase filter characteristics. Similarly, the vertical scaler also contains
an anti-aliasing filter and 16 poly-phase filter for down scaling. The filter characteristics are
shown in Fig. 9.
-5
-10
-15
-20
-25
-30
-35
-40
-45
0 1 2 3 4 5 6
Frequency (Hertz) 6
x 10
Fig 7 The Characteristics of Anti-aliasing filter for horizontal luminance scaling
Techwell, Inc. 15 09/09/2003

0.5
0.4
0.3
0.2
Magnitude Response (dB) 0.1
-0.1
-0.2
-0.3
-0.4
-0.5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Frequency (Hertz) 6
x 10
Fig 8 The Characteristics of Group delay for horizontal luminance scaling
-5
-10
-15
-20
-25
-30
-35
-40
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Vertical Frequency/Line Rate
Fig. 9 The Characteristics of Anti-aliasing filter for vertical luminance scaling
Techwell, Inc. 16 09/09/2003

Down scaling is achieved by programming the horizontal scaling register (HSCALE) and vertical
scaling register (VSCALE). When no scaled video image, the TW280X will output the number of
pixels per line as specified by the HACTIVE register. If the number of output pixels required is
smaller than the number specified by the HACTIVE register, the 16bit HSCALE register is used
to reduce the output pixels to the desired number.
Following equation is used to determine the horizontal scaling ratio to be written into the 16bit
HSCALE register.
HSCALE = [Npixel_desired/ HACTIVE] * (2^16 – 1)
Where Npixel_desired is the desired number of active pixels per line
For example, to scale full picture (HACTIVE is 720) to CIF (360 pixels), the HSCALE value can
be found as:
HSCALE = [320/720] * (2^16 – 1) = 0x7FFF
Following equation is used to determine the vertical scaling ratio to be written into the 16bit
VSCALE register.
VSCALE = [Nline_desired / VACTIVE] * (2^16 - 1)
Where Nline_desired is the desired number of active lines per field
For example, to scale full picture (VACTIVE is 240or288) to CIF (120/144 lines), the VSCALE
value can be found as:
VSCALE = [120 / 240] * (2^16 – 1) = 0x7FFF for 60Hz
VSCALE = [144 / 288] * (2^16 – 1) = 0x7FFF for 50Hz
The scaling ratios of popular case are listed in Table 2
Table 2 HSCALE and VSCALE value for some popular video formats
Scaling Output
Format HSCALE VSCALE
Ratio Resolution
NTSC 720x480 0xFFFF 0xFFFF
1
PAL 720x576 0xFFFF 0xFFFF
NTSC 360x240 0x7FFF 0x7FFF
1/2 (CIF)
PAL 360x288 0x7FFF 0x7FFF
NTSC 180x120 0x3FFF 0x3FFF
1/4 (QCIF)
PAL 180x144 0x3FFF 0x3FFF
Techwell, Inc. 17 09/09/2003

Video Cropping
The cropping function allows only subsection of a video image to be output. The active video
region is determined by HDELAY, HACTIVE, VDELAY and VACTIVE register as illustrated in
Fig 10. The first active line is defined by the VDELAY register and the first active pixel is defined
by the HDELAY register. The VACTIVE register can be programmed to define the number of
active lines in a video field, and the HACTIVE register can be programmed to define the number
of active pixels in a video line.
The horizontal delay register HDELAY determines the number of pixel delays between the
horizontal reference and the leading edge of the active region. The horizontal active register
HACTIVE determines the number of active pixels to be processed. Note that these values are
referenced to the pixel number before scaling. Therefore, even if the scaling ratio is changed,
the active video region used for scaling remains unchanged as set by the HDEALY and
HACTIVE register. In order for the cropping to work properly, the following equation should be
satisfied.
HDELAY + HACTIVE < Total number of pixels per line

Where the total number of pixels per line is 858 for 60Hz and 864 for 50Hz
To process full size region, the HDELAY should be set to 32 and HACTIVE set to 720 for both
60Hz and 50Hz system.
The vertical delay register (VDELAY) determines the number of line delays from the vertical
reference to the start of the active video lines. The vertical active register (VACTIVE)
determines the number of lines to be processed. These values are referenced to the incoming
scan lines before the vertical scaling. In order for the vertical cropping to work properly, the
following equation should be satisfied.
VDELAY + VACTIVE < Total number of lines per field

Where the total number of lines per field is 262 for 60Hz and 312 for 50Hz
To process full size region, the VDELAY should be set to 7 and VACTIVE set to 240 for 60Hz
and the VDELAY should be also set to 4 and VACTIVE set to 288 for 50Hz.
Techwell, Inc. 18 09/09/2003

V reference
VDELAY
VACTIVE
HDELAY HACTIVE
H reference
V reference
VDELAY
VACTIVE * VSCALE
VACTIVE
Cropping and Scaling

HACTIVE * HSCALE
HDELAY HACTIVE
H reference
Fig 10 The Effect of Cropping and Scaling Active Registers
Techwell, Inc. 19 09/09/2003

Motion Detector
The TW280X supports hardware motion detector for 4 channels individually. The motion
detection algorithm built in the TW280X uses difference between two luminance levels of the
adjacent two fields. Motion is detected for full screen image and each channel has 144(12x12)
mask regions, which enable or disable motion detection for that region. The motion detection
has several attributes, sensitivity and velocity of motion detector controlled by programming the
register. The Host takes the result of motion detection via IRQ or NVMD pin. Refer to the host
Interface for the detail.
Sensitivity Control
The motion detector has three sensitivity control parameters. One is level sensitivity control
parameter (LVLSENS), another is spatial sensitivity control parameter (SPTSENS), and a third
is temporal sensitivity control parameter (TMPSENS). The recommended values of sensitivity
control parameters for a proper operation are listed in Table 3
LVLSENS (Level Sensitivity)

In built-in motion detection algorithm, motion is detected when luminance level difference
between two fields is greater than the value, which is defined by LVLSENS. The smaller
LVLSENS value makes the motion detector sense more sensitively, and the larger is the
opposite. When LVLSENS is too small, the motion detector can be weak in noise.
SPTSENS (Spatial Sensitivity)

Motion detection from only luminance level difference between two fields is very weak in spatial
random noise. To remove the fake motion detection from the random noise, spatial filter is used.
SPTSENS adjusts the window size of the spatial filter to control the spatial sensitivity so that the
large SPTSENS value increases the immunity of spatial random noise.
TMPSENS (Temporal Sensitivity)

Likewise, temporal filter is used to remove the fake motion detection from the temporal random
noise. TMPSENS regulates the number of taps in the temporal filter to control the temporal
sensitivity so that the large TMPSENS value increases the immunity of temporal random noise.
Techwell, Inc. 20 09/09/2003

Table 3 The recommended values of sensitivity parameters for a proper operation
LVLSENS
TMPSENS SPTSENS
More Sensitive Less Sensitive
0 7 ~ 10
1 3 ~ 9
0
2 2 ~ 8
3 2 ~ 7
0 3 ~ 9
1 2 ~ 8
1
2 2 ~ 7
3 2 ~ 6
0 3 ~ 8
1 2 ~ 7
2
2 1 ~ 6
3 1 ~ 5
0 3 ~ 7
1 1 ~ 6
3
2 1 ~ 5
3 1 ~ 4
Velocity Control
Motion has various velocities. That is, in a fast motion an object appears and disappears rapidly
between the adjacent fields while in a slow motion it is to the contrary. As the built-in motion
detection algorithm uses the luminance level difference between two adjacent fields, a slow
motion is inferior in detection rate to a fast motion. To compensate this weakness, the
MDPERIOD parameter is used. MDPERIOD parameter adjusts the field interval in which the
luminance level is compared. Thus, for detection of a fast motion a small value is needed and
for a slow motion a large value is required. The parameter MDPERIOD value should be greater
than TMPSENS value.
Techwell, Inc. 21 09/09/2003

Mask Detection Region
The motion in the specific area can be ignored by the control of mask area. The full screen
image is divided into 144 (12x12) mask areas. If the mask bit in specific area is programmed
into high, the specific area is ignored in operation of motion detector, as illustrated in Fig. 11.
But for proper operation, more than 4 mask areas should be enabled in any case.
720 P ixels
M ask1[0] M ask1[1] M ask1[2] M ask1[3] M ask1[4] M ask1[5] M ask1[6] M ask1[7] M ask1[8] M ask1[9] M ask1[10] M ask1[11]
240 Lines for 60H z, 288 Lines for 50H z
M ask10[0] M ask10[1] M ask10[2] M ask10[3] M ask10[4] M ask10[5] M ask10[6] M ask10[7] M ask10[8] M ask10[9] M ask10[10]M ask10[11]
Fig. 11 Motion detection mask windows
Techwell, Inc. 22 09/09/2003

Output Format
The TW280X supports three 8bit output formats, ITU-R BT.656, 8bit ITU-R BT.601 and Dual
ITU-R BT.656 with 54MHz data format. The output data is synchronous with rising or falling
edge of CLK27O for ITU-R BT.656 and 8bit ITU-R BT.601 format and with rising edge of
CLK54I for Dual ITU-R BT.656 with 54MHz format. The polarity of CLK27O is controlled by the
CK27O_POL register (0x3B). For Dual ITU-R BT.656 with 54MHz format, two kinds of scaled
image are time-multiplexed with 54MHz. The output formats are selected by the OUT_FMT
register (0x22, 0x62, 0xA2, 0xE2).
ITU-R BT.656 Format

In ITU-R BT.656 format, SAV and EAV sequences are inserted into the data stream to indicate
the active video time. During the blanking time, the YCbCr outputs have a value 0x00 for Y, Cr
and Cb. It is noted that the number of active pixels per line is constant in this mode regardless
of the actual incoming line length. If scaling is used, the number of active pixels per line is
constant with invalid pixel indicated by the blanking code 0x00. The output timing is illustrated in
Fig. 12. The SAV and EAV sequences are shown in Table 4. An optional set of 656 SAV/EAV
code sequence can be enabled to identify no-video status using the NOVID_656 bit (0x22,
0x62, 0xA2, 0xE2).
CLK27O
VD[7:0] FFh 00h 00h XY 00h 00h 00h 00h FFh 00h 00h XY 00h 00h Cb0 Y0 Cr0 Y1 00h 00h
EAV code SAV code
HACIVE
VALID
Fig. 12 Timing Diagram of ITU-R BT.656 format on HSCALE = 16’h7FFF
Table 4 ITU-R 656 SAV and EAV Code Sequence

Condition 656 FVH Value SAV/EAV Code Sequence
Fourth
Field Vertical Horizontal F V H First Second Third Option
Normal
(Novideo)
EVEN Blank EAV 1 1 1 0xFF 0x00 0x00 0xF1 0x71
EVEN Blank SAV 1 1 0 0xFF 0x00 0x00 0xEC 0x6C
EVEN Active EAV 1 0 1 0xFF 0x00 0x00 0xDA 0x5A
EVEN Active SAV 1 0 0 0xFF 0x00 0x00 0xC7 0x47
ODD Blank EAV 0 1 1 0xFF 0x00 0x00 0xB6 0x36
ODD Blank SAV 0 1 0 0xFF 0x00 0x00 0xAB 0x2B
ODD Active EAV 0 0 1 0xFF 0x00 0x00 0x9D 0x1D
ODD Active SAV 0 0 0 0xFF 0x00 0x00 0x80 0x00
Techwell, Inc. 23 09/09/2003

8-bit ITU-R BT.601 Format
8-bit ITU-R BT.601 format is 8-bit YCbCr 4:2:2 data stream with additional timing information
such as syncs and field flag. The video output timing is illustrated in Fig 13 and Fig 14.
Analog
Input
Digital
Output
HS
VS
FLD
60Hz ODD Field
Analog
Input
Digital
Output
HS
VS VSMODE = 0
VSMODE = 1
FLD VSMODE = 0
VSMODE = 1
60Hz EVEN Field
Analog
Input
Digital
Output
HS
VS
FLD
50Hz ODD Field
Analog
Input
Digital
Output
HS
VS VSMODE = 0
VSMODE = 1
FLD VSMODE = 0
VSMODE = 1
50Hz EVEN Field
Fig 13 Vertical Timing for 60Hz / 50Hz Video
Techwell, Inc. 24 09/09/2003

HS
VS Tim ing 1 Tim ing 1
Tim ing 2 Tim ing 2
FLD Tim ing 1
Tim ing 2
Tim ing 1 : 40 system clo ck(54M H z) fo r the E ven field w ith VS M O D E = 1 o r O d d field
Tim ing 2 : 1760 system clo ck(54M H z) fo r the E ven field w ith VS M O D E = 0
Fig 14 Horizontal and Vertical Timing in Video Output
Dual ITU-R BT.656 Format in 54MHz

Dual ITU-R BT.656 format in 54MHz is very useful to the security applications, which need two
independently scaled video images for display and record purpose. In the case of HSCALE_X =
16’h7FFF and HSCALE_Y = 16’hFFFF, the timing diagram of video output is illustrated in Fig
15.
CLK27O
CLK54I
VD[7:0] FFh FFh 00h 00h 00h 00h XY XY 00h 00h 00h 00h FFh FFh 00h 00h 00h 00h XY XY 00h Cb0 00h Y0 Cb0 Cr0 Y0 Y1 Cr0 Cb2 Y1 Y2 00h Cr2 00h Y3
EAV code SAV code

HACIVE
VALID
Data : Scaled data output for Display purpose (X path)
Data : Scaled data output for Record purpose (Y path)
Fig 15 Timing Diagram in Dual ITU-R BT.656 with 54MHz format
Techwell, Inc. 25 09/09/2003

Host Interface
The TW280X provides I2C serial and parallel interfaces that can be selected by HSPB pin.
When HSPB is low, the parallel interface is selected, the serial interface for high. Some of the
interface pins serve a dual purpose depending on the working mode. The pins HALE and
HDAT[7] in parallel mode become SCLK and SDAT pins in serial mode respectively. Each
interface protocol is shown in the following figure.
Table 5 Pin Assignment for Serial/Parallel Interface

Pin Name Serial Mode Parallel Mode
HSPB HIGH LOW
HALE SCLK AEN
HRDB Not Used RENB
HWRB Not Used WENB
HCSB Slave Address[0] CSB
HDAT[0] Not Used PDATA[0]
HDAT[1] Slave Address[1] PDATA[1]
HDAT[7] SDAT PDATA[7]
Serial Interface
HDAT[6:1] and HCSB pins define slave address. Therefore, any slave address can be assigned
for full flexibility. TW2804 also supports auto index increments in write/read mode if the data are
in sequential order.
Start Slave address R/WB Ack Index Ack Data Ack Stop
SDAT MSB LSB MSB LSB MSB LSB
SCLK
Fig 16 Write mode in Serial Interface
Start Slave address R/WB Ack Index Ack Stop Start Slave address R/WB Ack Data NoAck Stop
“0” “1”
SDAT MSB LSB MSB LSB MSB LSB MSB LSB
SCLK
Fig 17 Read mode in Serial Interface
Techwell, Inc. 26 09/09/2003

Parallel Interface
The following figures show the write/read timing chart of parallel interface. The parallel interface
supports auto index increment after each byte of data is sent with WENB. Therefore, the host
can write multiple bytes to the slave without additional address if they are in sequential order.
The host completes the transfer cycle with CSB which is Low to High transition. Auto index
increment is also supported in read mode.
CSB
tsu(1) th(1)
WENB
tw
RENB
tw
AEN
PDATA
tsu(2) th(2) tsu(2) th(2)
Fig 18 Write mode in Parallel interface
CSB
tsu(1) th(1)
WENB
tw
RENB
tw
AEN
PDATA
tsu(2) th(2) td (1) td (2)
Fig 19 Read mode in Parallel interface
Table 6 Parallel Interface Timing Parameter

Parameter Symbol Min Typ Max Units
CSB setup until AEN active tsu (1) 10 ns
PDATA setup until AEN, WENB active tsu (2) 10 ns
AEN, WENB, RENB active pulse width tw 40 ns
CSB hold after WENB, RENB inactive th (1) 60 ns
PDATA hold after AEN, WENB inactive th (2) 60 ns
PDATA delay after RENB active td (1) 12 ns
PDATA delay after RENB inactive td (2) 12 ns
Techwell, Inc. 27 09/09/2003

Interrupt Interface
The TW280X provides the interrupt request function via an IRQ pin. Any video loss detection or
motion detection will make the IRQ pin high until cleared via register IRQCLR (0x39) by the
host. The host processor will read the interrupt status register DET_NVMD (0x38) to find out
which channel has sensed motion or video loss. Writing high to the corresponding bit of the
interrupt clear register IRQCLR (0x39) will clear the interrupt request. Each interrupt status bit
also has its mask bit (0x3A) to disable the interrupt for that function. This sequence is described
in Fig 20.
The TW280X also provides the video loss detection or motion detection flag of individual
channel via NVMD pins. Four NVMD pins have respective channel information of motion or
video loss so that host takes status information directly by reading these pins. Its mode is
controlled by NVMDB (0x3B) that is set “1” for video loss flag and “0” for motion detection flag.
N o V id eo D etectio n
M o tio n D etectio n
M o tio n D etectio n
o n C hannel 4
o n C hannel 3
o n C hannel 2
IRQ Pin output
Status Register 0x00 0x80 0x00 0x04 0x02 0x00
Clear Register 0x80 0x04 0x02

C lear by H o st C lear by H o st C lear b y H ost
Fig 20 Timing Diagram of Interrupt Interface
Techwell, Inc. 28 09/09/2003

Control Register
Register Map
Address
Mnemonic BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
CH1 CH2 CH3 CH4
0x00 0x40 0x80 0xC0 VIDSTAT * DET_FORMAT DET_COLOR LOCK_COLOR LOCK_GAIN LOCK_OFFSET LOCK_HPLL
0x01 0x41 0x81 0xC1 FORMAT IFMTMAN IFORMAT 0 1 DET_NONSTD * DET_FLD60 *
0x02 0x42 0x82 0xC2 AGC_PLL AGC PEDEST 0 GNTIME OSTIME
0x03 0x43 0x83 0xC3 HDELAY_X HDELAY_X [7:0]
0x04 0x44 0x84 0xC4 HACTIVE_X HACTIVE_X [7:0]
0x05 0x45 0x85 0xC5 HDELAY_Y HDELAY_Y [7:0]
0x06 0x46 0x86 0xC6 HACTIVE_Y HACTIVE_Y [7:0]
0x07 0x47 0x87 0xC7 MSB_ACTV HACTIVE_Y [9:8] HDELAY_Y [9:8] HACTIVE_X [9:8] HDELAY_X [9:8]
0x08 0x48 0x88 0xC8 HSWIDTH 0 HSWIDTH
0x09 0x49 0x89 0xC9 VDELAY_X VDELAY_X [7:0]
0x0A 0x4A 0x8A 0xCA VACTIVE_X VACTIVE_X [7:0]
0x0B 0x4B 0x8B 0xCB VDELAY_Y VDELAY_Y [7:0]
0x0C 0x4C 0x8C 0xCC VACTIVE_Y VACTIVE_Y [7:0]
0x0D 0x4D 0x8D 0xCD HPLL HPLLMAN HPLLTIME VACTVE_Y [8] VDELAY_Y [8] VACTVE_X [8] VDELAY_X [8]
0x0E 0x4E 0x8E 0xCE SYNCPOL FLDMODE VSMODE FLDPOL HSPOL VSPOL 1 0
0x0F 0x4F 0x8F 0xCF HUE HUE
0x10 0x50 0x90 0xD0 SAT SAT
0x11 0x51 0x91 0xD1 CONT CONT
0x12 0x52 0x92 0xD2 BRT BRT
0x13 0x53 0x93 0xD3 CFILTER IFCOMP CLPF ACCMODE APCMODE
0x14 0x54 0x94 0xD4 PEAKCKIL YPEAK_Y YPEAK_X 0 CKILL
0x15 0x55 0x95 0xD5 SCLFLT VLPF_Y VLPF_X HLPF_Y HLPF_X
0x16 0x56 0x96 0xD6 TRAP_X YBWI_X COMBMD_X 0
0x17 0x57 0x97 0xD7 TRAP_Y YBWI_Y COMBMD_Y 0
0x18 0x58 0x98 0xD8 VSCLMSB_X VSCALE_X [15:8]
0x19 0x59 0x99 0xD9 VSCLLSB_X VSCALE_X [7:0]
0x1A 0x5A 0x9A 0xDA VSCLMSB_Y VSCALE_Y [15:8]
0x1B 0x5B 0x9B 0xDB VSCLLSB_Y VSCALE_Y [7:0]
0x1C 0x5C 0x9C 0xDC HSCLMSB_X HSCALE_X [15:8]
0x1D 0x5D 0x9D 0xDD HSCLLSB_X HSCALE_X [7:0]
0x1E 0x5E 0x9E 0xDE HSCLMSB_Y HSCALE_Y [15:8]
0x1F 0x5F 0x9F 0xDF HSCLLSB_Y HSCALE_Y [7:0]
0x20 0x60 0xA0 0xE0 VSCLCON_X 0 VFLT_MD_X VBW_X PALDLY_X ODD_EN_X EVEN_EN_X 1
0x21 0x61 0xA1 0xE1 VSCLCON_Y 0 VFLT_MD_Y VBW_Y PALDLY_Y ODD_EN_Y EVEN_EN_Y 1
0x22 0x62 0xA2 0xE2 OUTFMT BGND_EN BGND_COLR NOVID_656 LIM_16 SW_RESET ANA_SW OUT_FMT
0x23 0x63 0xA3 0xE3 RESERVED 1 0 0 1 0 0 0 1
0x24 0x64 0xA4 0xE4 SENSCTL LVLSENS TMPSENS SPTSENS
0x25 0x65 0xA5 0xE5 MPERIOD 0 MDPERIOD
0x26 0x66 0xA6 0xE6 MDMASK1 MDMASK1[7:0]
Techwell, Inc. 29 09/09/2003

Address
Mnemonic BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
CH1 CH2 CH3 CH4
0x27 0x67 0xA7 0xE7 MDMASK12 MDMASK2[11:8] MDMASK1[11:8]
0x2A 0x6A 0xAA 0xEA MDMASK34 MDMASK4[11:8] MDMASK3[11:8]
0x2B 0x6B 0xAB 0xEB MDMASK4 MDMASK4[7:0]
0x2C 0x6C 0xAC 0xEC MDMASK5 MDMASK5[7:0]
0x2D 0x6D 0xAD 0xED MDMASK56 MDMASK6[11:8] MDMASK5[11:8]
0x2E 0x6E 0xAE 0xEE MDMASK6 MDMASK6[7:0]
0x2F 0x6F 0xAF 0xEF MDMASK7 MDMASK7[7:0]
0x30 0x70 0xB0 0xF0 MDMASK78 MDMASK8[11:8] MDMASK7[11:8]
0x31 0x71 0xB1 0xF1 MDMASK8 MDMASK8[7:0]
0x32 0x72 0xB2 0xF2 MDMASK9 MDMASK9[7:0]
0x33 0x73 0xB3 0xF3 MDMASK9A MDMASK10[11:8] MDMASK9[11:8]
0x34 0x74 0xB4 0xF4 MDMASKA MDMASK10[7:0]
0x35 0x75 0xB5 0xF5 MDMASKB MDMASK11[7:0]
0x36 0x76 0xB6 0xF6 MDMASKBC MDMASK12[11:8] MDMASK11[11:8]
0x37 0x77 0xB7 0xF7 MDMASKC MDMASK12[7:0]
0x38 DET_NVMD * DET_NOVID4 DET_NOVID3 DET_NOVID2 DET_NOVID1 DET_MOTION4 DET_MOTION3 DET_MOTION2 DET_MOTION1
0x39 IRQCLR IRQCLR
0x3A IRQENA IRQENA
0x3B MISC OE NVMD ACTIVE_MODE 0 CK27_POL IRQPOL IRQRPT
0x3C U_GAIN U_GAIN
0x3D V_GAIN V_GAIN
0x3E U_OFF U_OFF
0x3F V_OFF V_OFF
0x78 ADC_PWDN 0 0 0 0 ADC_PWDN4 ADC_PWDN3 ADC_PWDN2 ADC_PWDN1
0x79 RESERVED 0 0 0 0 0 0 0 0
0x7A RESERVED 0 0 0 0 0 0 0 0
0x7B FLDOFST 0 0 0 0 0 0 0 0
0x7C RESERVED 0 0 0 0 0 0 0 0
0x7D RESERVED 0 0 0 0 0 0 0 0
0xB8 RESERVED 0 0 0 0 0 0 0 0
0xF8 CORE HAV_VALID 0 0 0 C_CORE Y_H_CORE
0xF9 COMBCDEL 0 CDEL 0 FLD_656 1 0
0xFA RESERVED 0 0 1 1 1 1 0 0
0xFB RESERVED 0 0 1 0 0 0 0 0
0xFC RESERVED 0 0 0 0 0 0 0 0
0xFD RESERVED 0 0 0 0 0 0 0 0
Notes: ① * : Read only register
② : Modified in TW2804 RevC
③ : Modified in TW2804 RevD
Techwell, Inc. 30 09/09/2003

Recommended Value
Address NTSC PAL

Mnemonic
CH1 CH2 CH3 CH4 FULL CIF QCIF FULL CIF QCIF
0x00 0x40 0x80 0xC0 VIDSTAT 8’h00 8’h00
0x01 0x41 0x81 0xC1 FORMAT C4 84
0x02 0x42 0x82 0xC2 AGC_PLL A5 A5
0x03 0x43 0x83 0xC3 HDELAY_X 20 20
0x04 0x44 0x84 0xC4 HACTIVE_X D0 D0
0x05 0x45 0x85 0xC5 HDELAY_Y 20 20
0x06 0x46 0x86 0xC6 HACTIVE_Y D0 D0
0x07 0x47 0x87 0xC7 MSB_ACTV 88 88
0x08 0x48 0x88 0xC8 HSWIDTH 20 20
0x09 0x49 0x89 0xC9 VDELAY_X 07 04
0x0A 0x4A 0x8A 0xCA VACTIVE_X F0 20
0x0B 0x4B 0x8B 0xCB VDELAY_Y 07 04
0x0C 0x4C 0x8C 0xCC VACTIVE_Y F0 20
0x0D 0x4D 0x8D 0xCD HPLL 40 4A
0x0E 0x4E 0x8E 0xCE SYNCPOL D2 D2
0x0F 0x4F 0x8F 0xCF HUE 80 80
0x10 0x50 0x90 0xD0 SAT 80 80
0x11 0x51 0x91 0xD1 CONT 80 80
0x12 0x52 0x92 0xD2 BRT 80 80
0x13 0x53 0x93 0xD3 CFILTER 1F 1F
0x14 0x54 0x94 0xD4 PEAKCKIL 00 00 30 00
0x15 0x55 0x95 0xD5 SCLFLT 00 21 33 00 22 33
0x16 0x56 0x96 0xD6 TRAP_X 00 40
0x17 0x57 0x97 0xD7 TRAP_Y 00 40
0x18 0x58 0x98 0xD8 VSCLMSB_X FF 7F 3F FF 7F 3F
0x19 0x59 0x99 0xD9 VSCLLSB_X FF FF
0x1A 0x5A 0x9A 0xDA VSCLMSB_Y FF FF
0x1B 0x5B 0x9B 0xDB VSCLLSB_Y FF FF
0x1C 0x5C 0x9C 0xDC HSCLMSB_X FF 7F 3F FF 7F 3F
0x1D 0x5D 0x9D 0xDD HSCLLSB_X FF FF
0x1E 0x5E 0x9E 0xDE HSCLMSB_Y FF FF
0x1F 0x5F 0x9F 0xDF HSCLLSB_Y FF FF
0x20 0x60 0xA0 0xE0 VSCLCON_X 07 07 67 0F 07 67
0x21 0x61 0xA1 0xE1 VSCLCON_Y 07 0F
0x22 0x62 0xA2 0xE2 OUTFMT 00 00
0x23 0x63 0xA3 0xE3 RESERVED 91 91
0x24 0x64 0xA4 0xE4 SENSCTL 51 51
0x25 0x65 0xA5 0xE5 MPERIOD 03 03
0x26 0x66 0xA6 0xE6 MDMSKL1 00 00
0x27 0x67 0xA7 0xE7 MDMSKM12 00 00
0x28 0x68 0xA8 0xE8 MDMSKL2 00 00
0x29 0x69 0xA9 0xE9 MDMSKL3 00 00
0x2A 0x6A 0xAA 0xEA MDMSKM34 00 00
0x2B 0x6B 0xAB 0xEB MDMSKL4 00 00
0x2C 0x6C 0xAC 0xEC MDMSKL5 00 00
0x2D 0x6D 0xAD 0xED MDMSKM56 00 00
0x2E 0x6E 0xAE 0xEE MDMSKL6 00 00
0x2F 0x6F 0xAF 0xEF MDMSKL7 00 00
0x30 0x70 0xB0 0xF0 MDMSKM78 00 00
0x31 0x71 0xB1 0xF1 MDMSKL8 00 00
Techwell, Inc. 31 09/09/2003

Address NTSC PAL
Mnemonic
CH1 CH2 CH3 CH4 FULL CIF QCIF FULL CIF QCIF
0x32 0x72 0xB2 0xF2 MDMSKL9 00 00
0x33 0x73 0xB3 0xF3 MDMSKM9A 00 00
0x34 0x74 0xB4 0xF4 MDMSKLA 00 00
0x35 0x75 0xB5 0xF5 MDMSKLB 00 00
0x36 0x76 0xB6 0xF6 MDMSKMBC 00 00
0x37 0x77 0xB7 0xF7 MDMSKLC 00 00
0x38 DET_NVMD 00 00
0x39 IRQCLR 00 00
0x3A IRQENA FF FF
0x3B MISC 84 84
0x3C U_GAIN 80 80
0x3D V_GAIN 80 80
0x3E U_OFF 82 82
0x3F V_OFF 82 82
0x78 ADC_PWDN 00 00
0x79 RESERVED 00 00
0x7A RESERVED 00 00
0x7B FLDOFST 00 00
0x7C RESERVED 00 00
0x7D RESERVED 00 00
0xB8 RESERVED 00 00
0xF8 CORE 0A 0A
0xF9 COMBCDEL 42 42
0xFA RESERVED 3C 3C
0xFB RESERVED 10 10
0xFC RESERVED 00 00
0xFD RESERVED 00 00
Note : ① Blanks : Indicate the same value as full size
② : Modified in TW2804 RevC
③ : Modified in TW2804 RevD
Techwell, Inc. 32 09/09/2003

Register Description
Video Status Flag (Read only)

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x00
2 0x40
DET_FORMAT DET_COLORLOCK_COLOR LOCK_GAIN LOCK_OFST LOCK_PLL
3 0x80
4 0xC0
DET_FORMAT Status of video standard detection

0 PAL-B/D
1 PAL-M
2 PAL-N
3 PAL-60
4 NTSC-M
5 NTSC-4.43
6 NTSC-N
DET_COLOR Status of color detection

0 Color is not detected
1 Color is detected
LOCK_COLOR Status of locking for color demodulation loop

0 Color demodulation loop is not locked
1 Color demodulation loop is locked
LOCK_GAIN Status of locking for AGC loop

0 AGC loop is not locked
1 AGC loop is locked
LOCK_OFST Status of locking for clamping loop

0 Claming loop is not locked
1 Claming loop is locked
LOCK_PLL Status of locking for horizontal PLL

0 Horizontal PLL is not locked
1 Horizontal PLL is locked
Techwell, Inc. 33 09/09/2003

Input Video Format

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x01
2 0x41 DET_ DET_
IFMTMAN IFORMAT 0 1
3 0x81 NONSTD * FLD60 *
4 0xC1
Notes: * Read only register
IFMTMAN Setting video standard manually with IFORMAT

0 Detect video standard automatically according to incoming video
signal (default)
1 Video standard is selected with IFORMAT
IFORMAT Force the device to operate in a particular video standard when IFMTMAN
is high or to free-run in a particular video standard on no-video status when
IFMTMAN is low
0 PAL-B/D (default)
1 PAL-M
2 PAL-N
3 PAL-60
4 NTSC-M
5 NTSC-4.43
6 NTSC-N
DET_NONSTD Status of non-standard video detection (Read only)

0 The incoming video source is standard
1 The incoming video source is non-standard
DET_FLD60 Status of field frequency of incoming video (Read only)

0 50Hz field frequency
1 60Hz field frequency
Techwell, Inc. 34 09/09/2003

Gain and Offset Tracking

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x02
2 0x42
AGC PEDEST 1 0 GNTIME OSTIME
3 0x82
4 0xC2
AGC Enable the AGC

0 Disable the AGC (default)
1 Enable the AGC
PEDEST Select the 7.5 IRE setup level, pedestal to black

0 No pedestal (default)
1 7.5 IRE setup level
GNTIME Control the time constant of gain tracking loop

0 Slower
1 Slow (default)
2 Fast
3 Faster
OSTIME Control the time constant of offset tracking loop

0 Slower
1 Slow (default)
2 Fast
3 Faster
Techwell, Inc. 35 09/09/2003

Horizontal Delay Control for Path X

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x07 HDELAY[9:8]
1
0x03 HDELAY[7:0]
0x47 HDELAY[9:8]
2
0x43 HDELAY[7:0]
0x87 HDELAY[9:8]
3
0x83 HDELAY[7:0]
0xC7 HDELAY[9:8]
4
0xC3 HDELAY[7:0]
Horizontal Delay Control for Path Y

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x07 HDELAY[9:8]
1
0x05 HDELAY[7:0]
0x47 HDELAY[9:8]
2
0x45 HDELAY[7:0]
0x87 HDELAY[9:8]
3
0x85 HDELAY[7:0]
0xC7 HDELAY[9:8]
4
0xC5 HDELAY[7:0]
HDELAY This 10-bit register defines the starting location of horizontal active pixel. A
unit is 1 pixel. HDELAY1 and HDELAY2 define the different starting
location of horizontal active pixel for dual scaler output. The default value is
decimal 32.
Techwell, Inc. 36 09/09/2003

Horizontal Active Control for Path X

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x07 HACITIVE[9:8]
1
0x04 HACTIVE[7:0]
0x47 HACITIVE[9:8]
2
0x44 HACTIVE[7:0]
0x87 HACITIVE[9:8]
3
0x84 HACTIVE[7:0]
0xC7 HACITIVE[9:8]
4
0xC4 HACTIVE[7:0]
Horizontal Active Control for Path Y

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x07 HACTIVE[9:8]
1
0x06 HACTIVE[7:0]
0x47 HACTIVE[9:8]
2
0x46 HACTIVE[7:0]
0x87 HACTIVE[9:8]
3
0x86 HACTIVE[7:0]
0xC7 HACTIVE[9:8]
4
0xC6 HACTIVE[7:0]
HACTIVE This 10-bit register defines the number of horizontal active pixel. A unit is 1
pixel. HACTIVE1 and HACTIVE2 define the different number of horizontal
active pixels for dual scaler output. The default value is decimal 720.
Horizontal Sync Pulse Width Control

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x08
2 0x48
0 0 HSWIDTH
3 0x88
4 0xC8
HSWIDTH This 6bit register defines the width of horizontal sync output. A unit is 1
pixel. The default value is decimal 32
Techwell, Inc. 37 09/09/2003

Vertical Delay Control for Path X

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x0D VDELAY[8]
1
0x09 VDELAY[7:0]
0x4D VDELAY[8]
2
0x49 VDELAY[7:0]
0x8D VDELAY[8]
3
0x89 VDELAY[7:0]
0xCD VDELAY[8]
4
0xC9 VDELAY[7:0]
Vertical Delay Control for Path Y

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x0D VDELAY[8]
1
0x0B VDELAY[7:0]
0x4D VDELAY[8]
2
0x4B VDELAY[7:0]
0x8D VDELAY[8]
3
0x8B VDELAY[7:0]
0xCD VDELAY[8]
4
0xCB VDELAY[7:0]
VDELAY This 9bit register defines the starting location of vertical active. A unit is 1
line. VDELAY1 and VDELAY2 define the different starting location of
vertical active line for dual scaler output. The default value is decimal 6.
Techwell, Inc. 38 09/09/2003

Vertical Active Control for Path X

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x0D VACTIVE[8]
1
0x0A VACTIVE[7:0]
0x4D VACTIVE[8]
2
0x4A VACTIVE[7:0]
0x8D VACTIVE[8]
3
0x8A VACTIVE[7:0]
0xCD VACTIVE[8]
4
0xCA VACTIVE[7:0]
Vertical Active Control for Path Y

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x0D VACTIVE[8]
1
0x0C VACTIVE[7:0]
0x4D VACTIVE[8]
2
0x4C VACTIVE[7:0]
0x8D VACTIVE[8]
3
0x8C VACTIVE[7:0]
0xCD VACTIVE[8]
4
0xCC VACTIVE[7:0]
VACTIVE This 9bit register defines the number of vertical active lines. A unit is 1 line.
VACTIVE1 and VACTIVE2 define the different number of vertical active
lines for dual scaler output. The default value is decimal 240.
Techwell, Inc. 39 09/09/2003

Horizontal PLL Control

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x0D
2 0x4D
HPLLMAN HPLLTIME
3 0x8D
4 0xCD
HPLLMAN Set horizontal PLL time constant with HPLLTIME.

0 Automatic horizontal tracking mode (default)
1 Horizontal PLL time constant is fixed with HPLLTIME
HPLLTIME Control the time constant of horizontal PLL when HPLLMAN is high
0 Slow
: :
4 Typical (default)
: :
7 Fast
Techwell, Inc. 40 09/09/2003

Sync Pulse Polarity Control

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x0E
2 0x4E
FLDMODE VSMODE FLDPOL HSPOL VSPOL 1 0
3 0x8E
4 0xCE
FLDMODE Select the field flag generation mode

0 Field flag is detected from incoming video (default)
1 Field flag is generated from small accumulator of detected field
2 Field flag is generated from medium accumulator of detected field
3 Field flag is generated from large accumulator of detected field
VSMODE Control the VS and field flag timing

0 VS and field flag is aligned with vertical sync of incoming video
(default)
1 VS and field flag is aligned with HS
FLDPOL Select the FLD polarity

0 Odd field is high (default)
1 Even field is high
HSPOL Select the HS polarity

0 Low for sync duration (default)
1 High for sync duration
VSPOL Select the VS polarity

0 Low for sync duration (default)
1 High for sync duration
Techwell, Inc. 41 09/09/2003

Hue Control
CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x0F
2 0x4F
HUE
3 0x8F
4 0xCF
HUE Control the hue information. The resolution is 1.4° / LSB.

0 -180°
: :
128 0° (default)
: :
255 180°
Saturation Control
CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x10
2 0x50
SAT
3 0x90
4 0xD0
SAT Control the color saturation. The resolution is 0.8% / LSB.

0 0%
: :
128 100 % (default)
: :
255 200 %
Techwell, Inc. 42 09/09/2003

Contrast Control
CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x11
2 0x51
CONT
3 0x91
4 0xD1
CONT Control the contrast. The resolution is 0.8% / LSB.

0 0%
: :
128 100 % (default)
: :
255 200 %
Brightness Control
CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x12
2 0x52
BRT
3 0x92
4 0xD2
BRT Control the brightness. The resolution is 0.2IRE / LSB.

0 -25 IRE
: :
128 0 (default)
: :
255 25 IRE
Techwell, Inc. 43 09/09/2003

Color Filter Control

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x13
2 0x53
IFCOMP CLPF ACCMODE APCMODE
3 0x93
4 0xD3
IFCOMP Select the IF-compensation filter mode

0 No compensation (default)
1 +1 dB/ MHz
2 +2 dB/ MHz
3 +3 dB/ MHz
CLPF Select the Color LPF mode

0 550KHz bandwidth
1 750KHz bandwidth (default)
2 950KHz bandwidth
3 1.1MHz bandwidth
ACCMODE Control the time constant of auto color control loop

0 Slower
1 Slow
2 Fast
3 Faster (default)
APCMODE Control the time constant of auto phase control loop

0 Slower
1 Slow
2 Fast
3 Faster (default)
Techwell, Inc. 44 09/09/2003

Peaking and Color Killer Control

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x14
2 0x54
YPEAK_Y YPEAK_X 0 0 CKIL
3 0x94
4 0xD4
YPEAK_Y Control the luminance peaking for SCALER Y path

0 No peaking (default)
1 31.25%
2 62.5%
3 93.75%
YPEAK_X Control the luminance peaking for SCALER X path

0 No peaking (default)
1 31.25%
2 62.5%
3 93.75%
CKIL Control the color killing mode

0,1 Auto detection mode (default)
2 Color is always alive
3 Color is always killed
Techwell, Inc. 45 09/09/2003

Scaler Filter Control

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x15
2 0x55
VLPF_Y VLPF_X SCLFLT_Y SCLFLT_X
3 0x95
4 0xD5
VLPF_Y Select the vertical anti-aliasing filter mode for VSCALER Y

0,1 Full bandwidth (default)
2 0.25 Line-rate bandwidth
VLPF_X Select the vertical anti-aliasing filter mode for VSCALER X

0,1 Full bandwidth (default)
SCLFLT_Y Select the horizontal anti-aliasing filter mode for HSCALER Y

0 Full bandwidth (default)
1 2 MHz bandwidth
2 1.5 MHz bandwidth
3 1 MHz bandwidth
SCLFLT_X Select the horizontal anti-aliasing filter mode for HSCALER X

0 Full bandwidth (default)
1 2 MHz bandwidth
2 1.5 MHz bandwidth
3 1 MHz bandwidth
Techwell, Inc. 46 09/09/2003

Trap Filter Control for Path X

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x16
2 0x56
YBWI COMBMD 0 0 0 0 0
3 0x96
4 0xD6
Trap Filter Control for Path Y

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x17
2 0x57
YBWI COMBMD 0 0 0 0 0
3 0x97
4 0xD7
YBWI Select the luminance trap filter mode

0 Narrow bandwidth trap filter mode (default)
1 Wide bandwidth trap filter mode
COMBMD Select the adaptive comb filter mode

0,1 Adaptive comb filter mode (default)
2 Force trap filter mode
3 Not supported
Techwell, Inc. 47 09/09/2003

Vertical Scaler Ratio Control for Path X

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x18 VSCALE[15:8]
1
0x19 VSCALE[7:0]
0x58 VSCALE[15:8]
2
0x59 VSCALE[7:0]
0x98 VSCALE[15:8]
3
0x99 VSCALE[7:0]
0xD8 VSCALE[15:8]
4
0xD9 VSCALE[7:0]
Vertical Scaler Ratio Control for Path Y

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x1A VSCALE[15:8]
1
0x1B VSCALE[7:0]
0x5A VSCALE[15:8]
2
0x5B VSCALE[7:0]
0x9A VSCALE[15:8]
3
0x9B VSCALE[7:0]
0xDA VSCALE[15:8]
4
0xDB VSCALE[7:0]
VSCALE The 16bit register defines a vertical scaling ratio. The actual vertical scaling
ratio is VSCALE[15:0] / (2^16 – 1). VSCALE1 and VSCALE2 define the
different vertical scaling ratio for dual scaler. The default value is 16 bit
0xFFFF.
Techwell, Inc. 48 09/09/2003

Horizontal Scaler Ratio Control for Path X

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x1C HSCALE[15:8]
1
0x1D HSCALE[7:0]
0x5C HSCALE[15:8]
2
0x5D HSCALE[7:0]
0x9C HSCALE[15:8]
3
0x9D HSCALE[7:0]
0xDC HSCALE[15:8]
4
0xDD HSCALE[7:0]
Horizontal Scaler Ratio Control for Path Y

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x1E HSCALE[15:8]
1
0x1F HSCALE[7:0]
0x5E HSCALE[15:8]
2
0x5F HSCALE[7:0]
0x9E HSCALE[15:8]
3
0x9F HSCALE[7:0]
0xDE HSCALE[15:8]
4
0xDF HSCALE[7:0]
HSCALE The 16-bit register defines a horizontal scaling ratio. The actual horizontal
scaling ratio is HSCALE[15:0] / (2^16 – 1). HSCALE1 and HSCALE2 define
the different horizontal scaling ratio for dual scaler. The default value is 16
bit 0xFFFF.
Techwell, Inc. 49 09/09/2003

Vertical Scaler Control for Path X

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x20
2 0x60
0 VFLT_MD VBW PALDLY ODD_EN EVEN_EN 1
3 0xA0
4 0xE0
Vertical Scaler Control for Path X

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x21
2 0x61
0 VFLT_MD VBW PALDLY ODD_EN EVEN_EN 1
3 0xA1
4 0xE1
VFLT_MD Select the vertical scaling filter mode

0 Vertical poly-phase filter mode is selected (default)
1 Vertical bandwidth control mode is selected with VBW bits
VBW Control the vertical bandwidth only if VFLT_MD bit is high

0 Wider (default)
1 Wide
2 Narrow
3 Narrower
PAL_DLY Select the PAL delay line mode

0 Normal vertical scaling operation in chroma path (default)
1 PAL delay line mode is selected in chroma path
ODD_EN Control valid signal in ODD field

0 Valid signal is always disabled in ODD field
1 Normal operation (default)
EVEN_EN Control valid signal in EVEN field

0 Valid signal is always disabled in EVEN field
Techwell, Inc. 50 09/09/2003

Output Formatter
CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x22
2 0x62 SW_
BGNDEN BGNDCLR NOVID_656 LIM_16 ANA_SW OUT_FMT
3 0xA2 RESET
4 0xE2
BGNDEN Control the background color on/off

0 Background color is disabled (default)
1 Background color is enabled
BGNDCLR Select the background color mode only if BGNDEN bit is high
0 Blue color mode (default)
1 Black color mode
NOVID_656 Select the optional set of 656 SAV/EAV code sequence for no-video status
0 Normal 656 SAV/EAV code sequence (default)
1 An optional set of 656 SAV/EAV code sequence for no-video status
LIM_16 Control the output range

0 Output ranges are limited to 2 ~ 254 (default)
1 Output ranges are limited to 16 ~ 239
SW_RESET Reset the system by software except control registers.

This bit is self-clearing in a few clocks after enabled
1 Enable soft reset
ANA_SW Control the analog input channel switch

0 VIN_A channel is selected (default)
1 VIN_B channel is selected
OUT_FMT Select the output format

0 ITU-R BT.656 format (default)
1 8bit ITU-R BT.601 format
2 Dual ITU-R BT.656 with 54MHz format
3 Not supported
Techwell, Inc. 51 09/09/2003

Reserved
CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x23
2 0x63
1 0 0 1 0 0 0 1
3 0xA3
4 0xE3
This control register is reserved for putting the part into test mode. For normal operation, the
above value should be set in this register.
Techwell, Inc. 52 09/09/2003

Motion Detection Sensitivity

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x24
2 0x64
LVLSENS TMPSENS SPTSENS
3 0xA4
4 0xE4
LVLSENS Control the level sensitivity of motion detector (default : 3)

0 More sensitive
: :
15 Less sensitive
TMPSENS Control the temporal sensitivity of motion detector (default : 1)

0 More sensitive
: :
3 Less sensitive
SPTSENS Control the spatial sensitivity of motion detector (default : 1)

0 More sensitive
: :
3 Less sensitive
Motion Detection Control

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
1 0x25
2 0x65
0 MDPERIOD
3 0xA5
4 0xE5
MDPERIOD Control the velocity of motion detector (default : 3)

0 No field interval
1 1 field interval
: :
31 31 field interval
Techwell, Inc. 53 09/09/2003

Masking Motion Detection Area MASK1

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x27 MDMASK1[11:8]
1
0x26 MDMASK1[7:0]
0x67 MDMASK1[11:8]
2
0x66 MDMASK1[7:0]
0xA7 MDMASK1[11:8]
3
0xA6 MDMASK1[7:0]
0xE7 MDMASK1[11:8]
4
0xE6 MDMASK1[7:0]

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x27 MDMASK2[11:8]
1
0x28 MDMASK2[7:0]
0x67 MDMASK2[11:8]
2
0x68 MDMASK2[7:0]
0xA7 MDMASK2[11:8]
3
0xA8 MDMASK2[7:0]
0xE7 MDMASK2[11:8]
4
0xE8 MDMASK2[7:0]

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x2A MDMASK3[11:8]
1
0x29 MDMASK3[7:0]
0x6A MDMASK3[11:8]
2
0x69 MDMASK3[7:0]
0xAA MDMASK3[11:8]
3
0xA9 MDMASK3[7:0]
0xEA MDMASK3[11:8]
4
0xE9 MDMASK3[7:0]
Techwell, Inc. 54 09/09/2003


CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x2A MDMASK4[11:8]
1
0x2B MDMASK4[7:0]
0x6A MDMASK4[11:8]
2
0x6B MDMASK4[7:0]
0xAA MDMASK4[11:8]
3
0xAB MDMASK4[7:0]
0xEA MDMASK4[11:8]
4
0xEB MDMASK4[7:0]

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x2D MDMASK5[11:8]
1
0x2C MDMASK5[7:0]
0x6D MDMASK5[11:8]
2
0x6C MDMASK5[7:0]
0xAD MDMASK5[11:8]
3
0xAC MDMASK5[7:0]
0xED MDMASK5[11:8]
4
0xEC MDMASK5[7:0]

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x2D MDMASK6[11:8]
1
0x2E MDMASK6[7:0]
0x6D MDMASK6[11:8]
2
0x6E MDMASK6[7:0]
0xAD MDMASK6[11:8]
3
0xAE MDMASK6[7:0]
0xED MDMASK6[11:8]
4
0xEE MDMASK6[7:0]
Techwell, Inc. 55 09/09/2003


CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x30 MDMASK7[11:8]
1
0x2F MDMASK7[7:0]
0x70 MDMASK7[11:8]
2
0x6F MDMASK7[7:0]
0xB0 MDMASK7[11:8]
3
0xAF MDMASK7[7:0]
0xF0 MDMASK7[11:8]
4
0xEF MDMASK7[7:0]

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x30 MDMASK8[11:8]
1
0x31 MDMASK8[7:0]
0x70 MDMASK8[11:8]
2
0x71 MDMASK8[7:0]
0xB0 MDMASK8[11:8]
3
0xB1 MDMASK8[7:0]
0xF0 MDMASK8[11:8]
4
0xF1 MDMASK8[7:0]

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x33 MDMASK9[11:8]
1
0x32 MDMASK9[7:0]
0x73 MDMASK9[11:8]
2
0x72 MDMASK9[7:0]
0xB3 MDMASK9[11:8]
3
0xB2 MDMASK9[7:0]
0xF3 MDMASK9[11:8]
4
0xF2 MDMASK9[7:0]
Techwell, Inc. 56 09/09/2003


CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x33 MDMASK10[11:8]
1
0x34 MDMASK10[7:0]
0x73 MDMASK10[11:8]
2
0x74 MDMASK10[7:0]
0xB3 MDMASK10[11:8]
3
0xB4 MDMASK10[7:0]
0xF3 MDMASK10[11:8]
4
0xF4 MDMASK10[7:0]

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x36 MDMASK11[11:8]
1
0x35 MDMASK11[7:0]
0x76 MDMASK11[11:8]
2
0x75 MDMASK11[7:0]
0xB6 MDMASK11[11:8]
3
0xB5 MDMASK11[7:0]
0xF6 MDMASK11[11:8]
4
0xF5 MDMASK11[7:0]

CH Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x36 MDMASK12[11:8]
1
0x37 MDMASK12[7:0]
0x76 MDMASK12[11:8]
2
0x77 MDMASK12[7:0]
0xB6 MDMASK12[11:8]
3
0xB7 MDMASK12[7:0]
0xF6 MDMASK12[11:8]
4
0xF7 MDMASK12[7:0]
MDMASK1~12 Select mask area of motion detector. An active region is divided into 12x12
mask areas as illustrated in Fig. 11. If the mask bit in specific area is
programmed into high, the specific area is ignored in operation of motion
detector. But for proper operation, more than 4 mask areas should be
enabled in any case. (default : 0x00)
Techwell, Inc. 57 09/09/2003

No video and Motion Detection Flag (Read only)

Index
[7] [6] [5] [4] [3] [2] [1] [0]
DET_ DET_ DET_ DET_ DET_ DET_ DET_ DET_
0x38
NOVID4 NOVID3 NOVID2 NOVID1 MOTION4 MOTION3 MOTION2 MOTION1
DET_NOVID4 Status for detection of video loss in Channel 4

0 Video is alive
1 Video loss is detected

0 Video is alive

0 Video is alive

0 Video is alive
DET_MOTION4 Status for detection of motion in Channel 4

0 No motion
1 Motion is detected
DET_MOTION3 Status for detection of Motion in Channel 3

0 No motion

0 No motion

0 No motion
Techwell, Inc. 58 09/09/2003

Clear Interrupt Flag

Index
[7] [6] [5] [4] [3] [2] [1] [0]
CLEAR_ CLEAR_ CLEAR_ CLEAR_ CLEAR_ CLEAR_ CLEAR_ CLEAR_
0x39
IRQCLR Setting high to bits clears interrupt requests of corresponding bits. This bit
is self-clearing in a few clocks after setting high (default : 0x00)
Enable Interrupt Flag

Index
[7] [6] [5] [4] [3] [2] [1] [0]
EN_ EN _ EN_ EN _ EN _ EN_ EN_ EN_
0x3A
IRQENA Enable the corresponding (0x38, 0x39) interrupt register bit (default : 0x00)
Techwell, Inc. 59 09/09/2003

Miscellaneous Control Register

Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x3B OE NVMD ACTIVE_MODE[1:0] 0 CK27_POL IRQPOL IRQRPT
OE Control the tri-state of output pin

0 Outputs are Tri-state (default)
1 Outputs are enabled
NVMD Select the output mode of NVMD pin

0 Video loss flag (default)
1 Motion detection flag
ACTIVE_MODE Select the output mode of ACTIVE pin

0 HACTIVE (default)
1 VACTIVE
2 Horizontal valid pixel indicator
3 Vertical valid line indicator
CK27_POL Select the CLK27O polarity

0 ITU-R BT.656 data outputs at the rising edge of CLK27O (default)
1 ITU-R BT.656 data outputs at the falling edge of CLK27O
IRQPOL Select the IRQ polarity

0 Active high (default)
1 Active low
IRQRPT Select the IRQ mode

0 IRQ maintains the state until the interrupt request is cleared (default)
1 IRQ toggles the state at regular intervals until the interrupt request is
cleared
Techwell, Inc. 60 09/09/2003

U Gain
Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x3C U_GAIN[7:0]
U_GAIN Adjust gain for U (or Cb) component. The resolution is 0.8% / LSB.
0 0%
: :
128 100 % (default)
: :
255 200 %
V Gain
Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x3D V_GAIN[7:0]
V_GAIN Adjust gain for V (or Cr) component. The resolution is 0.8% / LSB.
0 0%
: :
128 100 % (default)
: :
255 200 %
Techwell, Inc. 61 09/09/2003

U Offset
Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x3E U_OFF[7:0]
U_OFF U (or Cb) offset adjustment register. The resolution is 0.4% / LSB.
0 -50 %
: :
128 0 % (default)
: :
255 50 %
V Offset
Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x3F V_OFF[7:0]
V_OFF V (or Cr) offset adjustment register. The resolution is 0.4% / LSB.
0 -50 %
: :
128 0 % (default)
: :
255 50 %
Techwell, Inc. 62 09/09/2003

ADC Power Down

Index
[7] [6] [5] [4] [3] [2] [1] [0]
ADC_ ADC_ ADC_ ADC_
0x78 0 0 0 0
PWDN4 PWDN3 PWDN2 PWDN1
ADC_PWDN4 Power down the ADC of channel 4

0 Normal (default)
1 Power down

0 Normal (default)
1 Power down

0 Normal (default)
1 Power down

0 Normal (default)
1 Power down
Techwell, Inc. 63 09/09/2003

Reserved
Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x79 0 0 0 0 0 0 0 0
Reserved
Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x7A 0 0 0 0 0 0 0 0
Techwell, Inc. 64 09/09/2003

Field Offset Control

Index
[7] [6] [5] [4] [3] [2] [1] [0]
FLD_OFST FLD_OFST FLD_OFST FLD_OFST FLD_OFST FLD_OFST FLD_OFST FLD_OFST
0x7B
_4Y _4X _3Y _3X _2Y _2X _1Y _1X
FLD_OFST_4Y Remove the field offset between ODD and EVEN for Y path of Channel 4
1 Remove the field offset between ODD and EVEN field
FLD_OFST_4X Remove the field offset between ODD and EVEN for X path of Channel 4
Techwell, Inc. 65 09/09/2003

Reserved
Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x7C 0 0 0 0 0 0 0 0
Reserved
Index
[7] [6] [5] [4] [3] [2] [1] [0]
0x7D 0 0 0 0 0 0 0 0
Reserved
Index
[7] [6] [5] [4] [3] [2] [1] [0]
0xB8 0 0 0 0 0 0 0 0
Techwell, Inc. 66 09/09/2003

Luma and Chroma Coring

Index
[7] [6] [5] [4] [3] [2] [1] [0]
0xF8 HAV_VALID 0 0 0 C_CORE[1:0] Y_H_CORE[1:0]
HAV_VALID Select VALID output mode

0 Valid data indicator only for active data (default)
1 Valid data indicator for both active data and ITU-R 656 timing codes
C_CORE Coring to reduce the noise in the chrominance

0 No coring
1 Coring value is within 128 +/- 1 range
2 Coring value is within 128 +/- 2 range (default)
3 Coring value is within 128 +/- 4 range
Y_H_CORE Coring to reduce the high frequency noise in the luminance

0 No coring
1 Coring value is within +/- 1 range
2 Coring value is within +/- 2 range (default)
3 Coring value is within +/- 4 range
Techwell, Inc. 67 09/09/2003

Chroma Delay and Comb Filter Correlation Reference

Index
[7] [6] [5] [4] [3] [2] [1] [0]
0xF9 0 CDEL[2:0] 0 FLD_656 1 0
CDEL Adjust the group delay of chrominance path relative to luminance

0 -2.0 pixel
1 -1.5 pixel
2 -1.0 pixel
3 -0.5 pixel
4 0.0 pixel (default)
5 0.5 pixel
6 1.0 pixel
7 1.5 pixel
FLD_656 Control the field polarity mode in ITU-R 656 timing codes
0 Fixed field polarity according to ITU-R 656 format (default)
1 Controllable field polarity by FLDPOL register (0x0E,0x4E,0x8E,0xCE)
Techwell, Inc. 68 09/09/2003

Reserved
Index
[7] [6] [5] [4] [3] [2] [1] [0]
0xFA 0 0 1 1 1 1 0 0
Reserved
Index
[7] [6] [5] [4] [3] [2] [1] [0]
0xFB 0 0 0 1 0 0 0 0
Techwell, Inc. 69 09/09/2003

Reserved
Index
[7] [6] [5] [4] [3] [2] [1] [0]
0xFC 0 0 0 0 0 0 0 0
Reserved
Index
[7] [6] [5] [4] [3] [2] [1] [0]
0xFD 0 0 0 0 0 0 0 0
Techwell, Inc. 70 09/09/2003

Parametric Information
DC Electrical Parameters
Table 7 Absolute Maximum Ratings

VDDA (measured to VSSA) VDDAM 3.5 V
VDD (measured to VSS) VDDIM 3.5 V
VDDO (measured to VSS) VDDOM 4.6 V
Voltage on any signal pin
- VSS–0.5 VDDO+0.5 V
(See the note below)
Analog Input Voltage - VSSA–0.5 VDDA+0.5 V
Storage Temperature TS – 65 150 °C
Junction Temperature TJ 0 125 °C
Vapor Phase Soldering (15 Seconds) TVSOL 220 °C
NOTE: Long-term exposure to absolute maximum ratings may affect device reliability, and
permanent damage may occur if operate exceeding the rating. The device should be
operated under recommended operating condition.
Table 8 Recommended Operating Conditions

VDDA (measured to VSSA) VDDA 2.25 2.5 2.75 V
VDD (measured to VSS) VDDI 2.25 2.5 2.75 V
VDDO (measured to VSS) VDDO 3.0 3.3 3.6 V
Maximum |VDDI – VDDA| 0.3 V
Maximum |VDDO – VDDA| 1.05 V
Maximum |VDDO – VDDI| 1.05 V
Analog VIN Amplitude Range
0.5 1.0 2.0 V
(AC coupling required)
Ambient Operating Temperature TA 0 70 °C
Techwell, Inc. 71 09/09/2003

Table 9 DC Characteristics
Digital Inputs
Input High Voltage (TTL) VIH 2.0 V
Input Low Voltage (TTL) VIL 0.8 V
Input Leakage Current
IL ±1 uA
(@VI=2.5V or 0V)
Input Capacitance CIN 6 pF
Digital Outputs
Output High Voltage VOH 2.4 V
Output Low Voltage VOL 0.4 V
High Level Output Current
IOH 5.7 11.6 18.6 mA
(@VOH=2.4V)
Low Level Output Current
IOL 4.1 6.7 8.2 mA
(@VOL=0.4V)
Tri-state Output Leakage Current
IOZ ±1 uA
(@VO=2.5V or 0V)
Output Capacitance CO 6 pF
Analog Pin Input Capacitance CA 6 pF
Table 10 Supply Current and Power Dissipation

Analog Supply Current (2.5V) IDDA 50 mA
Digital Internal Supply Current (2.5V) IDDI 400 mA
Digital I/O Supply Current (3.3V) IDDO 10 mA
Total Power Dissipation P 1.16 W
Techwell, Inc. 72 09/09/2003

AC Electrical Parameters
Table 11 Clock Timing Parameters
Delay from CLK54I to CLK27O 1 5 12 ns
Hold from CLK27O to Data 2a 16 ns
Delay from CLK27O to Data 2b 19 ns
Hold from CLK54I to Data 3a 5 ns
Delay from CLK54I to Data 3b 12 ns
CLK54I
1
CLK27O
2b
2a
Data Output
(27Mhz)
3b
3a
Data Output
(54Mhz)
Fig 21 Clock Timing Diagram
Techwell, Inc. 73 09/09/2003

Table 12.Decoder Performance Parameter
Horizontal PLL
Line frequency (60Hz) fH 15.734 KHz
Line frequency (50Hz) fH 15.625 KHz
Permissible static deviation ∆fH ±6 %
Subcarrier PLL
Subcarrier frequency (NTSC-M) fSC 3.579545 MHz
Subcarrier frequency (PAL-BDGHI) fSC 4.433619 MHz
Subcarrier frequency (PAL-M) fSC 3.575612 MHz
Subcarrier frequency (PAL-N) fSC 3.582056 MHz
Lock in range ∆fSC ±800 Hz
AGC (Auto Gain Control)
Range AGC -6 18 dB
ACC (Auto Color Gain Control)
Range ACC -6 30 dB
Oscillator Input
Nominal frequency fOSC 54 MHz
Permissible frequency deviation ∆fOSC/fOSC ±50 ppm
Duty cycle dtOSC 55 %
Techwell, Inc. 74 09/09/2003

Package Dimension
Techwell, Inc. 75 09/09/2003

Techwell, Inc. 76 09/09/2003

Application Information
Video Input Interface

TW2804 has a built-in 2:1 input MUX for software controllable input selections. This MUX can
be used to select two composite video sources. For a typical application, a video input
requires an analog low-pass filter for alias reduction. An illustration is shown in the following
application schematic.
Clamping / AGC
TW2804 has built-in clamping and AGC circuitry. The analog inputs must be AC coupled
through an external 2.2uF capacitor. Without it, no extra external component is needed for
this operation. The clamping and AGC tracking time constant can be controlled through
register setting.
Video Output Interface

All video data and sync outputs of four channels are synchronous to pin CLK27O. Therefore,
pin CLK27O should be connected to four channel interfaces for synchronizing data.
Power-Up
After power-up, TW2804 registers have unknown values. The RSTB pin must be asserted
and released to bring all registers to its default values. After reset, TW2804 data outputs are
tri-stated. The OE (0x3B) register should be written after reset to enable outputs desired.
Techwell, Inc. 77 09/09/2003

Application Schematic
VDD VDDO VDDA
J100
RCA JACK R101 L100 C102
CH1A 1
9
21
33
48
60
72
90
102
6
24
45
66
84
105
111
112
119
120
127
10uH U100
270 2.2uF
2
R100 C100 C101 R102
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDA
VDDA
VDDA
VDDA
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDAD
75 47pF 100pF 4.7k
VD1[7:0]
VD1_7 VD1[7:0]
13
VD1_7 14 VD1_6
VD1_6 16 VD1_5
VD1_5 17 VD1_4
113 VD1_4 19 VD1_3
VIN1A VD1_3 20 VD1_2
VD1_2 22 VD1_1
114 VD1_1 23 VD1_0
J101 VIN1B VD1_0
RCA JACK R104 L101 C105 11
CH2A VALID1 VALID1
1 8
HS1 HS1
10uH C112 7
VS1 VS1
270 2.2uF 5
FLD1 FLD1
2
R103 C103 C104 R105 0.1uF 10
ACTIVE1 ACTIVE1
75 47pF 100pF 4.7k
VD2[7:0]
VD2_7 VD2[7:0]
34
VD2_7 35 VD2_6
VD2_6 37 VD2_5
117 VD2_5 38 VD2_4
VD2_3 41 VD2_2
118 VD2_2 43 VD2_1
VIN2B VD2_1 44 VD2_0
J102 VD2_0
RCA JACK R107 L102 C108 32
CH3A VALID2 VALID2
1 C113 29
HS2 HS2
10uH 28
VS2 VS2
270 2.2uF 0.1uF 26
FLD2 FLD2
2
R106 C106 C107 R108 31
ACTIVE2 ACTIVE2
75 47pF 100pF 4.7k TW2804 VD3[7:0]
VD3_7 VD3[7:0]
55
VD3_7 56 VD3_6
121 128QFP VD3_6 58 VD3_5
VD3_4 61 VD3_3
122 VD3_3 62 VD3_2
VD3_1 65 VD3_0
J103 VD3_0
RCA JACK R110 L103 C111 C114 53
CH4A VALID3 VALID3
1 50
HS3 HS3
10uH 0.1uF 49
VS3 VS3
270 2.2uF 47
FLD3 FLD3
2
R109 C109 C110 R111 52
ACTIVE3 ACTIVE3
75 47pF 100pF 4.7k
VD4[7:0]
VD4_7 VD4[7:0]
76
125 VD4_7 77 VD4_6
VD4_5 80 VD4_4
126 VD4_4 82 VD4_3
VD4_2 85 VD4_1
C115 VD4_1 86 VD4_0
VD4_0 74
VALID4 VALID4
0.1uF 71
HS4 HS4
70
VS4 VS4
68
FLD4 FLD4
73
ACTIVE4 ACTIVE4
VDD2.5V VDD
L104
88
CLK27O CLK27
BEAD + C116 C117 C118 C119 C120 C121 C122 C123 C124
RESETB
47uF/16V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 103
IRQ IRQ
4
NVMD1 NVMD1
25
NVMD2 NVMD2
46
NVMD3 NVMD3
VDDA 2 67
L105 RSTB NVMD4 HDAT[7:0] NVMD4
OSC100 HDAT0 HDAT[7:0]
VDDO 101
HDAT_0 100 HDAT1 VDDO
1 8 HDAT_1 98 HDAT2
BEAD + C125 NC VCC HDAT_2 HDAT3
C126 C127 C128 C129 C130 97
DIP8 HDAT_3 95 HDAT4
47uF/16V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF HDAT_4 94 HDAT5 R113
R112
4 5 89 HDTV_5 92 HDAT6 47K
GND OUT CLK54I HDAT_6 91 HDAT7
To Micom
1 HDAT_7 104
100 HWRB
TEST HWRB 106
OSC 54MHz HRDB HRDB
VDD3.3V VDDO 107
L106 HALE HALE
109
HCSB HCSB
110
HSPB HSPB
BEAD + C131 C132 C133 C134 C135 C136 C137

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA
47uF/16V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

3
12
15
18
27
30
36
39
42
51
54
57
63
69
75
78
81
87
93
96
99
108
128
115 VSSAD
116 VSSA
123 VSSA
124 VSSA
Place near each device Analog GND Digital GND

power pin(0.1uF Cap.)
Note : Analog GND and Digital GND Plane

should be isolated
Techwell, Inc. 78 09/09/2003

Revision History
Table 13 Datasheet Revision History

Product
Revision Date Description
Code
E BAHB
0.9 Oct / 01 / 2002 Engineering Release
(Eng RevB)
(1) Update Application Schematic (P.77) E BAHB

1.0 Dec / 11 / 2002
(2) Update Recommended Value of Control Register Map (P.31~32) (Eng RevB)
(1) Update Control Register Map (Read only description is added) E BAHB
1.1 Jan / 29 / 2003
(P.29~30, P.33~34, P.58) (Eng RevB)
(1) Update Application Schematic (P.77) E BAHB

1.2 Feb / 04 / 2003
(2) Update Recommended Value of Control Register Map (P.31~32) (Eng RevB)
(1) Update Control Register Map (Default value is added)

E BAHB
1.3 Feb / 17 / 2003 (P.34, P.40, P.45, P.47, P.60)
(Eng RevB)
(2) Update Fig.14 (P.25)
(1) Change Pin Diagram (P.5~7) E BAHC

2.0 Feb / 19 / 2003
(2) Update Application Schematic (P.76) (Eng RevC)
(1) Update Fig 4 and Fig 9 (P.12, P.16)

(2) Update Table 4 (P.23)
E BAHC
2.1 Apr / 25 / 2003 (3) Update Control Register Map & Recommended Value
(Eng RevC)
(P.29~32, P.35, P.40, P.45~47, P.50~51, P.60, P.63~70)
(4) Fix FLDPOL and NVMD mode (P.41, P.60)
E BAHC
2.2 Jul / 21 / 2003 (1) Update Fig 19 (P.27)
(Eng RevC)
(1) Change digital power(Pin 111) and ground pin(Pin 128) to analog
power and ground pin (P.5 ~ 7)
E BAHD
2.3 Aug / 16 / 2003 (2) Change Recommended Value of Control Register 0xFB (P.69)
(Eng RevD)
(2) Update parallel interface timing diagram (P.27)
(3) Update Application Schematic (P.77)
(1) Update Supply Current and Power Dissipation information (P.72)

E BAHD
2.4 Sep / 09 / 2003 (2) Update Application Information (P.76)
(Eng RevD)
(1) Update Fig 12 and Fig 15 (P.23, P.25)

(2) Update Control Register Map (P.65) E BAHE
2.5 Nov / 11 / 2003
(3) Update Decoder Performance Parameter (P.74) (Eng RevE)
Techwell, Inc. 79 09/09/2003

Table 14. List of Revision Point in TW2804 RevC

No. Issue TW2804 RevB TW2804 RevC
Cross-talk between adjacent input Remove cross-talk by modifying analog
1 Cross-talk
channels circuit and changing analog pin location
100% amplitude,
2 100% saturation Clipping the yellow and cyan pattern Fixed by adjusting data range
Color bar pattern
3 Contrast range Biased toward upper range Fixed by adjusting contrast range
Background color
4 Not supported Supported with Blue and Black pattern
pattern
Vertical scaling Rejected perfectly by improving vertical
5 A little aliasing noise is remained
filter scaling filter
6 IRQ polarity Only active high is supported Both active high and low are supported
Optional ITU –R Optional No-video and non-valid code
7 Not supported
656 code set set are supported
8 Peaking filter Common mode in Scaling X & Y path Separate mode in Scaling X & Y path
Table 15 List of Revision Point in TW2804 RevD

No. Issue TW2804 RevC TW2804 RevD
1 ADC Linearity Not good in ADC linearity Improve ADC linearity
Table 16 List of Revision Point in TW2804 RevE

No. Issue TW2804 RevD TW2804 RevE
1 ADC Linearity Improve ADC linearity Improve ADC linearity more
Supports the field offset control for

Field Offset
2 Not supported speeding up the field rate in analog
Control
switching mode
Techwell, Inc. 80 09/09/2003


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TW2802/4 Multiple Video Decoder

Preliminary Data Sheet from Techwell, Inc.

Techwell, Inc. 09/09/2003

Luminance Processing ______________12 Video Input Interface ______________ 77

Chrominance Processing ____________13 Clamping / AGC __________________ 77

Motion Detector ___________________20

Techwell, Inc. 09/09/2003

Introduction and Features

automatic clamp and gain control VIN2A Color Decoder

− Proprietary architecture for locking to Motion Detector H/V Sync Processor

weak, noisy, or unstable signals NVMD2

− High performance adaptive comb filters VIN3A Color Decoder

− IF compensation filter for improvement

− PAL delay lines for correcting PAL VIN4A

down scaler for each channel IRQ CLK54I

Techwell, Inc. 3 09/09/2003

Techwell, Inc. 4 09/09/2003

Analog Interface Pins

Techwell, Inc. 5 09/09/2003

Techwell, Inc. 6 09/09/2003

Techwell, Inc. 7 09/09/2003

Video Input Formats

Table 1 Input Video Format Supported

Techwell, Inc. 8 09/09/2003

Video Level Adjustment

Horizontal Sync Processing

Vertical Sync Processing

Techwell, Inc. 9 09/09/2003

Fig 1 The Characteristic of the Decimation Filter

Techwell, Inc. 10 09/09/2003

Fig. 2 The Characteristics of Luminance Notch Filter for NTSC

Fig 3 The Characteristics of Luminance Notch Filter for PAL

Techwell, Inc. 11 09/09/2003

Fig. 4. The Characteristic of Luminance Peaking filter

Techwell, Inc. 12 09/09/2003

Fig. 5 The Characteristics of IF-compensation Filter

Techwell, Inc. 13 09/09/2003

Magnitude Response (dB)

Fig. 6 The Characteristics of Chrominance Low Pass Filter

ACC (Automatic Color gain control)

Chrominance Gain, Offset and Hue Adjustment

Techwell, Inc. 14 09/09/2003

Video Scaling and Cropping

Fig 7 The Characteristics of Anti-aliasing filter for horizontal luminance scaling

Techwell, Inc. 15 09/09/2003

Magnitude Response (dB) 0.1

Fig 8 The Characteristics of Group delay for horizontal luminance scaling

Fig. 9 The Characteristics of Anti-aliasing filter for vertical luminance scaling

Techwell, Inc. 16 09/09/2003

The scaling ratios of popular case are listed in Table 2

Techwell, Inc. 17 09/09/2003

HDELAY + HACTIVE < Total number of pixels per line

VDELAY + VACTIVE < Total number of lines per field

Techwell, Inc. 18 09/09/2003

Cropping and Scaling

Fig 10 The Effect of Cropping and Scaling Active Registers

Techwell, Inc. 19 09/09/2003

LVLSENS (Level Sensitivity)

Luminance Processing 12 Video Input Interface 77

Chrominance Processing 13 Clamping / AGC ______ 77