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    CS698Y: Modern Memory Systems Lecture-15 (DRAM Organization)

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    Benyamin Farzaneh Aghajarie
    The document discusses the organization of DRAM memory. It describes how DRAM is organized into channels, ranks, banks, rows, columns, and chips. A rank contains multiple DRAM chips and supports a certain interface width, such as x8 or x4. Each bank within a rank contains a row buffer to store the most recently accessed row/page of data. Reading from DRAM involves activating a row in a bank to load the row buffer and then accessing the desired column(s).

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    CS698Y: Modern Memory Systems Lecture-15 (DRAM Organization)

    Uploaded by

    Benyamin Farzaneh Aghajarie
    13 views18 pages
    The document discusses the organization of DRAM memory. It describes how DRAM is organized into channels, ranks, banks, rows, columns, and chips. A rank contains multiple DRAM chips and supports a certain interface width, such as x8 or x4. Each bank within a rank contains a row buffer to store the most recently accessed row/page of data. Reading from DRAM involves activating a row in a bank to load the row buffer and then accessing the desired column(s).

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    The document discusses the organization of DRAM memory. It describes how DRAM is organized into channels, ranks, banks, rows, columns, and chips. A rank contains multiple DRAM chips and supports a certain interface width, such as x8 or x4. Each bank within a rank contains a row buffer to store the most recently accessed row/page of data. Reading from DRAM involves activating a row in a bank to load the row buffer and then accessing the desired column(s).

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    13 views18 pages

    CS698Y: Modern Memory Systems Lecture-15 (DRAM Organization)

    Uploaded by

    Benyamin Farzaneh Aghajarie
    The document discusses the organization of DRAM memory. It describes how DRAM is organized into channels, ranks, banks, rows, columns, and chips. A rank contains multiple DRAM chips and supports a certain interface width, such as x8 or x4. Each bank within a rank contains a row buffer to store the most recently accessed row/page of data. Reading from DRAM involves activating a row in a bank to load the row buffer and then accessing the desired column(s).

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    CS698Y: Modern Memory Systems

    Lecture-15 (DRAM Organization)


    Biswabandan Panda
    [email protected]

    https://www.cse.iitk.ac.in/users/biswap/CS698Y.html
    DRAM Organization
    Channel
    Rank 1 with 8 chips
    DIMM

    Rank
    Rank 0 with 8 chips
    Chip

    Bank

    Row
    Column
    Modern Memory Systems Biswabandan Panda, CSE@IITK 2
    Ranks, Banks, Rows, and Columns
    Rank 0 Rank 1

    Bank 0 Bank 1

    DIMM

    Bank 2 Bank 3

    Multiple Chips

    Modern Memory Systems Biswabandan Panda, CSE@IITK 3


    Ranks, Banks, Rows, and Columns
    Rank 0
    Chip

    Bank 0 Bank 1
    16
    64 bits 16 Bank
    16

    Bank 2 Bank 3
    16 Row

    Column

    16-bit interface: 16 bits from each chip in one go


    Modern Memory Systems Biswabandan Panda, CSE@IITK 4
    Let’s Dig Deep

    Each rank has 64-bit wide data bus

    If a rank is of width x8 then # DRAM chips ??

    What about x4, # DRAM chips ??

    If a rank is of width x8 then # DRAM chips ?? 8

    What about x4, # DRAM chips ?? 16

    Modern Memory Systems Biswabandan Panda, CSE@IITK 5


    Where is Your 1 bit?
    Wordline

    Row or Page

    Bitline

    Modern Memory Systems Biswabandan Panda, CSE@IITK 6


    Row (page) and Row buffer (Sense Amplifier)
    Logically
    2KB
    Each bank has a row buffer
    R Stores the last used row
    o
    w
    D
    e
    c
    o
    d
    e Actually
    r
    Multiple local row buffers
    Row Buffer Multiple Sub-arrays
    Column mux
    Modern Memory Systems Biswabandan Panda, CSE@IITK 7
    SALP [ISCA ‘12]

    Logical Bank Physical Bank


    Row Local Row-
    Row
    Subarray64
    Buf
    32k rows Row
    Row Subarray
    Local Row-Buf1
    Row-Buffer Global Row-Buf
    A single row-buffer Many local row-buffers,
    cannot drive all rows one at each subarray
    For the sake of simplicity, we will use the logical view
    Modern Memory Systems Biswabandan Panda, CSE@IITK 8
    Bank: Collection of DRAM Arrays

    • DRAM Width
    RRR
    • x4 device RRR oo
    RR oooww
    o
    • x8 device oo wwwDD
    w
    wwDDDee
    • Other possible D
    DDeeecc
    e
    widths ee cccoo
    c
    cc ooodd
    o
    • x16 oo dddee
    d
    dd eeerr
    e
    • x32 ee rrr
    r
    rr
    • x48 RowBuffer
    Row
    Row
    Buffer
    Buffer
    RowBuffer
    Row Buffer
    Row Column
    Buffermux
    • x72 Row
    Row Column
    Buffermux
    Column
    Buffer
    Columnmux
    Column
    mux
    mux
    Column
    Columnmux mux
    mux
    Column

    Modern Memory Systems Biswabandan Panda, CSE@IITK 9


    An Example – 4GB DIMM

    2Gb * 8 DRAM Chips (one side of the rank)

    Total 16 chips + 2 chips for ECC (for both the ranks)

    64 bit + 8 bit ECC interface (72 bit wide DIMM)

    Transferring a 64B cache line will take 8 transfers of 8B each

    8B will come from 8 chips (8 bits from one chip)

    1 bit from each DRAM array assuming 8 DRAM arrays per bank

    Modern Memory Systems Biswabandan Panda, CSE@IITK 10


    Another View

    Modern Memory Systems Biswabandan Panda, CSE@IITK 11


    DRAM Channels

    2 channels: 1 channel per controller


    Modern Memory Systems Biswabandan Panda, CSE@IITK 12
    DRAM to LLC

    Physical memory
    space Chip 0 Chip 1 Chip 7
    Rank 0
    0xFFFF…F

    ...
    ...

    <56:63>
    <8:15>
    <0:7>
    0x40

    64B
    Data <0:63>
    cache block

    0x00

    Modern Memory Systems Biswabandan Panda, CSE@IITK 13


    DRAM to LLC

    Physical memory
    space Chip 0 Chip 1 Chip 7
    0xFFFF…F
    Rank 0

    Row 0 ...
    Col 0
    ...

    <56:63>
    <8:15>
    <0:7>
    0x40

    64B
    Data <0:63>
    cache block

    0x00

    Modern Memory Systems Biswabandan Panda, CSE@IITK 14


    DRAM to LLC

    Physical memory
    space Chip 0 Chip 1 Chip 7
    0xFFFF…F
    Rank 0

    Row 0 ...
    Col 0
    ...

    <56:63>
    <8:15>
    <0:7>
    0x40

    64B
    Data <0:63>
    cache block
    8B
    0x00 8B

    Modern Memory Systems Biswabandan Panda, CSE@IITK 15


    DRAM to LLC

    Physical memory
    space Chip 0 Chip 1 Chip 7
    0xFFFF…F
    Rank 0

    Row 0 ...
    Col 1
    ...

    <56:63>
    <8:15>
    <0:7>
    0x40

    64B
    8B Data <0:63>
    cache block
    8B
    0x00

    8 cycles (DRAM IO): 1 cycle transfers 8 bytes from a column


    Modern Memory Systems Biswabandan Panda, CSE@IITK 16
    DRAM Address Mapping (1 Channel)
    2GB DRAM, 8 Banks, 16K rows, 2K Columns per bank

    Cache Interleaving: Consecutive cache blocks in consecutive banks


    Row (14 bits) High Column Bank (3 bits) Low Col. Byte in bus (3 bits)

    8 bits 3 bits

    Row Interleaving: Consecutive rows in consecutive banks


    Row (14 bits) Bank (3 bits) Column (11 bits) Byte in bus (3 bits)

    What about Multiple Channels?

    Modern Memory Systems Biswabandan Panda, CSE@IITK 17


    ACK.

    Some of the slides are from


    Prof. Mutlu’s lectures
    T.V. Kalyan (IBM India)

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