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    Q036 Cpe 313: Introduction To HDL Activity Verilog Assignments

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    Jonjeffrey Agustin

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    Q036 Cpe 313: Introduction To HDL Activity Verilog Assignments

    Uploaded by

    Jonjeffrey Agustin
    11 views3 pages

    Original Title

    HDL PANGA

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    11 views3 pages

    Q036 Cpe 313: Introduction To HDL Activity Verilog Assignments

    Uploaded by

    Jonjeffrey Agustin

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 3

    URDANETA CITY UNIVERSITY

    COLLEGE OF ENGINEERING AND ARCHITECTURE


    SAN VICENTE WEST, URDANETA CITY 2428
    S.Y 2021-2022

    Q036 CPE 313: INTRODUCTION TO HDL


    ACTIVITY
    VERILOG ASSIGNMENTS

    SUBMITTED BY:
    AGUSTIN JON JEFFREY G.
    BSCPE-3

    SUBMITTED TO:
    ENGR. IRENE F. SALVADOR
    INSTRUCTOR
    1.)
    module Circuit_j1(F,G,H,A,B,C,D);
    output F,G,H;
    input A,B,C,D;

    assign F = (((~A)|(~C))|A|((~A)&C))&(((~B)&(~D))|(B&D));
    assign G = (~A)|(((~B)&(~D))|(B&D));
    assign H = (((~A)|(~C))|A|((~A)&C))^(((~B)&(~D))|(B&D));
    endmodule

    2.)
    module Circuit_j2(V,X,Y,D0,D1,D2,D3);
    output V,X,Y;
    input D0,D1,D2,D3;

    assign V = D3 | (D1&(~D2));
    assign X = D3 | D2;
    assign Y = X | D1 | D0;
    endmodule

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