Working With Adcs, Oas and The Msp430: Bonnie Baker Hpa Senior Applications Engineer Texas Instruments

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Working with ADCs, OAs

and the MSP430


Bonnie Baker
HPA Senior Applications Engineer
Texas Instruments
© 2006 Texas Instruments Inc, Slide 1
Agenda
• An Overview of the MSP430 Data Acquisition System
• SAR Converters
ƒ The INS and OUTS of the SAR converter
ƒ Useful Applications

• Using Op Amps
ƒ Op Amp Configurations
ƒ Driving SAR Converters

© 2006 Texas Instruments Inc, Slide 2


Where to Find ADCs and Op Amps
Voltage Reference Source
OP
OP
AMP
AMP
MUX
MUX FILTER
FILTER A/D
A/D

REF
REF Anti-Alias Filter
Sensor Interface Band-pass Filter
Voltage Reference Source Programmable Gain Amp
Buffer Instrumentation Amp
A/D Converter Driver
μμ C
Gain
Difference Amplifier C
Instrumentation Amplifier
Filter Voltage Reference Source
Level Shift DDS Synthesis

POWER
POWER D/A
D/A
Actuator Driver AMP
AMP
Valve Line Driver
4-20mA Driver © 2006 Texas Instruments Inc, Slide 3
ADC Architectures
• There are many different ADC Architectures
ƒ Successive Approximation (SAR)
ƒ Sigma Delta (SD)
ƒ Slope or Dual Slope
ƒ Pipeline
ƒ Flash...as in quick, not memory

• All converters in the MSP430 chips are SAR and


Sigma Delta types
• SAR determines the digital word
ƒ By approximating the input signal
ƒ Using an iterative process

• How the Sigma Delta converter determines the digital


word
ƒ By oversampling
ƒ Applying Digital Filtering © 2006 Texas Instruments Inc, Slide 4
Op Amp Architectures
• The Different Types Op Amp Architectures
ƒ Single Supply
– Rail to Rail In
– Rail to Rail Out
– CMOS or Bipolar
ƒ Dual Supply

• All Op Amps (OAs) in the MSP430 chips are Single


Supply, CMOS
• Our CMOS Op amp
ƒ Easily Configured with the MSP430 Controller
– General Purpose, Buffer, Comparator, PGA, Differential Amp
ƒ Easily Programmed for
– Optimized Gain
– Bandwidth
– etc © 2006 Texas Instruments Inc, Slide 5
Agenda
• An Overview of the MSP430 Data Acquisition System
• SAR Converters
ƒ The INS and OUTS of the SAR converter
ƒ Useful Applications

• Using Op Amps
ƒ Op Amp Configurations
ƒ Driving SAR Converters

© 2006 Texas Instruments Inc, Slide 6


The SAR ADC
• Most Serial ADCs are SARs or Sigma Deltas
• The MSP439 SAR Converter
ƒ SAR ADC = Successive Approximation Register, Analog-to-Digital
Converter
ƒ ADC12 – 12-bit Analog-to-Digital Converter

• SARs are Best for General Purpose Apps


ƒ Very Prevalent for Signal Level Applications: Data Loggers, Temp
Sensors, Bridge Sensors, General Purpose
SAR
• In the Market SARs Analog to
ƒ Can be 8 to 18 bits of resolution Digital
ƒ Speed range: >10 ksps to < 5 Msps Converter

• Usually require a Low-pass Filter before Analog Input

© 2006 Texas Instruments Inc, Slide 7


System Integration Using an A/D

MSP430
Amp Filter
Input SAR
Analog to Micro-
Analog
Digital to Controller
Signal Digital
Converter
Source Engine
Converter

Filter
Output DAC or
PWM

© 2006 Texas Instruments Inc, Slide 8


SAR Converter – Block Diagram

VS

S1 Cap array is both the sample Shift Register


RIN cap and a DAC
(2 kΩ) + S
SC
16C 2C C C A
_ R

1/2 VREF

Control
Logic

VSS VREF
© 2006 Texas Instruments Inc, Slide 9
Successive Approximation Concept
FS

Bit = 0
3/4FS
Bit = 1 Bit = 0 Analog
Bit = 1
input
VIN
1/2FS
TEST TEST TEST TEST
MSB MSB -1 MSB -2 LSB

1/4FS

0
Time
DAC Output Digital Output Code = 1010
© 2006 Texas Instruments Inc, Slide 10
ADC Ideal Transfer Function
111

110

101
Digital
Output 100
Code
011
Ideal transfer
010 function

001

000
0 1/4 FS 1/2 FS 3/4 FS FS
Analog Input Voltage
© 2006 Texas Instruments Inc, Slide 11
ADC with Offset and Gain Error
111 • y = a + (1+b)x
Actual where
110 transfer y=digital out
function x=analog in
101 a=offset err
b=gain err
Digital
Output 100 • Every Ideal Code has
Offset Error added
Code
011 • Every ideal code is
Multiplied by Gain Error
Ideal transfer
010 function

001

000
0 1/4 FS 1/2 FS 3/4 FS FS
Analog Input Voltage
© 2006 Texas Instruments Inc, Slide 12
Offset/Gain Impact on Dynamic Range
4096

Gain Error
Offset Error

• ADC12 specifications
Offset
ƒ EO typ = ±2 LSB
Digital Code OUT

ƒ EO max = ±4 LSB

Gain
Worse case ƒ EG typ = ±1.1 LSB
Dynamic ƒ EG max = ±2 LSB
Range = 4082 bits
= 11.995 bits (= ±0.0488%)

ƒ 1 LSB = (VR+ - VR-)/ 212


Analog Voltage IN VREF ƒ Easy to calibrate

© 2006 Texas Instruments Inc, Slide 13


DNL and INL Errors
Actual
transfer
function
INL < 0
111

110

101
DNL < 0
Digital
Output 100
Code Ideal transfer
011 function

010

001

000
Analog Voltage In
© 2006 Texas Instruments Inc, Slide 14
INL/DNL/Noise Impact on Dynamic Range
• ADC12 specifications
4096

ƒ DNL error
ƒ ED max = ±1.7 LSB
ƒ INL error
ƒ EI max = ±1 LSB
ƒ 1 LSB = (VR+ - VR-)/ 212
Digital Code OUT

• INL, DNL and Noise


errors move across
INL, DNL
rms ADC Noise the entire range
• Impacts the Effective
Number of Bits
(ENOB)
• Not Easily calibrated
Analog Voltage IN VREF • Effects Accuracy

© 2006 Texas Instruments Inc, Slide 15


ADC Input Impedance
Analog VCC
Input DESD Mux Resistance

RI = 2kΩ Sample Cap


RS DESD Leakage
current CI = 40pF

VSS

• Input Internal Impedance is Relatively Low


• A High Impedance Source Increases Sample Cap Charging Time
• Rise Time of Voltage on CI ~ (RS + RI) * CI

© 2006 Texas Instruments Inc, Slide 16


Sample Cap Charging Time
1400 ns (min) Sample Start Conversion
Period Conversion Complete

SAMPCON
1 2 3 4 5 6 7 8 9 10 11 12 13
ADC12OSC/ADC12DIV

D D D D D D D D D D D D
ADC12MEMx 11 10 9 8 7 6 5 4 3 2 1 0

Desired Voltage on CI

VC
Rise Time of
(RS + RI) * CI Final Voltage on CI
© 2006 Texas Instruments Inc, Slide 17
Alternative High Resolution Devices
• ADC12
ƒ Resolution = 12 bits
ƒ Minimum LSB size = VREF / 2n = 1.5 V / 212 = 366 mV
ƒ # channels = 12 to 16 (depends on part number)

• ADS8341
ƒ Resolution = 16 bits
ƒ Minimum LSB size = VREF / 2n = 2.7 V / 216 = 41.2 mV
ƒ # channels = 4

• ADS1100
ƒ Resolution = 16 bits
ƒ Minimum LSB size = VREF / 2n = 2*2.7 V / 216 = 82.4 mV
ƒ # channels = 1

© 2006 Texas Instruments Inc, Slide 18


Agenda
• An Overview of the MSP430 Data Acquisition System
• SAR Converters
ƒ The INS and OUTS of the SAR converter
ƒ Useful Applications
• Using Op Amps
ƒ Op Amp Configurations
ƒ Driving SAR Converters

© 2006 Texas Instruments Inc, Slide 19


Operational Amplifiers
• Most Prevalent Building Block in Analog Circuits
• Very Flexible - Large Variety of Functions
• Circuits We Will Talk About
ƒ General Purpose Op amp
ƒ Unity Gain Buffer
ƒ Comparator
ƒ PGA (Programmable Gain Amplifier)
ƒ Differential Amplifier RIN RF
VOUT

VIN

© 2006 Texas Instruments Inc, Slide 20


Where to Find Op Amps
Voltage Reference Source
OP
OP
AMP
AMP
MUX
MUX FILTER
FILTER A/D
A/D

REF
REF Anti-Alias Filter
Sensor Interface Band-pass Filter
Voltage Reference Source Programmable Gain Amp
Buffer Instrumentation Amp
A/D Converter Driver
μμ C
Gain
Difference Amplifier C
Instrumentation Amplifier
Filter Voltage Reference Source
Level Shift DDS Synthesis

POWER
POWER D/A
D/A
Actuator Driver AMP
AMP
Valve Line Driver
4-20mA Driver © 2006 Texas Instruments Inc, Slide 21
Ideal Op Amp

POWER SUPPLY
• No min or max Voltage
• ISUPPLY = 0 Amps
• Power Supply Rejection = ∞

INPUT VDD
• Input Current (IB) = 0 VIN- OUTPUT
• Input Impedance (ZIN) = ∞ VOUT • VOUT = VSS to VDD
• Input Voltage (VIN) → no limits
• Zero Noise VIN+ • IOUT = ∞
• Zero DC error •Slew Rate = ∞
•ZOUT = 0 Ω
• Common-Mode Rejection = ∞ VSS

SIGNAL TRANSFER
• Open Loop Gain = ∞
• Bandwidth = 0 → ∞ $0.00
• Zero Harmonic Distortion
© 2006 Texas Instruments Inc, Slide 22
Open Loop vs Closed Loop Design
• OAFCx = 011 VREF
• Open Loop Configuration VOUT
ƒ In Comparator mode VIN

VOUT = High for VIN > VREF


• OAFCx = 000
Low for VIN < VREF
• Closed Loop Configuration
ƒ Always a Connection from Output to
Inverting Input RIN RF
ƒ Gain is Dependant on Resistors VOUT

VIN

VOUT = ( 1 + RF / RIN) ( VIN)


© 2006 Texas Instruments Inc, Slide 23
Comparator Mode – OAFCx = 011
Temperature Sensor
VA(t) RREF
Px.y
MSP430FG43x
RNTC||RPAR
RREF
NTC||RPAR
Px.x

VTH
VA OAxI0

Comparator

Timer
CINT
t=0 t = t1 t = t2
Time VTH = 0.25VCC
RNTC||RPAR RREF
--------------- = ----------
tNTC||RPAR tREF © 2006 Texas Instruments Inc, Slide 24
General Op amp Mode – OAFCx = 000

V OU T MSP430FG43x

− OA0O

+
V IN OAxI1

OAxI0
VIN− +

VOUT
VIN+ +

VREF © 2006 Texas Instruments Inc, Slide 25


General Op amp Mode – OAFCx = 000
Non-inverting Gain
MSP430FG43x
RF CAx
VREF = 0.5VCC

VREF RIN VOUT


− VOUT OA0O

VIN +
OA0I1

OA0I0
+
VIN
VOUT = VIN (1 + RF/RIN) – VREF*RF/RIN
© 2006 Texas Instruments Inc, Slide 26
General Op amp Mode – OAFCx = 000
Inverting Gain
RF MSP430FG43x
VOUT OA0O
RIN
− VOUT
VIN OA0I1
+ −
VIN
OA0I0
VREF = 0.5VCC +
CAx

VREF = 0.5VCC

VOUT = VREF (1 + RF/RIN) – VIN*RF/RIN

© 2006 Texas Instruments Inc, Slide 27


Data Acquisition System

Analog
Gain
and Analog Analog to Digital
Signal Low Pass Digital Filter
Conditioning Filter Conversion
Cell (LPF) (ADC)

Input Output
Signal Signal
Analog Digital

© 2006 Texas Instruments Inc, Slide 28

Figure 4.1
Noise Reduction with a Low Pass Filter
Noise Reduction or Anti-aliasing Filter

R23

C22

R21 R22
VIN -

C21 ADC12
OA
+

VREF
© 2006 Texas Instruments Inc, Slide 29
Anti-alias Filter :: Nyquist Theorem
Signal at the fALIASED = |fIN - NfS| Digital Representation
Input of the A/D Find N by making at the
Converter N=1 fALIASED < fs / 2 Output of the Converter

N=2

N=4
N=0

N=3

N=0
Analog Input

Sampled Output
Representation
(1) (1)
(2) (2)
(3) (3)
(4) (4)
(5) (5)

fS/2 3fS/2 5fS/2 7fS/2 0 fS/2 fS


0 fS 2fS 3fS 4fS

© 2006 Texas Instruments Inc, Slide 30


Filter Pro Software
• Filter synthesis tool for designing
ƒ Multi-section filter
ƒ Low-pass Filter
ƒ High-pass active filter

• Supports
ƒ 2nd to 10th order
ƒ Multiple-feedback (MFB) Filter Topology
ƒ Sallen-Key Filter Topology

• www.ti.com

© 2006 Texas Instruments Inc, Slide 31


Operational Amp Output Swing
• Rail-to-Rail Output Operation does not Exist
• How Close the Amplifier’s Output can Come to the
Power Supplies (or “rails”) and still be Linear
• MSP430FG43x =
(VSS + 200mV) {min} to (VCC- 200mV) {max}

VOUT = ( 1 + RF / RIN) VIN


RIN RF
VOUT
VIN

© 2006 Texas Instruments Inc, Slide 32


Operational Amp Output Swing

10
Offset Voltage, VOS (mV)

-10

-20

-30

-40 3.6 4
0 1 2 3
Output Voltage, VOUT (V)

© 2006 Texas Instruments Inc, Slide 33


Unity Gain Buffer Mode – OAFCx = 001
• Op Amp Internally
connected as a buffer
MSP430FG43x
• Non-inverting input
available on a Controller
pin
− • Op Amp Output
OA ADC12 connected directly to
+ ADC12
OAxI0

© 2006 Texas Instruments Inc, Slide 34


Op Amp Input Voltage Range
• RRIP ON =
(VSS - 0.1V) {min} to (VCC + 0.1) {max}
• Charge pump on input stage is turned on
• Great Feature, not all amps have this!
VIN−
VOUT
VIN+

• RRIP OFF =
(VSS - 0.1V) {min} to (VCC - 1.2) {max}
• (Appropriate for Gains > 2)

© 2006 Texas Instruments Inc, Slide 35


PGA Mode –
Non-inverting Mode OAFCx = 100
VOUT = G VIN
MSP430FG44x
RRIP off
DACs or external VIN OAxCTL1
+ 111100x1 G=16
Ax int/ext
110100x1 G=8
VOUT 101100x1 G=3.33
- 100100x1 G=4
011100x1 G=2.67
RBOTTOM 010100x1 G=2
001100x0 G=1.33
R R R R 2R 2R 4R 4R RTOP 000100x0 G=1

AVSS
RRIP on
PGA
Non-inverting
© 2006 Texas Instruments Inc, Slide 36
PGA Mode –
Inverting Mode OAFCx = 110
VOUT = G VIN + VREF(1 – G)

MSP430FG44x RRIP off


DACs
or external OAxCTL1
+ 111110x1 G=-15
VREF Ax int/ext
110110x1 G=-7
VOUT 101110x1 G=-4.33
- 100110x1 G=-3
011110x1 G=2.67
010110x1 G=-1.67
VIN 001110x1 G=-1
000110x0 G=-0.33
R R R R 2R 2R 4R 4R RTOP
RBOTTOM

RRIP on
PGA
Inverting
© 2006 Texas Instruments Inc, Slide 37
Bridge Network MSP430FG43x

R23 μController

VREF1 -
C22 Functions
R21 R22
RL1 RL2 R1 INA326 -
G = 2 (R2/R1) SAR – ADC
= 245
C21
OA
12 bits
+
RL2 RL1 +
LCL- R2 C1
816G

VREF2

© 2006 Texas Instruments Inc, Slide 38


Summary
• 12-bit SAR Converter – ADC12
ƒ 12-bit Resolution and Accuracy
ƒ Excellent Dynamic Range
ƒ For more Resolution – Discrete Options

• Operational Amplifier – OA
ƒ Standard Single Supply CMOS Op Amp
ƒ Rail-to-rail Input
ƒ Rail-to-rail Output
ƒ Six Configurations or Modes
ƒ For more Accuracy – Discrete Options
ƒ For more Complexity – Discrete Options

• MSP430 Analog Options – Very Useful!

SLAP123 © 2006 Texas Instruments Inc, Slide 39


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