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    Pa9 35522

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    Mostafa Abdelazim

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    Pa9 35522

    Uploaded by

    Mostafa Abdelazim
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    PA9_35522

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    8 views2 pages

    Pa9 35522

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    Mostafa Abdelazim

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    © All Rights Reserved
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    of 2

    German University in Cairo

    Media Engineering and Technology


    Assoc. Prof. Dr. Hassan Soubra

    Computer System Architecture, Spring Semester 2021


    Practice Assignment 9
    Discussion: 13/06/2021 - 19/06/2021

    Exercise 9-1
    Consider the following code segment in MIPS:
    lw $t1 , 0( $t0 )
    lw $t2 , 4( $t0 )
    add $t3 , $t1 , $ t 2
    sw $t3 , 12( $t0 )
    lw $t4 , 8( $t0 )
    add $t5 , $t1 , $ t 4
    sw $t5 , 16( $t0 )

    a) What is the equivalent C code segment for the above program assuming all variables are in memory
    and are addressable as offsets from $t0.
    b) What is the problem with the above MIPS code that causes pipeline stalls? Propose a solution that
    avoids any pipeline stalls.

    Exercise 9-2
    The 5 stages of the processor have the following latencies:

    Fetch Decode Execute Memory Write Back


    Configuration A 300ps 200ps 250ps 500ps 100ps
    Configuration B 200ps 100ps 100ps 190ps 140ps

    Assume that when pipelining, each pipeline stage costs 20ps extra for the registers between the pipeline
    stages.

    a) Calculate the following for a Non-Pipelined processor and a Pipelined processor


    1. What is the new cycle time?
    2. What is the new latency of an instruction?
    3. What is the new throughput?
    b) If you could split one of the pipeline stages into 2 equal halves, which one would you choose?
    1. What is the new cycle time?
    2. What is the new latency of an instruction?
    3. What is the new throughput?
    c) Assume the distribution of instructions that run on the processor is as follows:
    • ALU: 51%
    • BEQ: 24%

    1
    • LW: 12%
    • SW: 13%
    Assuming there are no stalls or hazards, what is the utilization of the data memory? What is the
    utilization of the register block’s write port?
    - Utilization in percentage of clock cycles used

    Exercise 9-3
    The critical path latencies for the 6 major blocks in a simple processor are given below:

    IMEM ADD MUX ALU REGS DMEM


    Configuration A 450ps 150ps 35ps 170ps 250ps 400ps
    Configuration B 550ps 200ps 150ps 230ps 270ps 1050ps

    a) What is the critical path for a MIPS SUB instruction? Justify your answer.
    b) If the number of registers is doubled, this increases Regs by 50ps. This results in 20% fewer in-
    structions due to fewer load/stores. What is the new critical path for a MIPS SUB instruction?
    Why?

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