CS6303 - CA - IQ - Nov - Dec 2017 PDF

Anna University Exams Nov / Dec 2017 – Regulation 2013
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CS6303 Computer Architecture
Unit I – V
1. What is an addressing mode? Explain various addressing modes in detail with example and neat diagram for
each
2. Discuss about the various techniques to represent instructions in a computer system
3. Explain in detail on operations and operands of computer hardware
4. State the CPU performance equation and discuss the factors that affect performance
5. Explain in detail about Power wall with equation
6. Multiply the following pair of signed numbers using booth’s bit pair recoding of the multiplier A=
+13(Multiplicand) and B= -6(Multiplier).
7. Explain Booth’s multiplication algorithm with necessary hardware implementation, flowchart and solve it
for (+310) X (-210).
8. Explain the refined version of multiplication algorithm with necessary hardware implementation, flowchart
and solve it for 410 X 310
9. Divide (13)10 by (4)10 using non-restoring division algorithm with step by step intermediate results and
explain.
10. Divide (12)10 by (3)10 using restoring division algorithm with step by step intermediate results and explain
11. Multiply 1.11010 X 1010 and 9.200 X 10-5 using binary Floating point multiplication algorithm.
12. What is Pipelining? Discuss about various pipeline stages and pipelined data path and control.
13. What is hazards? Briefly explain about various categories of hazards with examples (or) Explain the
different types pipeline hazards with suitable examples.
14. Explain the basic MIPS implementation with necessary multiplexers and control lines.
15. Explain Instruction level Parallel Processing or Instruction level parallelism. State the challenges of parallel
processing.
16. Discuss about SISD, MIMD, SIMD, SPMD and VECTOR systems.
17. Write detailed note on Hardware multithreading and Multicore Processors
18. Explain in detail about Flynn’s Classification.
19. What is virtual memory? Explain the steps involved in virtual memory address translation. And TLB with
necessary diagram.
20. Explain (a) Bus Arbitration techniques in DMA. (b) DMA controller (c) I/O processor.
21. Explain mapping functions in cache memory to determine how memory blocks are placed in cache
22. Elaborate on the various memory technologies and its relevance
Part C
1. Assume a two address format specified as source, destination. Examine the following sequence of
instructions and identify the addressing modes used and the operation done in every instruction.
1. Move (R5)+,R0
2. Add (R5)+,R0
3. Move R0,(R5)
4. Move 16(R5),R3
5. Add #40,R5
2. A Program runs in 10 seconds on computer A, which has a 2 GHz clock. We are trying to help a computer
designer to build a computer B, which will run this program in 6 seconds. The designer has determined that a
substantial increase in the clock rate is possible, but this increase will affect the rest of the CPU design,
causing computer B to require 1.2 times as many clock cycles as computer A for this program. What clock
rate should we tell the designer to target?
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Consider the computer with three instruction classes and CPI measurements as given below and Instruction
counts for each instruction class for the same program from two different compilers are given. Assume that the
computer’s clock
rate is 4GHz. Which code sequence will execute most instruction and faster according to execution time?
What is the CPI for each sequence?
Code from CPI for each Instruction Class
A B C
1 2 3
Code from Instruction Counts for each instruction class
A B C
Compiler 1 2 1 2
Compiler 2 4 1 1
4. Assume a program requires the execution of 50 × 106 FP instructions,110 × 106 INT instructions, 80 ×
106 L/S instructions, and 16 × 106 branch instructions. The CPI for each type of instruction is 1, 1, 4,
and 2, respectively. Assume that the processor has a 2 GHz clock rate
a. By how much must we improve the CPI of FP instructions ifwe want the program to run two times faster?
b. By how much must we improve the CPI of L/S instructions if we want the program to run two times faster?
c. By how much is the execution time of the program improved if the CPI of INT and FP instructions is
reduced by 40% and the CPI of L/S and Branch is reduced by 30%?
5. Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz clock
rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of
2.2.
a. Which processor has the highest performance expressed in instructions per second?
b. If the processors each execute a program in 10 seconds, find the number of cycles and the number of
instructions.
c. We are trying to reduce the execution time by 30% but this leads to an increase of 20% in the CPI.
6. Add the numbers 0.510 and -0.437510using binary Floating point Addition algorithm
7. Multiply 1.10 10X 1010and 9.200X10-5 using binary Floating point multiplication
8. Show the IEEE 754 binary representation of the number -0.75 10in single and double precision
9. A byte addressable computer has a small data cache capable of holding eight 32-bit words. Each cache block
contains 132-bit word. When a given program is executed, the processor reads data from the following
sequence of hex addresses - 200, 204, 208, 20C, 2F4, 2F0, 200, 204,218, 21C, 24C, 2F4. The pattern is repeated
four times. Assuming that the cache is initially empty, show the contents of the cache at the end of each
pass, and compute the hit rate for a direct mapped cache
10. Registers R1 and R2 of a computer contains the decimal values 1200 and 2400 respectively. What is the
effective address of the memory operand in each of the following instructions?
i. Load 20(R1), R5

ii. Add –(R2) , R5
iii. Move #3000, R5
iv. Sub (R1)+, R5
11. Design a 4-bit Carry-Look ahead Adder and explain its operation with an example.
12. Design a binary multiplier using sequential adder. Explain its operation.
13. Design a 4-bit binary adder/ subtractor and explain its functions.
14. Perform the division on the following 5-bit unsigned integer using non-restoring division: 10101 / 00101.
15. Multiply the following pair of signed 2’s complements numbers using bit-pair-recoding of the multipliers: A=
010111, B=101100.
16. Explain the function of a six segment pipelines and draw a space diagram for a six segment pipeline showing
the time it takes to process eight tasks.
17. Explain how data may be transferred from a hard disk to memory using DMA including arbitration for
the bus,. Assume a synchronous bus, and draw a timing diagram showing the data transfer.
18. Explain the use of vectored interrupts in processors. Why is priority handling desired in interrupt controllers?
How do the different priority schemes work?
19. Study problem on Page Replacement Algorithm
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Anna University Exams Nov / Dec 2017 – Regulation 2013

Rejinpaul.com Unique Important Questions – 3rd Semester BE/BTECH

Download Our Official Android App – REJINPAUL NETWORK from

Code from CPI for each Instruction Class

Code from Instruction Counts for each instruction class

Download Our Official Android App – REJINPAUL NETWORK from

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