MetalOxide RRAM

INVITED
PAPER
Metal–Oxide RRAM
The authors discuss metal–insulator–metal structures that can be adopted to
integrate 3-D nonvolatile memory chips and neuromorphic computing.
By H.-S. Philip Wong, Fellow IEEE , Heng-Yuan Lee, Shimeng Yu, Student Member IEEE ,
Yu-Sheng Chen, Yi Wu, Pang-Shiu Chen, Byoungil Lee, Frederick T. Chen, and
Ming-Jinn Tsai
ABSTRACT | In this paper, recent progress of binary metal– I. INTRODUCTION

oxide resistive switching random access memory (RRAM) is
The observation that oxides that are nominally insulators
reviewed. The physical mechanism, material properties, and
can undergo an abrupt switching event to transition into a
electrical characteristics of a variety of binary metal–oxide
conductive state has been known for over 40 years. The
RRAM are discussed, with a focus on the use of RRAM for non- first reports of such resistive switching phenomena date
volatile memory application. A review of recent development back to the 1960s [1]–[4]. The device structure is simply an
of large-scale RRAM arrays is given. Issues such as uniformity, oxide material sandwiched between two metal electrodes,
endurance, retention, multibit operation, and scaling trends called the metal–insulator–metal (MIM) structure. The
are discussed. early observations of resistance switching were not robust
enough for memory applications and those reports remain
KEYWORDS | Emerging memory; metal oxide; multibit memory;
in the domain of scientific studies. The recent revival of
nonvolatile memory; OxRAM; ReRAM; resistance change mem-
interest in resistive switching began in the late 1990s, first
ory; resistive switching memory; resistive switching random with complex metal oxides such as the pervoskite oxides of
access memory (RRAM); solid-state memory SrTiO3 [5], SrZrO3 [6] and later the binary metal oxides
such as NiO [7] and TiO2 [8]. Various acronyms such as
OxRAM, ReRAM, and RRAM, have been used in the
literature for these devices that exhibit resistive switching
between a high-resistance state (HRS) and a low-resistance
Manuscript received November 12, 2010; revised March 17, 2011; accepted February 7,
2012. Date of publication May 2, 2012; date of current version May 10, 2012. This work state (LRS). Research activity began to intensify after 2004
was supported in part by the Stanford Non-Volatile Memory Technology Research when Samsung presented a paper [9] at the International
Initiative (NMTRI), the National Science Foundation (NSF, ECCS 0950305), the
Nanoelectronics Research Initiative (NRI) of the Semiconductor Research Corporation Electron Devices Meeting (IEDM) that demonstrated NiO
(SRC) through the NSF/NRI Supplement to the NSF NSEC Center for Probing the memory cells integrated with conventional 0.18-m
Nanoscale (CPN), and the C2S2 and MSD Focus Center, two of six research centers
funded under the Focus Center Research Program (FCRP), a SRC subsidiary. The work complementary metal–oxide–semiconductor (CMOS) in
of S. Yu, B. Lee, and Y. Wu was additionally supported by the Stanford Graduate a one-transistor–one-resistor (1T1R) device structure. The
Fellowship, the Samsung Scholarship, and the O. G. Villard Engineering Fund at
Stanford University, respectively. This work was also supported in part by the Taiwan’s paper included a more complete set of memory-technology-
Ministry of Economic Affairs (MOEA) and CMOS wafers provided by Taiwan oriented data such as data retention, endurance, and
Semiconductor Manufacturing Corporation (TSMC).
H.-S. P. Wong, S. Yu, and Y. Wu are with the Department of Electrical Engineering, programming characteristics that suggested that a memory
Stanford University, Stanford, CA 94305 USA (e-mail: [email protected]). technology based on resistive switching may be feasible.
H.-Y. Lee, F. T. Chen, and M.-J. Tsai are with the Nanoelectronic Technology Division,
Electronics and Optoelectronics Research Laboratories, Industrial Technology The expectation for RRAM is that it will be a memory
Research Institute (ITRI), Chutung, Hsinchu 31040, Taiwan. technology that can be integrated with conventional CMOS
Y.-S. Chen is with the Nanoelectronic Technology Division, Electronics and
Optoelectronics Research Laboratories, Industrial Technology Research Institute (ITRI), in a simple way, using a material set compatible with the
Chutung, Hsinchu 31040, Taiwan and also with the Institute of Electronics Engineering, conventional CMOS fabrication environment and process
National Tsing Hua University, Hsinchu 30013, Taiwan.
P.-S. Chen is with the Nanoelectronic Technology Division, Electronics and temperatures that allow it to be fabricated on the metal layers
Optoelectronics Research Laboratories, Industrial Technology Research Institute (ITRI), or within the contact vias to the source and drain of a metal–
Chutung, Hsinchu 31040, Taiwan and also with the Department of Chemical and
Materials Engineering, Ming Hsin University of Science and Technology, oxide–semiconductor field-effect transistor (MOSFET) of a
Hsinchu 30401, Taiwan. CMOS chip. Because the fabrication temperature is back-
B. Lee was with the Department of Electrical Engineering, Stanford University,
Stanford, CA 94305 USA. He is now with Samsung Electronics, end-of-the-line (BEOL) compatible, it is often additionally
Hwasung 445-701, Korea. envisioned that the RRAM can be stacked in 3-D in a cross-
Digital Object Identifier: 10.1109/JPROC.2012.2190369 point architecture with an effective memory cell area of
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Wong et al.: Metal–Oxide RRAM
4 F2 =n, where n is the number of 3-D-stacked memory layers to LRS is called the Bset[ process. Conversely, the switch-
[10]. On the system level, it is envisioned that a revolution in ing event from LRS to HRS is called the Breset[ process.
memory hierarchy and system architecture will be realized Usually for the fresh samples in its initial resistance state, a
by this low-cost, BEOL-compatible, nonvolatile memory voltage larger than the set voltage is needed to trigger on
with tens of nanosecond bit-alterable read/write speed, the resistive switching behaviors for the subsequent cycles.
over 106 endurance cycles, and potentially low power/ This is called the Belectroforming[ or Bforming[ process.
energy consumption. The switching modes of metal–oxide RRAM can be
While the concept of a MIM memory cell is simple, to broadly classified into two switching modes: unipolar
give a comprehensive review of the topic is virtually im- and bipolar. Fig. 1 shows a sketch of the I–V characteristics
possible. This is because there are numerous materials that for the two switching modes. Unipolar switching means
exhibit resistive switching. The switching behavior is not the switching direction depends on the amplitude of the
only dependent on the oxide materials but also dependent applied voltage but not on the polarity of the applied volt-
on the choice of metal electrodes and their interfacial age. Thus, set/reset can occur at the same polarity. If the
properties. Recent reviews by Waser et al. [11]–[13], Sawa unipolar switching can symmetrically occurs at both posi-
[14], and Akinaga et al. [15] provide excellent broad over- tive and negative voltages, it is also referred as a nonpolar
views and a useful taxonomy of the proposed switching and switching mode. Bipolar switching means the switching
conduction mechanisms of the various types of RRAM and direction depends on the polarity of the applied voltage.
will not be repeated here. And we will not discuss the Thus, set can only occur at one polarity and reset can only
conductive-bridge RAM (CBRAM) [16], which relies on occur at the reverse polarity. For either switching modes,
the fast-diffusing Ag or Cu ions into the oxide (or chalco- to avoid a permanent dielectric breakdown in the set pro-
genide) to form a conductive bridge. In this paper, we focus cess, it is recommended to enforce a set compliance, which
on the simple binary metal–oxide RRAM and review its is usually provided by the semiconductor parameter ana-
proposed resistance switching mechanisms (Section II), lyzer, or more practically, by a memory cell selection
materials properties and device characteristics (Section III), transistor/diode or a series resistor. To read the data from
memory cell, selection device and memory array design the cell, a small read voltage is applied that does not affect
considerations (Section IV), and key performance metrics the state of the memory cell to detect whether the cell is in
and their device scaling trends (Section V). Even when we HRS or LRS.
limit this review to binary metal oxides, there are still too There have been many efforts in the literature to fit the
many materials to cover. We selected some of the more I–V characteristics of current conduction in the HRS and
promising or interesting materials (HfOx , AlOx , NiOx , TiOx , the LRS. Most reports show a linear or ohmic relationship
and TaOx ) and review them in more detail. Note that the in the LRS. But, the conduction characteristics in HRS are
oxides here are often nonstoichiometric, thus we use quite diverse: Poole–Frenkel emission ðlogðI=VÞ V 1=2 Þ
subscript Bx[ for the oxygen composition in this review [17], [18], Schottky emission ðlogðIÞ V 1=2 ) [19], [20],
paper. Section VI concludes this paper with a future outlook the space charge limited current (SCLC) characteristic
for RRAM and its emerging applications for reconfigurable (the ohmic region I V, and the Child’s square law region
logic and neuromorphic computing. I V 2 ) [21], [22] were observed in various metal–oxide
RRAMs.
A simple I–V fitting with the aforementioned estab-
II. RESISTIVE S WITCHING MECHANISM lished model may not be sufficient to describe the con-
We first introduce some basic concepts and terminologies duction in metal–oxide RRAM. In general, Fig. 2 shows
about metal–oxide RRAM. The switching event from HRS all the possibilities for an electron pass from cathode to
Fig. 1. (a) Schematic of MIM structure for metal–oxide RRAM, and schematic of metal–oxide memory’s I–V curves, showing two modes of
operation: (b) unipolar and (c) bipolar.
1952 Proceedings of the IEEE | Vol. 100, No. 6, June 2012

A. Forming/Set
The forming/set process for the fresh samples is inter-
preted to be a dielectric soft breakdown [27]. Statistical
time-dependent dielectric breakdown (TDDB) measure-
ments show the exponential dependence of forming time
on applied voltage, confirming that forming process is not
a spontaneous process at some critical voltage, but an
upsurge process resulting from stress-induced defects [28].
Under the high electric field (> 10 MV/cm), the oxygen
atoms are knocked out of the lattice, and drift toward the
anode. Simultaneously, defects in the bulk oxide are gene-
rated. The localized deficiency of oxygen leads to the for-
mation of CFs with either oxygen vacancies [29] or metal
precipitates [30]. The localized CFs paths were observed in
various metal–oxide RRAMs by conductive atomic force
Fig. 2. Schematic of the possible electron conduction paths
through a MIM stack. (1) Schottky emission: thermally activated
microscopy (C-AFM) confirming the filamentary conduc-
electrons injected over the barrier into the conduction band. tion mechanism [31]–[34]. Usually the as-deposited RRAM
(2) Fowler–Nordheim (F–N) tunneling: electrons tunnel from the oxide thin films are amorphous or polycrystalline, and the
cathode into the conduction band; usually occurs at high field. CFs are preferentially generated along the grain bound-
(3) Direct tunneling: electron tunnel from cathode to anode directly; aries as revealed by C-AFM [35]. Recently, Kwon et al. [36]
usually occurs when the oxide is thin enough. If the oxide has
substantial number of traps (e.g., oxygen vacancies), trap-assisted
directly observed the nanoscale (G 10 nm in diameter) CFs
tunneling contributes to additional conduction, including the following with oxygen-deficient phase in TiOx memory by imaging
steps: (4) tunneling from cathode to traps; (5) emission from trap to the cross-section image of the MIM structure by high-
conduction band, which is essentially the Poole–Frenkel emission; resolution transmission electron microscopy (HR-TEM).
(6) F–N-like tunneling from trap to conduction band; (7) trap to trap In fresh samples, usually the amount of intrinsic defect
hopping or tunneling, maybe in the form of Mott hopping when the
electrons are in the localized states or maybe in the form of metallic
is few, thus a high forming voltage is needed to initiate the
conduction when the electrons are in the extended states depending switching. After the forming, a sufficient amount of de-
on the overlap of the electron wave function; and (8) tunneling from fects is present. In the subsequent switching cycles, only a
traps to anode. Adapted from [23]. portion of the defects, the ones near one electrode, can be
recovered during the reset process. This is why the set
voltage is smaller than the forming voltage, and the resis-
anode [23] (note that most of the RRAM oxides are n-type tance in HRS is much smaller than the resistance in the
conducting). Whether any one particular process dom- initial fresh samples. Often, the remaining defect-rich re-
inates is determined by its transition rate; electrons would gion is referred to as the Bvirtual electrode.[
seek the least resistive paths among all the possibilities. Obviously, it is not desirable to have a large forming
Therefore, various metal–oxide RRAMs may have different voltage in practical applications. Thus, significant efforts
dominant conduction mechanism depending on the dielec- have been made to achieve the so-called Bforming-free[
tric properties (bandgap or trap energy level, etc.), the devices. It is found that the forming voltage is linearly
fabrication process conditions (annealing temperature, dependent on the thickness of the oxide film [37]–[39]. So
annealing ambient, etc.), and the properties of the inter- a thinner oxide film is effective for reducing the forming
face between the oxides and the electrodes (interfacial voltage. Lee et al. [37] showed that HfOx memory is free
barrier height). For HfOx memory, Yu et al. verified that at from the forming process as the thickness of the film is
low bias regime the HRS conduction is dominated by trap- reduced to 3 nm. Forming is also a strong function of film
assisted tunneling using various characterization techni- deposition conditions [40]. It was found that controlling
ques such as varying temperature [23], [24], low-frequency the annealing ambient during deposition is also helpful in
noise [25], and alternate current (AC) conductance reducing the forming voltage [41]–[43], possibly due to the
measurement [26]. The I–V relationship at the low bias introduction of defects to make the films oxygen deficient.
regime is mainly determined by the electron conduction
process for a given configuration of the conductive B. Unipolar/Bipolar Reset
filaments (CFs), while at the high bias regime, the motion Although the forming/set mechanism appears to have a
of atoms (such as oxygen ions/vacancies) would change the consensus as discussed above, the reset mechanism for
configuration of the CFs and trigger a change of the different switching modes is a controversial topic. It seems
current. The details of the physical mechanism for a that the thermal dissolution model [44] can explain parts
resistance switching phenomenon in metal–oxide memory of the unipolar switching characteristics, while the ionic
are still an active research area. Here we aim to give a broad migration model [45] can explain parts of the bipolar
overview for simple binary metal–oxide RRAM. switching characteristics. However, a full physical
Vol. 100, No. 6, June 2012 | Proceedings of the IEEE 1953

Table 1 The Switching Modes for Various Metal–Oxide RRAM Devices property of both the oxide material and electrode/oxide
With Different Electrode Combination
interfaces. In most cases, the unipolar mode is obtained
with a noble metal such as Pt or Ru as both top and bottom
electrodes. With one of the electrodes replaced by oxidi-
zable materials such as Ti or TiN, the bipolar mode is
obtained. Zhou et al. [62] performed TEM and Auger
electron spectroscopy (AES) analyses on the depth profile
of the CuOx memory, and found the interfacial TaON layer
may be responsible for the bipolar TaN/Cux O/Cu struc-
ture, while no interfacial oxide layer is found for the
unipolar Pt/Cux O/Cu structure.
Based on the above observations, Yu et al. [63] proposed
description of the two switching modes that can explain all a unified reset mechanism for both unipolar/bipolar modes.
the experimental observations is still incomplete for these Fig. 3 is a schematic illustration of switching processes.
models. During the forming process, soft dielectric breakdown oc-
Experimental observations by various materials charac- curs and oxygen ions drift to the anode interface by the high
terization techniques reveal that the oxygen migration is electric field, where they are discharged as neutral nonlat-
present in the switching process and plays an important tice oxygen if the anode materials are noble metals or react
role in both bipolar devices [46]–[49] and unipolar devices with the oxidizable anode materials to form an interfacial
[50]. Electrothermal calculations suggest that the local oxide layer. Thus, the electrode/oxide interface behaves
temperature around the CFs would rise by several hundred like an Boxygen reservoir[ [64]. For a memory cell in the
Kelvin due to the large current flow [51]–[53], which may LRS, the current flows through the CFs in the bulk oxide.
enhance the oxygen migration. In addition, it is found that During the reset process, oxygen ions migrate back to the
the electrode materials have a significant effect on the bulk either to recombine with the oxygen vacancies or to
switching modes of the metal–oxide memory. Table 1 oxidize the metal precipitates and return the memory cell
summarizes the switching modes for various metal–oxide to the HRS. For devices that switch in the unipolar mode,
memories with different electrode combinations [7], [8], Joule heating from the current thermally activates the
[18], [54]–[61]. Even with the same oxide material but diffusion of oxygen ions. Oxygen ions diffuse from the in-
with different electrode materials, the switching modes terface or the region around the CFs [65] due to the con-
can be different. Therefore, it is inferred that the switching centration gradient, thus usually the unipolar switching
mode is not an intrinsic property of the oxide itself but a mode requires a relatively higher reset current to raise the
Fig. 3. Schematic illustration of the switching process in the simple binary metal–oxide RRAM. Adapted from [68].

Table 2 Summary of the Materials That Have Been Used for Binary Metal–Oxide RRAM. Metals of the Corresponding Binary Oxides Used for the
Resistive Switching Layer Are Colored in Yellow. Metals Used for the Electrodes Are Colored in Blue. Adapted From [68]
local temperature around CFs. For devices that switch in on these oxides are discussed in the following sections. The
the bipolar mode, the interfacial oxide layer may present a deposition methods of these binary metal oxides usually
significant diffusion barrier, and pure thermal diffusion is include the oxidation of a corresponding metal, reactive
not sufficient, thus oxygen ions migration needs to be aided sputtering, pulse laser deposition (PLD), and atomic layer
by the reverse electric field. The physical picture presented deposition (ALD). Among these methods, ALD is recently
here combines the previous thermal model [44] and ionic widely used due to the ability to precisely control the
migration model [45]. This picture can at best be viewed as thickness and uniformity of the thin film.
a phenomenological description of the above experimental
observations for the binary metal–oxide RRAM. Details of
A. Hafium Oxide (HfOx )
the physics of switching remain an area of active research.
HfOx -based materials have been employed as a high-k
Alternative theories have been proposed, such as those by
dielectric for the gate insulator for high-performance
Strukov et al. [66] and Yang et al. [67].
CMOS MOSFETs [72]. Interestingly, defect-rich HfOx is
also a superior RRAM material. In the early stage of HfOx
memory exploration, the TiN/HfOx /Pt structure [73] is
II I. MATERIAL AND DEVICE usually employed to achieve the bipolar switching charac-
PROPERT IE S teristics. In this structure, TiN acts as an oxygen reservoir.
Plenty of binary metal oxides have been found to exhibit To make the fabrication process to be CMOS compatible
resistive switching behavior. Most of them are transition (avoiding the uses of Pt since Pt is hard to etch), TiN/metal
metal oxides, and some are lanthanide series metal oxides. capping layer/HfOx /Pt structure is used. The metal cap-
The materials for the resistive switching oxide layer and ping layer is inserted to deplete the O atoms from the HfOx
the electrodes are summarized in Table 2. Note that some thin film and act as an oxygen reservoir. Lee et al. [37]
conductive nitrides, e.g., TiN and TaN, are also used as adjusted the dielectric strength of HfOx with a Ti capping
electrode materials. Among various oxides, CuOx [69], layer by postdeposition annealing. In Fig. 4(a), a schematic
[70] and WOx [71], are most compatible with the conven- diagram of a typical RRAM cell consisting of HfOx film
tional CMOS process because a simple additional oxida- with a transistor as a current limiter (the 1T1R configu-
tion step of the Cu or W via/plug is needed. Due to the ration) is illustrated. Fig. 4(b) shows the HR-TEM image of
limited space, we will not discuss them. Here we choose the stacked layers consisting of TiN/Ti/HfOx /TiN. The
HfOx , AlOx , NiOx , TiOx , and TaOx , because they have typical I–V curve for the resistive switching of the
drawn most attention and have been extensively studied in device, including 1R and 1T1R configuration, is demon-
the past several years. The properties of the devices based strated in Fig. 5(a). The resultant bipolar HfOx RRAM with

devices reported in the early literatures show typical

switching current in the order of mA or hundreds of A.
Wu et al. [75] first demonstrated low reset current down to
1 A in Al/AlOx /Pt stack. Recently, Kim et al. [76] doped
the AlOx with nitrogen and achieved even lower reset
current (G 100 nA). The low power/energy consumption of
AlOx memory is attractive. Furthermore, the low reset
current leads to LRS resistance above M. The higher LRS
resistance can potentially enable ultralarge-scale memory
arrays without selection devices because the sneak leakage
currents are significantly reduced due to the high LRS
Fig. 4. (a) A typical 1T1R structure of RRAM with HfOx ; (b) HR-TEM resistance [77].
image of the TiN/Ti/HfOx /TiN stacked layer; the thickness of the AlOx can also be stacked with other RRAM materials
HfO2 is 20 nm. to improve the uniformity of the device characteristics.
Chen et al. [78] used an AlOx buffer layer underneath the
HfOx resistive layer to enhance the read disturb immu-
high-speed operation (G 10 ns) has large on/off ratio nity. Yu et al. [79] utilized a bilayer HfOx /AlOx cell struc-
(> 100), reliable switching endurance [> 106 cycles; ture and obtained better switching uniformity than the
Fig. 5(b)], long high-temperature lifetime, multibit stor- pure HfOx layer cells.
age, and high device yield (100%). The same group also
used AlCu and Ta as the capping layer for the HfOx mem-
ory. These devices also show stable bipolar resistance C. Nickel Oxide (NiO)
switching but they have a small on/off ratio (4) [22]; NiO is one of the earliest materials investigated for the
the oxygen capture ability of the capping metal layer may RRAM application. It has been reported that various me-
be responsible for these results. With an ultrathin HfOx tals, such as Pt, Au, W, Ru, and Ni, can be used as the
(3 nm), the Ti/HfOx stack after a postmetal anneal electrodes in the NiO memory. When using these metals as
exhibits forming-free characteristics [37]. Recently, electrodes, NiO usually shows unipolar switching behav-
Govoreanu et al. [74] reported excellent performances ior. The reported reset voltages range from 0.5 to 2 V and
for a 10-nm 10-nm TiN/Hf/HfOx /TiN RRAM stack with reported set voltages range from 1 to 3 V after the forming
Hf as the capping layer. So far, HfOx is one of the most process. Programming endurance has been demonstrated
mature RRAM materials explored. up to 106 cycles and retention time is larger than eight
months [9] [Fig. 6(a) and (b)]. Previously, the reset cur-
rent of NiO memory has been usually large (> mA), but
B. Aluminum Oxide (AlOx ) recently reset current smaller than 10 A has been re-
The first observation of negative resistance phenome- ported [80] [Fig. 6(c)].
non of anodic AlOx can be traced back several years ago to Due to the unipolar switching property, NiO allows for
the report by Hickmott [1]. AlOx memory behaves in a way use of diode [Fig. 6(d)], instead of transistor, for selecting
similar to HfOx memory in many characteristics. In addi- a memory cell in the memory array during write and read
tion, AlOx is of interest because of the lower reset current, operations as the one-diode–one-resistor configuration
possibly due to a large band gap (8.9 eV). Most RRAM (1D1R) [81]. However, because of the unipolar switching
Fig. 5. (a) Bipolar resistance switching characteristic of TiN/TiOx /HfOx /TiN device in 1R and 1T1R configuration.
(b) Switch endurance of 106 cycles by 500-s pulse. Reprinted from [37].

Fig. 6. (a) Programming endurance data measured from a NiO memory demonstrating 106 cycles; adapted from [9]. (b) Retention of
the two states (ON/OFF) measured from NiO for eight months; adapted from [9]. (c) Reset current as low as 2 A with NiO; adapted from [80].
(d) I–V characteristics of a NiO memory cell in series with a diode; adapted from [81]. The leakage from the unselected memory cells can be
suppressed by the reverse bias on the 1D1R stack.
property for which the set and reset are the same voltage TiO2x layer has been deliberately stacked with the
polarity, it is crucial to have narrow distributions of set and stoichiometric TiO2 layer to form a bilayer structure.
reset parameters. Poor switching uniformity is one of the Yang et al. [67] fabricated 50-nm 50-nm Pt/TiO2 /
well-known issues with NiO RRAM, which has to be over- TiO2x /Pt devices, which showed bipolar switching with
come to achieve low failure rate and possible multilevel set occurring under the negative bias on the top electrode.
capability. Recent studies showed that the uniformity of Strukov et al. [66] proposed that the switching mechanism
NiO can be improved by using novel nanoscale CFs con- of this device is due to the migration of the positive
fined structures [82]. charged oxygen vacancies that push forward/backward
the oxygen rich/poor region interface front. However,
D. Titanium Oxide (TiOx ) Do et al. [88] fabricated a similar Pt/TiO2 /TiO2x /Pt cell
TiOx is also one of the earliest materials investigated structure, and found the bipolar switching direction is
for the RRAM application. Although extensive studies have opposite with set occurring under a positive bias on the
been carried out for TiOx RRAM, most of these studies top electrode. At this point, there is no consensus on the
focused on investigating the switching mechanism and thus switching mechanism for such oxygen-rich/oxygen-poor
there is limited endurance and retention data in the bilayer structure.
literature. As noted before, Kwon et al. [36] directly ob-
served the nanoscale CFs in TiOx memory by HR-TEM, and E. Tantalum Oxide (TaOx )
identified the CFs composition to be the oxygen-deficient TaOx recently has drawn much attention due to good
Magnéli phase, e.g., Ti4 O7 . endurance. X-ray photoelectron spectroscopy (XPS) [89]
Pt/TiO2 /Pt cell shows the typical unipolar switching and electron energy-loss spectroscopy (EELS) [90] reveal
behavior [8], [34], [83], [84]. In principle, bipolar reset that TaOx usually consists of two phases and oxygen mig-
can coexist in symmetric unipolar switching devices. How- ration exists between the two phases during the switching:
ever, the reset current for the unipolar reset is larger than one is closer to TaO2 phase (more conducting), and the
that for the bipolar reset in Pt/TiOx /Pt cells [85], [86]. other is closer to Ta2 O5 phase (more insulating). And
Pt/TiOx /TiN cell showed bipolar switching behavior as TaO2 /Ta2 O5 bilayer stack can be intentionally designed as
expected. Yet, the unipolar reset is still observable at the RRAM stack [91]. Wei et al. [89] reported a pulse switch-
Pt/TiOx interface [87]. Recently, the substoichiometric ing endurance (> 109 cycles) in TaOx memory. Yang et al.

[92] reported a pulse switching endurance (> 1010 cycles)

in TaOx memory. Lee et al. [91] reported a pulse switching
endurance (> 1012 cycles) in TaOx memory. Such a long
endurance capability enables RRAM devices to be used in
embedded memory applications and potentially can make
a change of the memory hierarchy.
IV. RRAM MEMORY ARRAYS
A. Cell Design
A filamentary RRAM device exhibits a characteristic of
abrupt current increase during the forming/set process,
when CFs are formed/reformed in the oxide matrix.
Therefore, a current limiter, which can optimally clamp
the forming/set current, is necessary for the filamentary
switching device to prevent the degradation of HRS and
even the failure of the memory device [37], [93], [94]. Due
to the benefits of fast response time and very large resis-
tance at the saturation region, a transistor is a better cur-
rent limiter than an external electrical measurement
instrument [37], [93]. Special consideration must be taken
in the design of memory cell of 1T1R structure to avoid
having a large parasitic capacitance between the transistor Fig. 7. Ireset versus Icomp in various measurement configurations.
and the RRAM. The parasitic capacitance causes overshoot Configuration A: 1R with semiconductor parameter analyzer.
current during the forming/set process which in turn in- Configuration B: 1T1R with monitor pad. Configuration C: 1T1R.
creases the reset current [37], [93]. Specifically, during the Adapted from [93].
forming/set process, the RRAM resistance changes in-
stantly while the voltage drop across the RRAM cannot
drop instantly due to the presence of parasitic capacitance.
Therefore, during the overshoot period that the voltage device with a concave structure, which has a large parasitic
across the RRAM gradually decreases, excessive oxygen capacitance due to the supporting oxide, shows larger
vacancies form and the CFs tend to grow laterally and overshoot current than the ones with a pillar structure.
increase in diameter or multiple CFs can be generated. The contact RRAM, which minimizes the parasitic capa-
Fig. 7 shows that the 1T1R configuration can effectively citance from the interconnect between the transistor and
limit the current overshoot. While this observation was the RRAM by fabricating the RRAM directly on the
investigated primarily for explaining the correlation be- MOSFET’s source/drain contact, can provide good current
tween the reset current and the compliance current for clamp in sub-100-A region [95].
directly probed RRAM, we note that the analogous situa-
tion of parasitic capacitance is present in a large memory B. Process Technology
array. The bit line capacitance plays the role of the parasi- Although the preferred material for RRAM technology
tic capacitance in a large memory array with long bit lines. has not been determined yet, the fabrication process of the
This is a direct result of the large resistance ratio and the memory cell should be carefully controlled to prevent the
high HRS resistance of RRAM. aforementioned oxide layers from suffering process dam-
Since the maximum reset current for the memory de- age, such as plasma damages from the etching step and the
vice is almost the same as the compliance current in the deposition process. Avoiding the forming process, which
forming/set process, one can evaluate the degree of needs voltage larger than the set process and increases
overshoot current in the memory cell by comparing the testing time of the memory chip, is of great importance in
difference between the maximum reset current and nomi- the study of filamentary switching devices, as mentioned
nal compliance current used in forming/set process: the earlier. However, the methods for fabricating a forming-
greater is the current difference between the maximum free device such as reducing oxide thickness may increase
reset current and the nominal compliance current, the the initial defect density and also severely decrease the
larger is the overshoot current through the memory cell resistivity of the oxide layer and may decrease the resis-
during the forming/set process [37], [43], [93], [94]. tance of HRS. Therefore, there is a compromise between
Gu et al. [94] reported that the device structure also plays a the forming voltage and memory window. On the other
role in determining the overshoot current. The memory hand, the metallic residue on the sidewall of the memory

cell, which leads to unwanted leakage path, should be crystalline silicon p/n diode is not compatible with the
avoided during the etching process [96]. BEOL low-temperature processing. For the unipolar
Since the breakdown voltage of dielectrics depends on RRAM, several oxide-based diodes with large on/off ratio
the number of defects rather than the defect density in the have been demonstrated, such as NiOx /TiOx [10] and
dielectric layer, the breakdown voltage increases with the CuOx /InZnOx [81]. With GaInZnO peripheral thin-film
decreasing device size and a linear correlation was found transistor and CuOx /InZnOx diode, Lee et al. realized all
between the breakdown voltage and the device size in log– oxide 3-D RRAM [104]. Tallarida et al. [105] showed
log scale [97], [98]. Because the forming process leads to a Schottky diode (Ag/ZnO/TiAu) using ZnO. For the
oxide breakdown in the RRAM device, this linear corre- bipolar RRAM, a bidirectional diode, which provides large
lation was also found between the forming voltage and the on/off current for both voltage polarities, is necessary.
device size and can be used to monitor the fabrication Huang et al. [106] showed a 1D1R stack (Ni/TiOx /Ni/
process of the memory cell across a range of cell sizes. In HfOx /Pt) using HfOx as memory cell and Ni/TiOx /Ni as
the work of Gu et al. [95], as the device is scaled down to bidirectional diode with current density 105 A/cm2 . Re-
the nanoscale region, the sidewall reaction between the cently, Kawahara et al. [107] showed a 1D1R stack (Ir/
encapsulating low-temperature oxide and the Ti layer in Ta2 O5 /TaO2 /TaN/SiNx /TaN) using TaOx as memory cell
the Ti/HfOx memory becomes important and results in and TaN/SiNx /TaN as bidirectional diode with current
deviation of the forming voltage from the predicted value. density 105 A/cm2 , and based on this structure, they de-
An alternative low-temperature nitride encapsulating layer monstrated a 8-Mb macrocircuit with G 25-ns write/read
was proposed to suppress this sidewall reaction. time using 0.18-m technology. However, the current
densities of these oxide diodes currently are not large
C. Memory Array enough to program RRAM at sub-30-nm dimensions. For
To effectively clamp the forming/set current, nor-type example, assuming a 20-nm 20-nm RRAM with a 5-A
memory array with 1T1R unit cell is preferred for a fila- reset current, it requires a cell selection device that can
mentary RRAM device. The nor-type RRAM memory deliver current density at 1.25 MA/cm2 . The oxide diodes
roughly includes the following components: memory array, demonstrated so far can provide large enough current to
word line decoder, bit line decoder, sense amplifier, output program the RRAM only because the device areas were
buffer, read driver, and write driver. Sato et al. [99] large. Besides diodes, a device that shows a threshold
demonstrated that NiO unipolar RRAM with nor-type switching can also serve as the selector. For example,
memory array can have a unit cell as small as 6 F2 in a Lee et al. [108] proposed using VO2 as a selection device,
0.18-m technology. They proposed a voltage-clamp tran- utilizing its metal–insulator–transition (MIT) property.
sistor connected to 1T1R unit cell to stabilize the reset However, the threshold voltage of MIT in VO2 strongly
pulse operation without undesirable set. However, mem- depends on the temperature, which rapidly drops to zero
ory array of this device cannot be shrunk accordingly in the when temperature rises to around 67 C [109], [110].
technology node beyond 90 nm. This is because the tran- Therefore, the thermal instability is a major barrier for
sistor in the column or source-selective gate should main- VO2 for practical applications. Kau et al. [111] used ovonic
tain the same size adopted in 0.18-m technology node to threshold switch (OTS) and achieved 106 on/off ratio.
sustain the set and reset voltages, which is around 2 V and Gopalakrishnan et al. demonstrated mixed ionic electronic
cannot be reduced further. A unique circuit configuration, conduction (MIEC)-material-based bidirectional diode
where each pair of source lines connects to each source- with 107 on/off ratio and 15 MA/cm2 on current [112].
line selective gate, was proposed by the same group to Table 3 summarizes the memory cell selection device
allow the design of 6 F2 unit cells in the 90-nm technology published in the literature. It should be pointed out that
node [100]. nor-type memory array with 1T1R unit cell is there needs to be a balance between the conductivity of the
also adopted in bipolar RRAM [69], [89], [101], [102]. For nonlinear element such as the diode and the conductivity
example, Sheu et al. [102] demonstrated 4-Mb macro- of the RRAM itself. A highly resistive nonlinear element as
circuit of HfOx RRAM with G 10-ns write/read time using compared to the RRAM LRS resistance will reduce the
0.18-m technology. However, considering the shrinkage resistance window of HRS and LRS since most of the ap-
of memory array size, the bipolar RRAM, where both bit plied voltage will be dropped across the nonlinear element.
line and source line need to deliver the voltage signal, is On the other hand, a nonlinear element that is too con-
less competitive than unipolar RRAM one. In order to ductive as compared to the RRAM LRS resistance will not
reduce the bit cost of bipolar RRAM, vertical bipolar junc- be an effective current limiter.
tion transistor (BJT) has been proposed to replace the For cross-point memory array without the selection
planar MOSFET as the selection device [103]. device, a large nonlinearity in the I–V characteristics of the
To be implemented in the 3-D stacking memory in a RRAM itself is needed to mitigate the leakage current of the
cross-point architecture, usually a memory cell selection array [77]. For example, the CMOx , where both LRS and
device is needed at each crosspoint. For this purpose, a HRS are characteristic of a nonlinear I–V curve with very
1D1R configuration is needed. The traditional single- large current ratio between write and read operations, can

Table 3 Memory Cell Selection Device Published in the Literature. Adapted From [113] and Updated With Recent Experimental Results
be implemented in cross-point array without diode as the effectively confines the active switching area and thereby
selection device [114], [115]. A 64-Mb CMOx chip with may reduce the LRS variation. The HRS resistance varia-
0.5-F2 effective bit size has been realized in 0.13-m tion comes from the variation of the ruptured CFs length,
technology node by using four-layer cross-point array. A thus any small variation of the tunneling gap distance may
general analysis of the maximum allowable memory array be magnified to be an exponential dependence of the tun-
size for memory cells with highly nonlinear I–V curves, as neling current on the tunneling distance. Therefore, the
noted above, is given by Liang et al. [77]. HRS variation is a more severe problem. It is found that
the tail bits of the HRS variation correspond to a CF con-
figuration with oxygen vacancies left over inside the
V. KEY DEVICE tunneling gap region [116]. Essentially, the variation is an
PERFORMANCE METRICS intrinsic property of metal–oxide RRAM associated with
the stochastic atomic motion.
A. Uniformity Many efforts have been expended to improve the uni-
Poor uniformity of device characteristics is a major formity, and various materials engineering methods have
barrier to large-scale manufacturing of RRAM. Significant been explored. The first type of the methods is engineering
parameter fluctuations exist in terms of variations of the the electrode/oxide interface by embedding appropriate
switching voltages as well as the resistances in HRS and buffer layers. Kim et al. [117] proposed to use IrO2 as the
LRS. The variations of the resistance switching include top electrode for the NiO memory. Yu et al. [118] proposed
temporal fluctuations (cycle to cycle) and spatial fluctua- to stack a thin Al buffer layer between TiN electrode and
tions (device to device). The origin of the variations may be HfOx bulk oxide for the HfOx memory. The improvement
attributed to the stochastic nature of the oxygen vacancies/ of the set voltage distribution and resistance distribution is
ions processes, as discussed in [116]. The LRS resistance shown in Fig. 8. The second type of the methods is con-
variation comes from the variation of the number or the fining the CFs paths using the local electric field en-
size of CFs, thus the reduction of possible filament paths hancement effect by inserting the seeds in the bulk oxide.

Fig. 8. Uniformity improvement of Al buffered HfOx memory over pure HfOx memory: (a) the statistical distribution of set voltages (Vset )
obtained by 100 direct current (DC) sweep cycles; (b) the statistical distribution of resistances in HRS and LRS for 100 pulse sweep cycles.
Adapted from [118].
Chang et al. [119] proposed to embed Pt nanocrystals into the ral, the HRS resistance tends to decrease, and usually the
TiOx memory. Liu et al. [120] proposed to implant Ti atoms final failure state of RRAM cells is stuck with LRS and
into ZrOx memory. The third type is to directly confine the unable to reset back to HRS. This can be caused by too
region for the CFs paths by redesigning the cell structure or many defects such as oxygen vacancies accumulated during
reducing the cell area. Lee et al. [82] placed the NiO layer on the cycling in a number of ways: 1) too many oxygen va-
the sidewall between the top electrode and the bottom cancies generated at or near the electrode–oxide interface;
electrode in a cross-point architecture. The electric field is 2) too many oxygen vacancies in or near the filament;
enhanced at the bottom corner of the top electrode and 3) too many oxygen vacancies in the oxide matrix. It is also
device uniformity is thus improved. Lee et al. [121] scaled noticed that during the cycling, sometimes there is a worn
down the cell size of ZrOx /HfOx bilayer memory devices to phase of LRS where LRS tends to increase, which may be
50 nm. Compared with the large-size devices, these devices caused by a formation of interfacial oxide layer between
showed a remarkable improvement of the uniformity not the electrode and the oxide [125], [126]. The oxygen va-
only in cycle-to-cycle testing but also in device-to-device cancy accumulation is best mitigated by a verified reset
measurements across the wafer. Chang et al. [122] fabri- operation as in [78], which effectively puts oxygen back
cated vertically aligned ZnO nanorod memory devices with into the RRAM switching region, in a well-monitored fa-
the purpose of forming straight and extensible CFs along the shion. However, care must be taken not to overuse the
direction of each single nanorod. verified reset operation, because over-reset CFs become
Besides the materials engineering approaches above, difficult to set, if they are shunted by filaments or areas
novel programming methods are also helpful in reducing surrounding them which contain more oxygen vacancies
parameter fluctuations. Two effective verification techni- [125]. This nonuniformity of the oxygen vacancy distribu-
ques are carried out to tighten the distributions of HRS and tion is aggravated by the electric field nonuniformity aris-
LRS in [78]. By ramping up the reset voltage (VRESET ), the ing from the roughness of the bottom electrode. To address
HRS can be increased to acceptable resistance levels. How- this problem, Lee et al. [125] use chemical mechanical
ever, to constrain the LRS values to certain range, a higher polishing (CMP) to flatten the memory bottom electrode
set voltage (VSET ) must be applied to the device after reset, and demonstrated HfOx memory with endurance cycles
since in this way a stronger filament might be formed. The over 1010 using 40-ns write/erase pulses while maintain-
above HRS verification method is also demonstrated in ing a resistance ratio of around 20, which greatly improves
[123] for CuOx memory. Using multiple pulses rather than the endurance property compared to their earlier work
a single pulse [124] or using a ramped series of pulses [123] without CMP [37].
can also improve the cycle-to-cycle uniformity.
C. Retention
B. Endurance A data retention time longer than ten years is expected
Generally, the write endurance cycles of RRAM de- for nonvolatile memory. This retention must be main-
pend on a variety of factors: material, processing, device tained at thermal stress up to 85 C (operating temper-
structure, operation scheme. During the cycling, in gene- ature) and small electrical stress such as a constant stream

of read pulses. However, the combination of the require- realistic statistics on retention property can only be col-
ments on memory write speed (10 ns) and retention lected on large memory arrays and the tail bits of the
time (108 s) sets a voltage-time dilemma, discussed in failure time distribution become the limiting factor for the
[12], which suggests that a physical mechanism that has a whole array [130].
large nonlinearity of the order of 1016 is required. Clearly,
a thorough understanding of the physical mechanism of D. Multibit Operation
resistive switching is required to make reliable retention Among all memory characteristics, the so-called multi-
projections. The voltage-time dilemma may be resolved by bit operation or multilevel cell (MLC), which exploits the
the hyperbolic–sinusoidal (Bsinh[) dependence of oxygen layout area of a memory device to realize more than one
vacancies/ions drift velocity on the electric field [63]. It bit of digital data per cell, is a desirable capability for high-
was also experimentally observed that the switching time density memory application. RRAM modulates the resis-
for both set and reset transitions (in the range from ns to tance states to realize the MLC operation. As shown in
ms) decreases exponentially when the programming Fig. 9, the LRS resistance can be changed by the set cur-
voltage amplitudes are linearly increased [127], [128]. rent compliance possibly due to the modulation of the
One common extrapolation method in the literature is diameter or number of CFs, while the HRS resistance can
to take the devices to a high temperature, and monitor the be controlled by the reset stop voltage possibly due to the
device’s resistance by applying read pulses at certain time modulation of the ruptured CF length [37]. In addition, for
intervals, e.g., every 1 s, and extrapolate the resistance LRS, the current is clamped by the measurement instru-
evolution line to the ten-year point. However, this method, ment for the 1R device or by the gate voltage of the tran-
while easy to implement in an industrial test setting, has sistor for the 1T1R device. Therefore, minimizing the
its limitation, because although the RRAM can maintain overshoot is crucial for achieving multilevel states in LRS.
the resistance window over 104 or 105 s (the time interval For a memory array, the current clamping must be pro-
that is convenient for testing), it cannot be guaranteed that vided by on-chip circuits. Most RRAM material systems,
the resistance window is still adequate after 106 or 107 s such as CuOx [131], TiOx [55], HfOx [37], WOx [132], and
because it is often observed that the resistance window TaOx [133], were reported to be capable of MLC operation.
would collapse abruptly rather than gradually [129]. Also The largest number of resistance levels reported so far are
in this method, the read voltage stress is applied to the cell five levels without verification for the HfOx memory [37]
during the retention test. To minimize the effect of the and eight levels with verification for the WOx memory
read voltage stress, another often used method is to bake [132]. Recently, Yu et al. [127] proposed and verified two
the device at elevated temperatures for an extended period equivalent pulse programming schemes to achieve the
and then read out the resistances at specific times (after multilevel resistance values owing to the exponential
cool-down), e.g., 24 h, 100 h, and so on. An alternative voltage–time relationship: one is to exponentially increase
method is the temperature-accelerated method by varying the programming pulse width; the other is to linearly
the temperature to record the time-to-failure and draw the increase the programming pulse amplitude. Although both
Arrhenius plot to extract the activation energy, and then schemes were effective for achieving the target resistance,
extrapolate down to the operating temperature. In this the transient current response measurements suggest the
method, one has to wait until the failure occurs, thus it is second scheme consumes considerably less energy for the
more time consuming and expensive. The activation ener- programming.
gy extracted for TaOx memory is 1.2 eV [20], and for HfOx For MLC operation, first, enough resistance window
memory, it is 1.9 eV [129]. It should be mentioned that between any two states and the uniformity of each
Fig. 9. Multilevel characteristic for a TiN/TiOx /HfOx /TiN RRAM: (a) multilevel RHigh is obtained by controlling VStop and (b) multilevel RLow is
obtained by controlling ISet . (c) The retention of multilevel resistance values extrapolated to ten years at 85 C. Adapted from [37].

resistance state are required. Second, the cycling endur-

ance for each state is also an important criterion. This was
investigated for the WOx memory in [132] and [134].
Without verification, only four levels were obtained and
the endurance did not exceed 100 cycles [134]. However,
when verification is employed, the eight-level resistance
states were possible and the endurance of each state was
more than 8000 cycles [132]. Third, the thermal stability
of the stored data in each state is also important for the
MLC operation. For HfOx memory [37], [133], a four-level
cell remains stable for 3 104 s above 85 C. Last, the
read disturbance test of each resistance state must be
considered. Good immunity of read disturbance for four
resistance states in HfOx memory was demonstrated for
total read stress of 2 104 s (20 ms read for 106 cycles)
in [70].
As described earlier, verification can help improve the
uniformity of the two basic resistance states (HRS and
LRS) within an array. This can also be applied in the case
of MLC [102]. Fig. 10 shows the effect of successively
ramping up the compliance current (determined by word
line voltage for 1T1R configuration) to the desired level. As
the compliance current is ramped up, the resistance is
decreased further. In the event that an excessively low
resistance occurs, a reset operation is performed and the
compliance current ramp is reattempted to achieve the
target resistance.
E. Scaling Trends
The potential scalability to the nanometer regime is
one of the key motivations that push the development of
metal–oxide RRAM technology. Lee et al. [50] triggered
the localized switching events successfully in NiO memory
by manipulating the C-AFM, thus showing that the size of
CF can be lower than 10 nm. Therefore, in principle,
metal–oxide memory can potentially scale to sub-10 nm
dimensions. In recent years, more and more metal–oxide Fig. 10. MLC verification for HfOx RRAM array. The verify scheme
consists of ramping up the gate voltage (compliance current),
memory devices with sub-100-nm feature size have been
but applying a reset and repeating reramping in order to avoid
fabricated either by optical lithography [43], [95], nanoim- excessively low resistance. The desired outcome after verification
print lithography [67], [135], or e-beam lithography [82]. is shown at the bottom. Adapted from [102].
Chen et al. [78] scaled down the HfOx memory device size
to 30 nm, and demonstrated a 1-kb array with good yield.
Recently, Govoreanu et al. [74] aggressively scaled down
the HfOx memory device size to 10 nm 10 nm, while dependency on the cell area. This trend of increasing HRS/
retained the good performances. Besides the conventional LRS resistance ratio as cell area decreases is a benefit of
top-down fabrication approach, the self-assembly grown device scaling.
metal–oxide nanowires were able to exhibit the resistive The peak current during the reset process (defined as
switching behavior [136]–[138], further illustrating the the reset current) is another parameter of concern because
scalability of RRAM to the nanometer regime. the peak power consumption is mostly determined by the
The scaling trends of the RRAM device parameters are reset current. Most reports in the literature show a typical
examined next. Fig. 11 plots the general scaling trend of reset current for a single memory cell on the order of mA
HRS and LRS from various metal–oxide memories. The or hundreds of A. Fig. 12 plots the general scaling trend
resistance of HRS increases as the inverse of the cell area, of reset current and corresponding reset current density
roughly following the Ohm’s law. The conduction current for unipolar NiO memory [9] and bipolar HfOx memory
in the LRS is mainly filamentary conduction current, as [37]. It is seen that the reset current reduces only slightly
discussed before. So the resistance of LRS has only a slight when the devices are scaled down, thus leading to a

Fig. 13. The reset current versus set compliance current. Data are
Fig. 11. HRS and LRS resistance versus cell area of metal–oxide RRAM collected from [7], [93], [146], and [147].
devices. Data were from [9], [37], [139], [140], [47], [141], and [142].
the A regime, the parasitic capacitance should be mini-

remarkable increase of the current density required for mized [93]. Sub-100-A reset current has been success-
reset. This apparently presents a significant challenge for fully demonstrated in 1T1R cell structures by adjusting the
the memory cell selection devices, which need to provide selection transistor’s gate voltage to deliver a small set
such a large current density for ultrascaled cells, e.g., compliance current [37], [69], [99], [145]. However, as a
107 A/cm2 even for a relatively large 100-nm 100-nm consequence of the smaller set compliance, the LRS resis-
cell. tance becomes higher. For a certain HRS resistance, the
However, this apparent problem can be alleviated by requirement for a sufficient resistance window limits the
using a smaller set compliance current during the set smallest set compliance that can be used. Fortunately,
process, because the reset current is almost linear with the the HRS resistance rises up with the decrease of cell area,
set compliance current, as shown in Fig. 13. A possible as mentioned before. This means that for the scaled-down
reason for the linear correlation of set and reset current is memory cell, a higher LRS resistance can be tolerated, and
that a smaller set compliance current leads to weaker CFs a smaller set compliance can be utilized to achieve a lower
and those weaker CFs require a smaller reset current to reset current. In brief, the reset current does not depend
rupture them. To ensure this linear relationship well into on the cell area but depends on the set compliance current;
and in smaller area cells, smaller set compliance can be
used, therefore the reset current can scale down with de-
vice size. Capitalizing on this concept, Ahn et al. [143] used
5-A set compliance in a 100-nm 100-nm NiO memory
cell, and obtained a 50-A reset current (reset current
density: 5 105 A/cm2 ) with sufficient HRS/LRS ratio
(104 ), and Wu et al. [144] used 5-A set compliance in a
500-nm 10-nm (using several carbon nanotubes as one
of the electrodes) HfOx memory cell, and obtained sub-
5-A reset current (reset current density: 105 A/cm2 ) with
reasonable HRS/LRS ratio (10). However, such forward
current density (105 A/cm2 ) is still quite challenging for
today’s low-temperature grown diodes to be implemented
in the 1D1R cross-point memory architecture.
VI. FUTURE OUTLOOK

Fig. 12. The peak value of reset current and corresponding current The development of metal–oxide RRAM has progressed
density versus cell area. Data are collected from [9], [37], [143], and rapidly in the last five years. In particular, binary metal
[144]. Note that for the HfO2 [37] data, the set compliance current
oxides that use materials that are familiar to the semi-
was fixed at 500 A, while for the NiO [9] data, the set compliance
current changed from 200 to 20 A as the cell area is scaled down.
conductor industry have seen intense research and devel-
The HfO2 data from [144] used a set compliance current of 5 A. The opment in both industry and academia. The vision for
NiO data from [143] also used a set compliance current of 5 A. RRAM is a nonvolatile solid-state memory that is fast,

Table 4 A Representative List of Binary Metal–Oxide RRAM device characteristics. Data Are Collected From [9], [69], [146], [89], [37],
[78], [71], [121], [76], [155], and [74]
high-density, and compatible with integration with con- parameter variations, and provided insights into the origin
ventional Si CMOS technology. The early RRAM had large of the tail bits of the resistance distribution.
device areas, large programming currents (mA), long Since the device density is mostly determined by the
programming times (s), low endurance (G 103 cycles), memory cell selection device and not the memory cell
and requires a 1T1R structure which was limited in device itself, any expectations of device scalability and imple-
density. Today, many of these deficiencies have been over- mentation of the cross-point architecture in a 3-D fashion
come. Table 4 summarizes some of the recent advances necessarily need to ensure there is a scalable memory cell
of RRAM reported in the literature. Device sizes down to selection device that can provide the on/off character-
10 nm 10 nm have been published, programming istics and device density commensurate with the RRAM
currents are now in the order of A range, programming programming requirement and 4-F2 expectations. The
and read speed are on the order of ns, endurance cycles are challenge for a 3-D integrated RRAM is very much anal-
up to 1012 , retention time is up to 3000 h at 150 C, and ogous to those faced by phase change memory (PCM) and
the forming process can be eliminated. Chip-scale memory is already discussed in [113] and not repeated here.
arrays with megabit size were demonstrated. Demonstra- Currently, the best RRAM device has a bipolar switching
tions of multibit operation have been made, and rudimen- mode. This makes the search for a suitable cell selection
tary demonstration of integrated 1D1R-type devices for 3-D device even more difficult (as compared to, say, PCM) as
integration looks promising even though they do not meet the selection device has to conduct current in both direc-
all the requirements at this point. Meanwhile, further tions and the conventional reverse-bias blocking effect
understanding of the underlying physics of RRAM has cannot be used. The major remaining challenge is device
been obtained through modeling works from the atomistic uniformity. Device variation is a major barrier for using the
level to the device level. For example, Park et al. [148] RRAM in large memory arrays as well as MLC operation.
employed ab initio modeling techniques to study the There is still substantial cycle-to-cycle variation as well as
oxygen vacancy’s effect on the energy band diagram and device-to-device variation of the device characteristics. To
electron density of states, and revealed that the ordering of make progress in this area, it is necessary to have a more
oxygen vacancies into a filament would lead to substantial complete understanding of the conduction and resistive
increase of the conductivity. Yu et al. [116] developed a switching mechanism. In the end, the solution may come
Monte Carlo numerical simulator to quantify the electron from a combination of materials engineering, device struc-
conduction and the stochastic generation, recombination, ture optimization, as well as innovations in addressing/
and migration process of oxygen vacancies/ions during the readout circuitry.
switching. Simulations using this model empirically re- While RRAM has the potential to be a standalone,
produced the experimentally observed abrupt set process, high-capacity nonvolatile memory technology, it may be
gradual reset process, current fluctuations, and switching even more suitable for embedded applications. This is

because it offers the low programming voltage that FLASH with MLC and multiple 3-D integrated memory array
does not offer and the nonvolatility that DRAM does not layers, it is not entirely clear that these goals continue to
offer and yet has a speed that is comparable to DRAM. For make sense generally, given the many diverse potential
embedded applications, the endurance cycles must be applications of RRAM. For example, for embedded ap-
substantially improved. Novel applications that use RRAM plications, improving other attributes of RRAM appears to
as reconfigurable logic were also proposed. CMOS-nano be more important as far as research goals are concerned.
hybrid reconfigurable field-programmable gate array And the ability to put an RRAM at the contact vias of the
(FPGA) architecture was designed [149] and 3-D FPGA MOSFET without extensive process steps is an attractive
based on RRAM was reported [150]. Another emerging device feature, especially for applications where only a low
application is using RRAM as artificial synapse element for bit-count (memory capacity) embedded, multiple-time
hardware neuromorphic computing. Owing to RRAM’s programmable, nonvolatile memory is required. As sug-
multilevel capability and low power/energy consumption, gested in [113] and references therein, there is an enor-
it can behave like an analog memory emulating the mous opportunity to completely rethink the design of the
function of plastic synapses in a neural network. Recently, memory subsystem to gain orders of magnitude improve-
TiOx - [151], WOx - [152], and HfOx -based [153] synapses ments in speed and/or power consumption. A revolution in
have been demonstrated for spike timing-dependent plas- the memory subsystem will bring about a fundamental
ticity [154] in the device level. Although the early vision change in how one can extract performance out of tech-
for RRAM is to strive for a 4-F2 cross-point architecture, nology improvements. h
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ABOUT THE AUTHORS

H.-S. Philip Wong (Fellow, IEEE) received the B.Sc. (honors) degree from Yi Wu received the B.S. degree in microelectronics from Peking Uni-
the University of Hong Kong, Hong Kong, in 1982, the M.S. degree from versity, Beijing, China, in 2008. She is currently working toward the Ph.D.
the State University of New York at Stony Brook, Stony Brook, in 1983, degree in electrical engineering at Stanford University, Stanford, CA.
and the Ph.D. degree from Lehigh University, Bethlehem, PA, in 1988, all She is currently working on RRAM with a focus on the thin-film
in electrical engineering. properties study and the memory structure innovations.
He joined the IBM T. J. Watson Research Center, Yorktown Heights, NY,
in 1988. In September 2004, he joined Stanford University, Stanford, CA, Pang-Shiu Chen received the Ph.D. in materials science and engineering
as Professor of Electrical Engineering. His present research covers a from National Chiao-Tung University, Hsinchu, Taiwan, in 2000.
broad range of topics including carbon nanotubes, semiconductor He is currently an Associate Professor in the Department of Chemical
nanowires, self-assembly, exploratory logic devices, nanoelectromecha- and Materials Engineering, Ming Hsin University of Science and
nical devices, novel memory devices, and biosensors. Technology, Hsinchu, Taiwan. His research interests include RRAM and
transparent electronics.
Heng-Yuan Lee received the Ph.D. degree in electronics engineering
from National Tsing Hua University, Hsinchu, Taiwan, in 2010.
Byoungil Lee received the B.S. degree in electrical engineering from
He is currently a Device Engineer at the Industrial Technology Re-
Korea Advanced Institute of Science and Technology, Daejeon, Korea, in
search Institute (ITRI), Hsinchu, Taiwan. His research interests include
2005 and the Ph.D. degree in electrical engineering from Stanford
complementary metal–oxide–semiconductor (CMOS) technology and
University, Stanford, CA, in 2011.
nonvolatile memory technology.
He has been working on nanoscale RRAM devices, and joined
Samsung Electronics, Hwasung, Korea, as a Device Engineer.
Shimeng Yu (Student Member, IEEE) received the B.S. degree in micro-
electronics from Peking University, Beijing, China, in 2009. He is
currently working toward the Ph.D. degree in electrical engineering in Frederick T. Chen received the Ph.D. in applied physics from Cornell
Stanford University, Stanford, CA. University, Ithaca, NY, in 1996.
He has been working on the fabrication, characterization, and mod- He worked for nine years at Intel Corp. before moving to the Industrial
eling of RRAM devices and their applications for neuromorphic compu- Technology Research Institute (ITRI), Hsinchu, Taiwan, in 2005, where he
tation system since 2008. He has authored a book chapter and tens of is currently directing the RRAM research and development.
papers on these topics.
Ming-Jinn Tsai received the Ph.D. in materials science and engineering
Yu-Sheng Chen is currently working toward the Ph.D. degree in elec- from the Massachusetts Institute of Technology (MIT), Cambridge, in
tronics engineering in National Tsing Hua University, Hsinchu, Taiwan. 1991.
He is a Device and Testing Engineer at the Industrial Technology He then joined the Industrial Technology Research Institute (ITRI),
Research Institute (ITRI), Hsinchu, Taiwan. His research interests include Hsinchu, Taiwan. He is currently overseeing semiconductor-related path
complementary metal–oxide–semiconductor (CMOS) technology, non- finding projects and R&D collaborations with key academic and industrial
volatile memory technology, and circuit design for memory. partners, particularly those involving RRAM and power electronics.


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INVITED

ABSTRACT | In this paper, recent progress of binary metal– I. INTRODUCTION

1952 Proceedings of the IEEE | Vol. 100, No. 6, June 2012

Vol. 100, No. 6, June 2012 | Proceedings of the IEEE 1953

1954 Proceedings of the IEEE | Vol. 100, No. 6, June 2012

Vol. 100, No. 6, June 2012 | Proceedings of the IEEE 1955

devices reported in the early literatures show typical

1956 Proceedings of the IEEE | Vol. 100, No. 6, June 2012

Vol. 100, No. 6, June 2012 | Proceedings of the IEEE 1957

[92] reported a pulse switching endurance (> 1010 cycles)

IV. RRAM MEMORY ARRAYS

1958 Proceedings of the IEEE | Vol. 100, No. 6, June 2012

Vol. 100, No. 6, June 2012 | Proceedings of the IEEE 1959

1960 Proceedings of the IEEE | Vol. 100, No. 6, June 2012

Vol. 100, No. 6, June 2012 | Proceedings of the IEEE 1961

1962 Proceedings of the IEEE | Vol. 100, No. 6, June 2012

resistance state are required. Second, the cycling endur-

Vol. 100, No. 6, June 2012 | Proceedings of the IEEE 1963

the A regime, the parasitic capacitance should be mini-

VI. FUTURE OUTLOOK

1964 Proceedings of the IEEE | Vol. 100, No. 6, June 2012

Vol. 100, No. 6, June 2012 | Proceedings of the IEEE 1965

1966 Proceedings of the IEEE | Vol. 100, No. 6, June 2012

Vol. 100, No. 6, June 2012 | Proceedings of the IEEE 1967

1968 Proceedings of the IEEE | Vol. 100, No. 6, June 2012

Vol. 100, No. 6, June 2012 | Proceedings of the IEEE 1969

ABOUT THE AUTHORS

1970 Proceedings of the IEEE | Vol. 100, No. 6, June 2012

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