Nanoscale Advances: Minireview

Nanoscale
Advances
This article is licensed under a Creative Commons Attribution-NonCommercial 3.0 Unported Licence.
MINIREVIEW View Article Online

View Journal | View Issue
Research progress on solutions to the sneak path

issue in memristor crossbar arrays
Open Access Article. Published on 11 March 2020. Downloaded on 11/10/2021 4:01:52 AM.
Cite this: Nanoscale Adv., 2020, 2, 1811
Lingyun Shi,a Guohao Zheng,a Bobo Tian, *ab Brahim Dkhil b
and Chungang Duan ac
Since the emergence of memristors (or memristive devices), how to integrate them into arrays has been widely
investigated. After years of research, memristor crossbar arrays have been proposed and realized with potential
applications in nonvolatile memory, logic and neuromorphic computing systems. Despite the promising
prospects of memristor crossbar arrays, one of the main obstacles for their development is the so-called
sneak-path current causing cross-talk interference between adjacent memory cells and thus may result in
misinterpretation which greatly influences the operation of memristor crossbar arrays. Solving the sneak-path
current issue, the power consumption of the array will immensely decrease, and the reliability and stability will
simultaneously increase. In order to suppress the sneak-path current, various solutions have been provided.
So far, some reviews have considered some of these solutions and established a sophisticated classification,
including 1D1M, 1T1M, 1S1M (D: diode, M: memristor, T: transistor, S: selector), self-selective and self-rectifying
memristors. Recently, a mass of studies have been additionally reported. This review thus attempts to provide
a survey on these new findings, by highlighting the latest research progress realized for relieving the sneak-
path issue. Here, we first present the concept of the sneak-path current issue and solutions proposed to solve
Received 6th February 2020
Accepted 10th March 2020
it. Consequently, we select some typical and promising devices, and present their structures and properties in
detail. Then, the latest research activities focusing on single-device structures are introduced taking into
DOI: 10.1039/d0na00100g
account the mechanisms underlying these devices. Finally, we summarize the properties and perspectives of
rsc.li/nanoscale-advances these solutions.
a
Department of Electronics, Key Laboratory of Polar Materials and Devices (MOE), c
Collaborative Innovation Center of Extreme Optics, Shanxi University, Shanxi
East China Normal University, Shanghai 200241, China. E-mail: [email protected]. 030006, China
edu.cn
b
Laboratoire Structures, Propriétés et Modélisation des Solides, CentraleSupélec,
CNRS-UMR8580, Université Paris-Saclay, 91190 Gif-sur-Yvette, France
Lingyun Shi is an undergraduate Bobo Tian earned his Ph.D. in

student of East China Normal Microelectronics and Solid-State
University, and Key Laboratory Electronics from the University
of Polar Materials and Devices, of Chinese Academy of Sciences,
Ministry of Education, majoring Beijing, China and Central-
in Microelectronics Science and eSupélec, Université Paris-
Engineering. His research inter- Saclay, Paris, France in 2016.
ests include the design and Then he performed post-doctoral
analysis of nanostructures of research at East China Normal
memristor crossbar arrays, University and CentraleSupélec,
optical devices and radio Université Paris-Saclay. He is
frequency integrated circuits. now a young researcher at the
Relevant studies have been Key Lab of Polar Materials and
published in Opt. Commun. Devices (MOE), East China Normal University, China. His group is
currently working on ferroelectrics, memristors, and neuromorphic
computing. He has published over 50 papers in journals such as
Nat. Electron., Nat. Commun., Adv. Electron. Mater., Appl. Phys.
Lett., and Phys. Rev. B.
This journal is © The Royal Society of Chemistry 2020 Nanoscale Adv., 2020, 2, 1811–1827 | 1811
View Article Online
Nanoscale Advances Minireview
basics associated with its solutions. Especially, typical and

1. Introduction promising devices are presented in detail. Finally, we summa-
Information transfer between the central processing unit (CPU) rize the properties and perspectives of these solutions.
and the memories in von Neumann systems inevitably imposes
limits on the performance and scalability of the architecture 1.1 VMM based on memristor crossbar arrays
and results in large additional power consumption. This Memristor crossbar arrays whose discrete conductance states
problem becomes more severe for tasks needing vast vector stand for synaptic weights could accomplish efficient brain-
matrix multiplication (VMM) computing, such as real-time inspired computation. Massive parallelism could be per-
image recognition, data classication, and natural language formed in an analog manner using their intrinsic physical laws.
processing, where state-of-the-art von Neumann systems diffi- Fig. 1a shows a typical memristor crossbar array. Memristors
cultly work to match the performance of an average human are located at each cross point of top electrodes (rows) and
brain.1 A potential candidate hardware neuromorphic network, bottom electrodes (columns). The total current out of every
which mimics the operations of the human brain, has recently column is a summation of the current through each memristor
aroused much attention. Among numerous solutions to realize on this column following Kirchhoff's current law, while the
the required functions, neuromorphic networks based on current through the memristor is the multiplication of input
memristors appear extremely promising. One of the crucial voltage and memristor conductance following Ohm's law. This
obstacles for an efficient memristor crossbar array is the so- P
column current follows the formula: Ij ¼ Vi Gij . In the same
called sneak path current problem, which decreases the reli- i
ability of the array by importing error when programing/reading way, the charges collected from each column of the crossbar are
the resistance state of memristors. Vast research studies are
dedicated to solve this sneak-path current issue. Some general
reviews2–5 dealing with fundamental mechanisms, materials
and architectures of memristors have partially addressed the
sneak-path current problem and its solutions. Generally
speaking, most of the early studies focused on structures,
including one transistor-one memristor (1T1M), one diode-one
memristor (1D1M) and one selector-one memristor (1S1M).
Besides the multiple device solutions mentioned above, single-
device systems, including self-selective memristors and self-
rectifying memristors, have also drawn large amounts of
attention due to their simple structure. These solutions are not
only classied based on their I–V characteristics, but also
depending on the composition of the devices in a memory cell.
For a specic category, the devices differ from each other in Fig. 1 Diagrams show (a) a crossbar array, (b) the sneak-path issue in
terms of their intrinsic physical mechanisms. In this review, we the crossbar array, and (c) the equivalent circuit of the sneak-path
introduce the concept of the sneak-path current issue and issue.
Brahim Dkhil earned his Ph.D. Chungang Duan earned his

in Materials Science from the Ph.D. in theoretical physics from
University of Orsay and Ecole the Institute of Physics, Beijing,
Centrale Paris, France in 1999. Chinese Academy of Sciences,
Then he worked as a researcher China in 1998. Then he worked
at Ecole Centrale Paris. He also at the University of Nebraska,
worked as a visiting professor at USA from 1998 to 2007. Aer
Waseda University, Japan in that, he joined East China
2003, at Ioffe Institute, St Normal University as a full
Petersburg, Russia in 2005, and professor. He is now the director
at the Department of Physics, of Key Lab of Polar Materials
University of Arkansas, USA in and Devices, Ministry of Educa-
2007. Now he is a professor at tion, China. His group is
CentraleSupélec, Université Paris-Saclay, France. His group is currently working on ferroelectrics, multiferroics and neuro-
currently working on multiferroics, relaxors, ferroelectrics, piezo- morphic computing. He has published over 200 papers in journals
electrics and neuromorphic computing. He has published over 200 such as Nat. Electron., Nat. Commun., Phys. Rev. Lett., and Nano
papers in journals such as Nature, Nat. Mater., Nat. Commun., Lett. He has over 7000 citations.
and Phys. Rev. Lett. He has over 10 000 citations.
1812 | Nanoscale Adv., 2020, 2, 1811–1827 This journal is © The Royal Society of Chemistry 2020
View Article Online
Minireview Nanoscale Advances
P
expressed as: Qj ¼ Vti Gij , when input voltage pulses keep
i
a constant amplitude of V and vary their widths (ti). Thus, vector
matrix multiplication (VMM), which is the basis for parallel
computation in articial neural networks, could be imple-

mented by memristor crossbar arrays. In this VMM process by
memristor crossbar arrays, the value of a matrix cell is encoded
as the analogue memristor conductance of the crossbar array,
the input vector is encoded as different voltage pulse ampli-
tudes (widths) to the rows of the crossbar, and the VMM outputs
correspond to currents (charges) collected from columns of the
memristor crossbar.6–8 For the current domain VMM method,

according to Ohm's law, a strict linear current–voltage (I–V)
characteristic of the memristor is required so that voltage pulse
amplitudes are easily encoded as input vectors for multiplica- 1 1
tion computing. On the contrary, the charge domain VMM Fig. 2 Schematics of the V bias method (a) and V method (b).
2 3
method tolerates nonlinear current because the voltage pulse
widths are encoded as input vectors with a xed voltage pulse
amplitude. Furthermore, the xed amplitude immensely scheme, the selected word line and selected bit line are applied
simplies the peripheral circuits in the charge domain VMM full voltage (V) and 0 voltage, respectively. The unselected word
method. Both analog approaches nish the VMM computing in lines are applied V/3, whereas the unselected bit lines are
a single step, regardless of the matrix size, attracting huge applied 2V/3. Accordingly, the selected memristor is under V
interest for implementing brain-inspired computation.9 bias, half-selected memristors are under V/3 bias, and unse-
lected memristors are under V/3 bias. Note that more than one
selected cell could be programed parallelly in the memristor
1.2 Sneak path current issue
crossbar array. The V/2 bias in the V/2 method and V/3 bias in
During the analog VMM computing, the memristor conduc- the V/3 method inevitably contribute to energy consumption.
tances (resistances) in the crossbar array need to be duly The nonlinear I–V curves give a lower energy consumption than
updated. One of the crucial obstacles in the resistance the linear one. For a specic array size and nonlinearity, the V/3
programing and reading process is the so-called sneak path method is more energy efficient for small arrays; as the array
current problem. Fig. 1b and c show the case of sneak-path size increases and the number of selected cells decreases, the V/
current in a 2 2 crossbar array. When we intend to apply 2 method achieves greater energy efficiency.12
a voltage between A1 and B1 lines to switch the resistance state These bias schemes are effective ways to update and obtain
of memristor one (M1), the blue path is the desired current states of the memristor crossbar array. However, for realization
path. However, current could also un-intentionally ow through of efficient states update in situation where voltage pulses is
the red path which is called the sneak path current. Not only messaged and complicated, such as spike neural network, and
does it lead to incorrect reading of the resistance state of for a lower energy consumption, device level to suppress sneak
memristors, but it also disturbs the precise resistance modu- path currents issue for precise resistance modulation of the
lation of the array because M2, M3 and M4 memristors in series array is necessary.
also experience the voltage. The sneak path currents also induce
high energy consumption. Vast research studies are devoted to
this urgent and signicant task to eliminate or suppress the
sneak path current issue in memristor crossbar arrays. 2. Solutions to the sneak path current
issue
1.3 Programing and reading schemes in memristor crossbar 2.1 1T1M
arrays The 1T1M cell structure is an effective solution to the sneak-
The sneak path current could be effectively suppressed by path current issue. The 1T1M crossbar array is called the
designing the bias scheme for the programing and reading active crossbar array, where the series transistor plays the role of
process. As shown in Fig. 2, the resistance of memristors a switch. When the series eld effect transistor is in the ON-
sandwiched between word lines and bit lines is programed or state, it behaves much like a wire with high conductance.
read under two common types of write bias schemes: the V/2 Consequently, the voltage can entirely drop across the mem-
method10 and V/3 method.11 In the V/2 scheme, the selected ristor no matter the polarity of the biased voltage, which facil-
word line and selected bit line are applied full voltage (V) and itates the state switching of the memristor. When the series
0 voltage, respectively. The unselected word lines and bit lines eld effect transistor is in the OFF-state, nearly no current ows
are applied half voltage (V/2). As a result, the selected memristor through the cell and no voltage drops across the memristor. Via
is under V bias, half-selected memristors are under V/2 bias, and deliberately manipulating the ON–OFF state of transistors,
unselected memristors are under no bias. As for the V/3 bias precise selection of a designated memory cell can be realized.
View Article Online
processing and other machine learning tasks.6,13,26,27 Based on

the 1T1M crossbar array, they further demonstrated in situ
training of feed-forward and recurrent convolutional memristor
networks.28
Very recently, Wu's group demonstrated reliable and

uniform analogue switching behaviors in the 2048 1T1M
crossbar array of TiN/TaOx/HfOx/TiN devices.29 By integrating
eight 2048-cell 1T1M crossbar arrays on a printed circuit board
(PCB) and a eld-programmable gate array evaluation board
Fig. 3 Schematic diagram of a 1T1M crossbar.
(ZC706, Xilinx), they successfully built a ve-layer memristor-
based CNN and performed MNIST image recognition with

a high accuracy of more than 96 per cent. They demonstrated
A typical schematic diagram of the 1T1M crossbar array is that the energy efficiency in memristor-based CNN neuro-
shown in Fig. 3. Here the line which activates memristors is morphic systems is two orders of magnitude greater than that of
called the bit line (B), and the gate line (G) controls the ON/OFF the state-of-the-art graphics-processing units.29 Despite the
state of the cell. Bit-lines and gate-lines are usually perpendic- slightly overshadowed scaling issue, the 1T1M crossbar arrays
ular to each other. For example, when one control operation show great potential for neuromorphic application.
from A1 and B1 is implemented on M1 (gate-line 1 in the ON
state), the other adjacent gate-lines are set to the OFF state to
avoid crosstalk. Thus, the sneak path currents can be efficiently 2.2 1D1M
suppressed to enable accurate resistance programming and The 1D1M crossbar array with a unit cell area of 4F2 is a prom-
reading in the 1T1M crossbar array. The 1T1M has a cell area of ising architecture for high-density memory due to its excellent
8F2, which is relatively large and limits the scaling of the array scalability. As shown in Fig. 4a, the 1D1M cell structure is
and integration density. To minimize as much as possible the composed of two elements: one diode and one memristor, and
scaling issue, a high channel conductance of transistors is these two devices are connected in series. The current of
preferred. On the other hand, CMOS transistors take advantage a forward-biased diode is relatively large while the current is
of their sophisticated fabrication techniques and scalability, blocked when the diode is reverse-biased. By connecting a uni-
whereby large 1T1M crossbar arrays could be easily achieved. polar resistive switching device to this diode in series, this
Furthermore, by offering compliance currents, the gate lines in double-device structure displays a resistive switching behavior
the 1T1M crossbar array assist in obtaining the linear and with a rectifying property.30 Consequently, this rectifying prop-
symmetric conductance increase and decrease with minimal erty can be used to inhibit sneak current, as implied by the red
cycle-to-cycle and device-to-device variations.13 This is favored dashed line in Fig. 4a and b. In addition, the series diode also
by the time-efficient current domain VMM computing. acts as an external load resistor to suppress the overow current
Therefore, 1T1M crossbar arrays have already been widely during the resistance transition, which signicantly improves
studied.6,13–24 Wu's group fabricated a 128 8 1T1M crossbar the cycle-to-cycle distribution of the integrated cells.30,31
array of TiN/TaOx/HfAlyOx/TiN devices.25 Using this 1024-cell Some requirements must be satised for a series diode in the
array with parallel online training, a grey-scale face classica- passive crossbar array. A high rectication ratio, dened as the
tion is demonstrated for the rst time experimentally. The ratio between forward and reverse currents, is the most crucial
energy consumption is 1000 times less than that of the Intel one. A higher rectication ratio eliminates more sneak-path
Xeon Phi processor with off-chip memory and the accuracy on currents and allows larger passive crossbar arrays. Another
test sets is close to the result using a central processing unit. Xia performance concerned is the forward current density. Since
and Yang's groups built up a 128 64 Ta/HfO2 1T1M crossbar the forward current should be high enough to switch the series
array and used it for efficient analogue signal and image memristor, a higher forward current density allows a smaller
Fig. 4 (a) A diagram and (b) equivalent circuit of a 2 2 crossbar array containing memory elements and diodes in series, in which the sneak path
current is inhibited.
View Article Online
cell area of the diode and a higher integration density. Other
Ref.
32
33
30
31
34
35
factors such as endurance, a low temperature fabrication
4 4 2 (integrated 2 layer)
process and compatibility with CMOS technology are also
considered when approaching their commercial application.
Some recent advances of 1D1M structures, concerning param-

eters mentioned above, are summarized in Table 1.
Retention Current array size Yoon et al. reported a 1D1M crossbar memory array fabri-
The forward current density of the series diode. b The ratio is dened as the ratio between forward and reverse currents of the lowest resistance state of the 1D1M unit.
cated by physical vapor deposition methods at low tempera-
ture.32 The unit consists of a nanoporous SiOx lm and a TiO2
88
88 oxide-based diode and shows uniform and stable memory

—
—
—
performances even under mechanical deformation, while the
endurance of 300 should be optimized. The low temperature
fabrication process and exible properties allow compatibility
>105 s
>105 s
104 s
104 s
with not only conventional semiconductor processes, but also

—
exible memory applications. Using near-room-temperature

108 (D), 500 (1D1M)
physical vapor deposition methods, Kyung et al. fabricated

1D1M units with a TiO2-based Schottky diode and unipolar
300 (1D1M)
100 (1D1M)
103 (1D1M)
resistance switching TiO2.33 Based on these outstanding units

Endurance
whose rectication ratio is as high as 1.4 109, they demon-

108 (D)
strated a double-layer-stacked (4 4 2) 1D1M crossbar array,

—
conrming the possible route for the multi-stacked memory

103 (0.5 V)
103 (0.5 V)
structure.33
105 (2 V)
109 (2 V)
102 (1 V)
102 (1 V)
It is noted that the 1D1M method prefers unipolar mem-

Fabrication temperature Ratiob
ristors where the set and reset processes occur at the same
voltage polarity, because the voltage mainly drops across the
diode and hardly switches the resistance back in the bipolar one
Near room temperature
when the cell is reversely biased. Since the bipolar-type memory

Room temperature
Room temperature
is more appropriate in most neural networks where resistance

states are altered by simple voltage pulses with different voltage
polarities, diodes satisfying bipolar memristors are required.
#200 C
This makes it necessary for the diode to meet at least two

100 C
necessary requirements: (1) high forward current density and

—
low reverse current density as in a regular diode to guarantee

>104 A cm2 (2 V)
>106 A cm2 (1 V)
102 A cm2 (2 V)
104 A cm2 (2 V)
102 A cm2 (1 V)
104 A cm2 (1 V)
Current densitya
forward resistive switching and to suppress the sneak path

currents. (2) Enough reverse current density at the voltage larger
than the breakdown voltage (so called Zener voltage) to guar-
antee reverse resistive switching. When a forward voltage is
applied to update resistance state of the intended memristor,
only the middle cell in the sneak paths (D4M4 in Fig. 4) sustains
Pt/Ti-doped NiO/Pt unipolar
an ultrahigh resistance state due to the reversed series diode

and accommodates most of the applied voltage. To eliminate
Pt/Ta2O5/Pt unipolar
Pt/TiO2/Pt unipolar
Pt/HfO2/Cu bipolar
Ti/SiOx/Pt unipolar
unintended programming, the amplitude of the reverse

Al/STN/Pt bipolar
threshold voltage should be higher than the forward threshold

voltage in the integrated one diode and one bipolar memristor
Partially reported 1D1M structure
unit. Despite some advances of bipolar 1D1M devices,34,35 the

array application of 1D1M for bipolar memristors is still in its
M
early stage.
Pt/InZnOx/CuOx/Pt p–n junction
2.3 1S1M
Pt/a-IGZO/Cu Schottky
In a 1S1M array, a two-terminal selector device is connected to

Pt/n-type Si Schottky
Ni/TiO2/Ti Schottky
each memristor cell in series keeping the unit cell area of 4F2.
Pt/TiO2/Ti Schottky
Pt/TiO2/Ti Schottky
The selector is actually a bidirectional highly nonlinear resistor.

The selector and memristor can be stacked on top of each other,
giving a higher density potential than the 1T1M scheme. As
Table 1
sketched in Fig. 5a and b, the I–V curve of the 1S1M structure

shows very low current at half read (also program) voltage (high
D
View Article Online

Fig. 5(a) Schematic diagram of the bipolar Resistive-RAM (RRAM) without a selection device (left), and the corresponding I–V model (right). (b)
Schematic diagram of the bipolar RRAM with a selection device (left), and the corresponding I–V model (right) (reproduced from ref. 36,
Copyright 2011, with permission of AIP Publishing).
resistance), while the resistive switching of the memristor approaching their commercial application. Especially, the
occurs in the high voltage region.36 The nonlinearity k of an I–V endurance of a selector should be signicantly greater than that
curve is dened as k ¼ I(Vop)/I(Vop/2), where Vop is the operation of its series memristor because the selector is turned on for
voltage applied to the selected cell for reading or writing. As every programming and reading event. The tunneling
discussed in Part 1.3, during the programing/reading process in barrier37,38 and n–p–n39 or p–n–p40 junctions are commonly used
the 1S1M crossbar array, full voltage is only applied to selected in selectors. Ovonic threshold switching (OTS) behavior could
cells, while half voltage is biased on these half-selected cells for also be used to achieve high nonlinearity for oxide capacitor
the V/2 method and |V/3| is biased on half-selected and unse- devices; this requires the threshold resistive switching to occur
lected cells for the V/3 method. Thus, the nonlinear property transiently (less than 10 ns).41 Some recent advances of the
can effectively prevent the sneak effect in the 1S1M crossbar 1S1M structure, concerning parameters mentioned above, are
array. Consequently, the nonlinear I–V curve of the 1S1M unit summarized in Table 2. The following are carefully picked
can use the charge domain method when performing the VMM examples, categorized by their intrinsic physical mechanisms,
computing. in which their merits, drawbacks and opportunities are
Similar to the requirements of a series diode in Part 2.2, high discussed.
nonlinearity and large current density in the high voltage region 2.3.1 Tunneling barrier selectors. Tunneling barrier struc-
benet a large and dense crossbar array. The large current at tures have been widely utilized in Resistive-RAM (ReRAM or
high voltage is essential for the resistive switching of the series RRAM) selectors due to their intrinsic nonlinear I–V curves.
memristor, and a bigger nonlinearity of the I–V curve also Compared with single-layer barrier structures, trilayer
results in higher resistance within the low voltage region, which tunneling barriers are more attractive because of the enhanced
benets low energy consumption. Other factors such as nonlinearity.37,38 In Choi's work,38 a selector with a structure of
endurance, a low temperature fabrication process and Pt/TaN1+x/Ta2O5/TaN1+x/Pt has been proposed, where 3 nm
compatibility with CMOS technology are also considered when TaN1+x/2.5 nm Ta2O5/3 nm TaN1+x serves as a trilayer tunneling
Table 2 Partially reported 1S1M structure
Fabrication Endurance
S M Current densitya temperature Nonlinearityb of S Dynamicsc Ref.
Pt/TaN1+x/Ta2O5/TaN1+x/Pt, Pt/TaN1+x/Pt 103 A cm2 400 C 104 108 — 38

tunneling barrier
TaN/ITO/Co3O4/ITO/TaN, TaN/Al2O3/ZrO2/Al2O3/TaN 6.5 A cm2 Room 103 107 — 39
n–p–n temperature
Pt/CoOx/IGZO/CoOx/Pt, Pt/TaOx/TiN 0.1 A cm2 — 104 104 — 40
p–n–p
Ag/HfOx/Ag, OTS Pd/Ta2O5/TaOx/Pd >104 A cm2 200 C 1010 108 75 ns, 300 ns 42
TiN/Nb1xO2/Pt, OTS Cu/HfO2/Pt >106 A cm2 — 102 1012 <10 ns, <10 ns 41
W/SiTe/W, OTS — 107 A cm2 Room 105 108 2 ns, 7 ns 43
temperature
TiN/SiTe/Ag, OTS — >102 A cm2 300 C 104 105 30 ns, 5.1 ms 44
TiN/GeSe/TiN, OTS — 103 A cm2 300 C 107 105 100 ns, 300 ns 45
Ti/CuO-NW/Ti, OTS — — — 104 105 — 46
a
The highest current density of the series selector. b The nonlinearity is obtained from the selector. For the ovonic threshold switching (OTS)
selectors, this value is obtained as selectivity (Rhigh/Rlow, ratio between resistances before and aer threshold switching). c The switch speed for
the transition (up) and delay (down) in these OTS selectors.
View Article Online
and the illuminated mechanism is shown in Fig. 7b; when

a positively biased voltage is applied, the formation of the Ag
lament decreases the resistance of the selector at the threshold
voltage, leading to an abrupt increase of current. When the
voltage sweeps back, the lament rupture event occurs due to

the diffusion potential, the Nernst potential and Gibbs–Thom-
son effect. Because of the symmetry of this structure, it exhibits
similar electrical properties at reverse-biased voltage (Fig. 7c).
The ovonic threshold switching based on lament formation
and the rupture mechanism always give ultrahigh nonlinearity,
for example, 1010 in this Pd/Ag/HfOx/Ag/Pd case. Combining

this selector with a bipolar resistive device such as Pd/TaOx/
Ta2O5/Pd (Fig. 7d), the memory cell exhibits nonlinear resistive
switching with a slightly degraded nonlinearity (Fig. 7e). This
lament-based selector could exhibit an endurance of up to 108
cycles. The transition time is about 75 ns for lament formation
and 250 ns for lament rupture. The outstanding nonlinearity
and endurance behaviors in the Pd/Ag/HfOx/Ag/Pd selector are
appealing, while the mediocre transition time which may
degrade the speed of series memristors needs to be optimized.
Fig. 6 (a) I–V curves through metallic TaN and single TaN1+x layer To improve the transition time, Lv and Liu's groups designed
barriers with two different thicknesses (5 and 10 nm) and trilayer (3 nm an ovonic threshold switching selector governed by the pure
TaN1+x/2.5 nm Ta2O5/3 nm TaN1+x) barriers. (b) I–V curves through
electron transition effect.41 In their Nb1xO2 based selector, the
three trilayer devices with the thickness of each layer being 2/1/2, 3/1/
3, and 3/2.5/3 nm. The inset is in the semilog plot. (c) Schematic band threshold switching is triggered by local thermal runaway which
diagrams of the single and trilayer barrier structures (reproduced from reduces the energy barrier. There are no ions moving or phase
ref. 38, Copyright 2015, with permission of John Wiley & Sons, Inc). transitions in the threshold switching process. Consequently,
the speed of less than 10 ns and an ultra-high endurance of up
to 1012 cycles are obtained, while the nonlinearity is 500, in this
barrier. The I–V characteristics are shown in Fig. 6a and b and pure electron selector. Other pure electron OTS selectors based
the energy band diagrams are shown in Fig. 6c. The high voltage on SiTe with a transition of 2 ns and a delay of 7 ns are re-
decreases the height and effective width of the trilayer ported.43 Corresponding endurance and nonlinearity are 108
tunneling barrier simultaneously, resulting in a signicantly cycles and 105, respectively. The OTS selectors based on the
larger nonlinearity of >104 than that in a single tunneling pure electron mechanism provide a promising prospect for
barrier structure. This trilayer tunneling barrier selector is large and dense crossbar arrays.
capable of a high endurance of >108 cycles. 2.3.3 p-/n-Type semiconductor-based selectors. p-/n-Type
Despite the merits of trilayer tunneling barriers, such as oxide semiconductors are plausible to be designed as selec-
large nonlinearity and high endurance, tunnel selectors are tors with good uniformity performance because of the mature
promising due to the following reasons: the nonlinearity results controllability of lattice mismatch and doping proles of p–n
from the intrinsic physical mechanisms, which are well hetero-junctions. Bae et al. reported a selector entirely based on
understood and reproduced by accurate mathematical oxide semiconductor p–n–p junctions with a structure of p-
modeling. The intrinsic abrupt high currents don't need assis- CoOx/n-IGZO/p-CoOx (ref. 40) (Fig. 8a). Unlike conventional
tance of Joule heating, and are independent of temperature. bipolar transistors connecting all three terminals (i.e. emitter,
These characteristics benet low energy consumption and wide base and collector electrodes), this device is open-based and is
available temperature windows. Furthermore, tunnel selectors used as a two-terminal selector. Fig. 8d shows the schematic
possess the advantages of intrinsic speed and reproducibility of band diagram of the device. At zero or low bias voltage, the
their I–V curves. One of the challenges is that fabricating high- whole device is analogous to two anti-connected diodes, which
quality ultrathin lms usually needs a high temperature leads to a suppressed current density. However, when a larger
process.47,48 High-quality tunnel selectors processed at room voltage (>threshold voltage) is applied, the top of the valence
temperature, such as organic tunneling junctions,49 are under band of the collector exceeds the bottom of the conduction
explored. band of the base, enabling a large number of electrons to inject
2.3.2 OTS selectors. The OTS is known to be fast, instan- into the base from the collector. Therefore, the current rapidly
taneous, abrupt, volatile, repeatable and eld-dependent. Thus, increases at this point resulting in a nonlinearity of 104. Because
OTS devices are extensively used as selectors.41–46 Midya et al. of the symmetry of the device, the I–V curves (Fig. 8b) are highly
reported an OTS selector based on metal lament formation symmetric at both voltage polarities. Finally, as shown by the I–
and the rupture mechanism.42 The structure is composed of Pd/ V curves in Fig. 8c, by combining this selector, the Pt/TaOx/TiN
Ag/HfOx/Ag/Pd (Fig. 7a). Fig. 7c shows the nonlinear I–V curves structure presents excellent nonlinear resistive switching
behavior.
View Article Online

Fig. 7 (a) Structure of the integrated 1S-1R device consisting of a Pd/Ta2O5/TaOx/Pd memristor and a Pd/Ag/HfOx/Ag/Pd selector highlighted by
SEM and cross-sectional TEM techniques. (b) Schematic diagram of the filament during the threshold switching process. (c) Repeatable bidi-
rectional threshold switching of the individual Pd/Ag/HfOx/Ag/Pd selector. (d) Repeatable bipolar resistive switching of the individual Pd/Ta2O5/
TaOx/Pd memristor. (e) Repeatable nonlinear resistive switching of integration of the selector and memristor (reproduced from ref. 42, Copyright
2017, with permission of John Wiley & Sons, Inc).
Similarly, a highly nonlinear n–p–n selector is also re- 3.1 Self-selective memristors
ported.39 One resistor device connecting the proposed n–p–n
Self-selective memristors exhibit self-nonlinear I–V character-
selector demonstrates a high nonlinearity of 103, excellent
istics as the overall feature of 1S1T. Recently, various self-
endurance of 107 cycles, fast switching speed (60 ns), and stable
selective devices have been realized. Most devices have a bi-
retention (104 s) at 100 C.39 The successful operation of the p–
layer structure, but based on different physical mechanisms.
n–p or n–p–n selector and one memristor with the 1S1R archi-
The following are some typical examples categorized by
tecture contributes a new route for advancing crossbar arrays.
mechanisms.
One of the challenges is the low current density in the p–n–p 3.1.1 Interface phase transition. Huang et al. reported
and n–p–n structures, which hinders a high-density crossbar a self-selective device with a Pt/TiO2/uorine-doped tin oxide
array.
(FTO) structure.50 Fig. 9a shows the nonlinear resistive
switching I–V curves with a nonlinearity of 10 in the device.
The resistive switching is attributed to metallic laments
3. Single-device memory cell formed by oxygen vacancy driing, while the nonlinearity in
the device was attributed to a gradual transition of the sub-
structure
oxide phase in the TiO2x suboxide region near FTO elec-
A single memristor device with either self-nonlinear or self- trodes. As schematized in Fig. 9b–e, the as-deposited device
rectifying I–V characteristics could suppress the sneak path undergoes a formation process, where abundant heat
currents without other assistant cells in a crossbar array, and is generated by Joule heating facilitates the oxidation of TiO2.
a great improvement to simplify the memory cell, which reduces Because the nanorods grow from bottom to top, the diameter
the cost, and benets highly integrated crossbar arrays. By of the nanorods near the top electrode is smaller than that at
listing necessary parameters as in 1D1T and 1S1T structures, the bottom electrode, increasing the porosity of TiO2 nano-
recent advances of these single-device memristors used in rods near the top electrode, which facilitates the top side to
crossbar arrays are summarized in Table 3. The following is absorb more O2. Consequently, the top layer becomes an
a careful introduction separated as self-selective memristors oxygen-rich region (TiO2), while the bottom layer is oxygen-
and self-rectifying memristors. decient suboxide (TiO2x). Numbers of non-stoichiometric
View Article Online

Fig. 8 (a) High-resolution EDS (HR-EDS) elemental line profile across a line of the STEM image, where the inset shows a dark-field STEM image
of the Pt/CoOx/IGZO/CoOx/Pt frame. (b and c) I–V curves of a CoOx/IGZO/CoOx selector (b) and electrical connection unit containing both the
Pt/CoOx/IGZO/CoOx/Pt selector and Pt/TaOx/TiN memristor (c). (d) Schematic band diagram of the device p(emitter)–n(base)–p(collector)
under zero (low) and high (above threshold) voltage bias, respectively (reproduced from ref. 40, Copyright 2015, with permission of Springer
Nature).
Ti suboxides (TinO2n1, the so-called Magnéli phase), insulator. Some other materials, such as VOx,65 are also re-
including Ti2O3, Ti3O5, Ti4O7, Ti5O9,64 have been shown to ported to display self-selective resistive switching
demonstrate the gradual transition from the metal to the performance.
Table 3 Partially reported single-device memristors used in crossbar arrays
Structure Mechanismsa Fabrication temperature Nonlinearity or ratiob Endurance Retention Ref.
Pt/TiO2-NRs/FTO, self-selective Interface phase transition 350 C 10 — 103 s 50

W/WO3/WOx/W, self-selective Tunneling barrier 500 C 8.8 — 103 s 51
Pd/TaOx/HfO2/Pd, self-selective Tunneling barrier 300 C 103 — — 52
TiN/HfO2/TaOx/Ti, self-selective Tunneling barrier — 102 107 104 s 53
TiN/HfO2/TiOx/Ru, self-selective Tunneling barrier — 103 107 104 s 54
Au/h-BN/G/h-BN/Ag, self-selective Volatile Ag lament 120 C 1010 106 106 s 55
Pt/Ta2O5/HfO2x/TiN, self-rectifying Schottky barrier 280 C 103 103 104 s 56
Pt/TiO2/HfO2x/TiN, self-rectifying Schottky barrier 280 C 103 103 106 s 57
Pt/TaOy/NP TaOx/Ta, self-rectifying Schottky barrier — 104 103 104 s 58
Pt/C/NbOx/TiN, self-rectifying Asymmetric potential barrier Room temperature 106 — — 59
Pt/HfO2/n+-Si, self-rectifying Asymmetric potential barrier 300 C 105 103 104 s 60
Pt/NbOx/TiOy/NbOx/TiN, self-rectifying Asymmetric potential barrier 300 C 105 103 103 s 61
Al/Cu-pMSSQ/Al, self-rectifying Asymmetric potential barrier 160 C 102 — — 62
p-Si/SiO2/n-Si, self-rectifying Asymmetric potential barrier 400 C 105 — 105 s 63
a
The mechanism of self-nonlinear or self-rectifying memristors. b The nonlinearity is for self-selective memristors and the ratio is for self-rectifying
memristors.
View Article Online

Fig. 9 (a) Nonlinear I–V curves of the Pt/TiO2 NRs/FTO device. (b–e) Schematics of the nonlinear resistive switching mechanism. Four states: (b)
the original state, (c) after the formation process, (d and e) back and forth switching between the set process and the reset process (reproduced
from ref. 50, Copyright 2017, with permission of Springer Nature).
Fig. 10 (a) Schematic diagram of a W/WO3/WOx/W resistive switching memory device. (b) I–V curves of the device. (c and d) Schematic diagram
of the oxygen-vacancy filament of the device at both LRS and HRS (c) and the corresponding energy band diagram (d) (reproduced from ref. 51,
Copyright 2016, with permission of Springer Nature).
3.1.2 Tunneling barrier. Stimulated by the nonlinearity of dominates the current. These tunneling and thermionic emission
the tunneling barrier, the device adding a tunneling barrier in mechanisms give the nonlinear conductance behavior (Fig. 11c).
their structure is proposed as a self-selective one. Chakrabarti Replacing Ta by HfO2 as the switching layer, the unit shows
et al. reported a self-selective device with a W/WO3/WOx/W a nonlinear resistive switching and the I–V curves agree well with
structure51 (Fig. 10a). Fig. 10c shows the schematic diagram of the the simulation based on these aforementioned mechanisms
resistive lament for the low resistance state (LRS) and high (Fig. 11d). This integrated device shows a high nonlinearity (5
resistance state (HRS), respectively. Due to the gap barrier near the 103) in the low resistance state and could be considered as a self-
top electrode (TE), the Fowler–Nordheim (F–N) tunneling (Fig. 10d) selective memristor device.
under high bias gives the nonlinearity of the I–V curves. The I–V By designing a bilayer structure of HfO2/TaOx, where the
curves present nonlinear resistive switching (Fig. 10b). Wang et al. HfO2 layer plays the role of the tunneling barrier53, Lv and Liu's
demonstrated nonlinear I–V curves in the Pd/TaOx/Ta/Pd junction groups realized self-selective resistive devices with outstanding
(Fig. 11a), whose conductance mechanism arises from tunneling properties, including high nonlinearity (>102) and high endur-
or thermionic emission.52 The energy band diagram is shown in ance (>107). Interestingly, based on these self-selective resistive
Fig. 11b. Under positively biased voltage, both tunneling and devices, an 8-layer 3D vertical RRAM architecture with 5 nm size
thermionic electron emission contribute to the current. At and 4 nm vertical pitch was demonstrated. Bayat et al. designed
reversely biased voltage, only the tunneling electron transport a Pt/Al2O3/TiO2x/Ti/Pt memristor whose nonlinearity arises
View Article Online

Fig. 11 (a) The high resolution cross-sectional TEM image of a Pd/TaOx/Ta/Pd device. (b) Schematic diagrams of the band diagram of the Pd/
TaOx/Ta/Pd tunneling junction under positive and negative bias. (c) I–V curves of the Pd/TaOx/Ta/Pd device at different temperatures from 150 K
to 300 K. (d) I–V curves of the Pd/TaOx/HfO2/Pd device, the red lines represent the simulation using fixed values of Ron ¼ 4 105 U and Roff ¼ 1
107 U (reproduced from ref. 52, Copyright 2015, with permission of Royal Society of Chemistry).
from the alumina tunneling barrier.66 Passive 20 20 crossbar 3.2 Self-rectifying memristor
arrays based on this nonlinear memristor were fabricated, in
In contrast to selector-less memristors whose I–V curves are
which leakage currents are sufficiently suppressed. Assisted by
nonlinear, self-rectifying memristors are single-stack devices
ex situ training, these passive 20 20 crossbar arrays achieve
where reverse current is extremely small. Therefore, self-
classication delity within 3% of that obtained in rectifying memristors resemble bipolar 1D1M structures.
simulations66. Thus, as discussed in Part 2.2, to eliminate the unintended
3.1.3 Volatile lament in van der Waals heterostructure.
programming, the amplitude of the reverse threshold voltage
Sun et al. proposed a self-selective memory cell based on the Au/
should be higher than that of the forward threshold voltage in
h-BN/G/h-BN/Ag van der Waals heterostructure (Fig. 12a),55
self-rectifying memristors. The self-rectifying property mostly
where h-BN and G are hexagonal boron nitride and graphene
originates from the asymmetric barrier due to the Schottky
respectively. Non-volatile boron vacancy laments and volatile
contact or asymmetric potential in the devices, while various
silver laments are formed in Au/h-BN/G and G/h-BN/Ag
mechanisms contribute to these memristive behaviors. The
structures, respectively. In the cell integrating the non-volatile following are some typical examples.
and volatile structures together, the graphene layer efficiently 3.2.1 Self-rectifying memristors based on poly(-
blocks the diffusion of volatile silver laments (Fig. 12c),
methylsilsesquioxane) (PMSSQ). Wu et al. reported a well-
resulting in a highly nonlinear resistive switching with a self-
designed exible structure where copper (Cu) ions are non-
selectivity of 1010 and an on/off resistance ratio of more than
uniformly doped into a PMSSQ polymer.62 PMSSQ is a hole-
103 (Fig. 12b). Based on these self-selective memory cells, a 12
injection material.67 In Wu's work, ultraviolet-visible absorp-
12 crossbar array is demonstrated. Due to the high self-
tion spectra conrmed that the energy gap decreases with
selectivity of 1010, a code of “SKKU” was successfully pro-
increasing Cu concentration. As shown in Fig. 13a, the device
grammed using 144 binary bits for four letters (SKKU) in their has a structure of Al/lightly-doped layer/highly-doped layer/Al.
12 12 crossbar array.55 Taking into account the on-the-way The schematic energy band diagrams under positive and
wafer ability of 2D materials, efficient crossbar arrays using
negative biases are also shown. The currents here are domi-
van der Waals heterostructures on exible substrates are
nated by the contact barrier using positive bias. When positive
expectable.
bias is applied to the device, the contact barrier under positive
bias (pre-electrode side) is small, and holes tunnel into the
View Article Online

Fig. 12 (a) Schematic of the Au/h-BN/G/h-BN/Ag van der Waals heterostructure in the crossbar array architecture. (b) I–V curves of an Au/h-BN/
G/h-BN/Ag memory cell in the crossbar array. (c) Schematic pictures of the Au/h-BN/G/h-BN/Ag memory cell for the four states in (b). States “1”
and “3” represent the high-resistance state and low-resistance state of unselected cells, respectively. States “2” and “4” represent the high-
resistance state and low-resistance state of a selected memory cell, respectively. A complete conductive silver filament is formed in state “2” and
state “4”. A complete conductive boron vacancy filament is formed in state “3” and state “4”. The gray, purple, blue, yellow and white spheres
represent silver, hexagonal boron nitride, graphene, gold and boron vacancies, respectively (reproduced from ref. 55, Copyright 2019, with
permission of Springer Nature).
Fig. 13 (a) Schematic diagram and band structure of the sandwiched structure of Al (bottom electrode)/lightly doped layer/highly doped layer/Al
(top electrode), and the kinetic model of carrier transportation under both polarization of voltage bias. (b) I–V curves under consecutive positive
bias sweeps. (c) I–V curves under consecutive positive bias sweeps after the positive bias sweeps (reproduced from ref. 62, Copyright 2017, with
permission of Springer Nature).
View Article Online

Fig. 14 (a) Cross-sectional TEM image of the Si/SiO2/Si device shows a single crystalline structure for the top and bottom electrodes and the
5 nm amorphous SiO2 switching layer. Scale bar, 2 nm. (b) A typical unipolar resistive switching I–V curve of the Si/SiO2/Si device. The n-Si
bottom electrode was grounded while the bias was applied to the p-Si top electrode. (c) The band diagram in LRS under a forward bias describes
a piece of non-degenerated silicon bridge between two degenerate silicon electrodes. The excess holes flow from the p-type electrode to the n-
type electrode while the electrons flow from the n-type electrode to the p-type electrode (reproduced from ref. 63, Copyright 2017, with
permission of Nature Publishing Group).
PMSSQ (F–N tunneling), leading to a large current. Simulta- conrmed in 3D crossbar arrays made of these all-silicon-based
neously, copper ions are dried away from the pre-electrode, memristors. The fabrication of such a device is highly
increasing the barrier height and decreasing the conductance. compatible with the current CMOS process, which indicates its
As shown in Fig. 13b, the current is relatively large under the practical suitability.
rst forward voltage sweeping and gradually dwindles under 3.2.3 Charge-trap-associated self-rectifying memristor.
repeated forward voltage sweepings. When negative bias is Generally, electron effect-based resistive devices show highly
applied to the device, the contact barrier under positive bias uniform switching performances. By inducing a Schottky
(post-electrode side) is big, holes inject into the PMSSQ with contact or asymmetric electrodes (asymmetric potential barrier
a thermionic emission mechanism, and the current is small in the device) into an electron trapping/detrapping system,
(Fig. 13c). It is noted that the conductance increases (under a charge-trap-associated self-rectifying memristor is
positive read voltage) while the currents decrease with these obtained.56,57
repeated negative voltage sweepings. The switching of Kim et al. designed a low-current and self-rectifying Pt/NbOx/
tunneling and thermionic emission mechanisms between TiOy/NbOx/TiN device61 (Fig. 15a), where the memristive
positive and negative biases leads to the self-rectifying property behavior is attributed to the electron trapping/detrapping
of this single-device memristor with a rectifying ratio of 100. process while the asymmetric potential barriers induce a self-
Meanwhile, the driing of Cu ions under an applied eld rectifying ratio of 105. The schematic energy band diagram
enables multi-level states of the device. This unique I–V char- of the device is shown in Fig. 15b; a trap energy as deep as 0.8 eV
acteristic facilitates its application in neuromorphic networks. is formed in the TiOy layer. The as-deposited devices experi-
Three-dimensional (3D) device networks based on this exible enced a 300 C atmosphere during the fabrication process,
structure are successfully realized, which shows the feasibility which facilitates the trap sites to be lled with electrons. The I–V
of using them in future electronic devices involving hierarchical curves are shown in Fig. 15a, and the corresponding evolution
neural networks.62 of energy diagrams is shown in Fig. 15c. As mentioned above,
3.2.2 All-silicon-based self-rectifying memristor. Li et al. electrons are trapped in the trap sites initially. These electrons
reported an all-silicon-based memristor with a structure of p-Si/ attract positive charges to accumulate at the interface of the
SiO2/n-Si63 (Fig. 14a). A conducting channel made of a non- electrodes, leading to a built-in electric eld pointing toward
degenerate semiconductor is formed between the top p and the trap sites. Under this circumstance, the whole barrier height
bottom n silicon, and the energy band diagram is shown in increases, giving a high resistive state (HRS). When positively
Fig. 14c. This all-silicon-based memristor shows a repeatable biased voltage is applied, the Fermi level of the Pt electrode is
unipolar resistive switching behavior with a rectifying ratio of pulled down, and electrons are released to the Pt electrode. This
105 and ON/OFF ratio of 104 (Fig. 14b), which effectively detrapping process leads the device to the low resistive state
suppresses the sneak-path current and enables larger array (LRS). There can also be a trapping process from the TiN elec-
operations without discrete selectors. Suppression of both trode to the trap sites, which is much weaker than the detrap-
intra- and inter-layer sneak-path currents is experimentally ping process because of the longer tunneling distance between
View Article Online

Fig. 15 (a) I–V curves of the Pt/NbOx/TiOy/NbOx/TiN device. Inset shows the structure of the device and the test setup for the measurement. (b)
The energy band diagram of the device. (c) Diagram of the charge capture and decapture process in the device. (i) The HRS, electrons fill the trap
sites. (ii and iii) A positive set bias is applied on the Pt electrode, (iv) LRS, the trapped electrons can be released. (v and vi) A negative reset bias is
applied, and the HRS is restored (adapted from ref. 61, Copyright 2016, with permission of American Chemical Society).
the TiN and trap sites. Similarly, the memristor is switched back There are also other self-rectifying memristors associating
to the HRS when the negatively biased voltage sweeps. memristive mechanisms such as interaction of composition
Wang et al. designed a synaptic memory of Pt/C/NbOx/TiN.59 dependent thermal conductivity and oxygen-ion migra-
The charge trapping and detrapping in the NbOx lm dominate tion,58,68–70 electron tunneling controlled by ferroelectric
the resistive switching. The inserted C layer plays a role of surfaces,71,72 and interfacial trap site engineering.73 Most re-
forming an asymmetric potential barrier in the device, resulting ported self-rectifying memristors do not show an abrupt
in a self-rectifying ratio of 106. The high self-rectifying ratio of increase and decrease of conductance. These properties indi-
106 effectively eliminates sneak path currents, and thus the cate that self-rectifying memristors have great potential appli-
conductance in a crossbar array can be efficiently programed. cation for neuromorphic networks. However, most reported
Excellent classication accuracy (95.7%) of handwritten digits is self-rectifying memristors suffer from an important issue of
achieved by a simulation of two-layer perceptron neural poor endurance (Table 3). This may be due to the fact that
networks based on these self-rectifying Pt/C/NbOx/TiN devices. a high barrier is usually induced to achieve self-rectication,
which inevitably needs a higher voltage operation for
View Article Online
programing the states. Reducing the syndrome of high voltage series diode has been continuously increased. The application
needs to be explored. of this solution is not only subject to unipolar memristors but
extends to bipolar devices. The TiO2-based Schottky diode with
4. Perspectives a rectication ratio as high as 1.4 109 and an endurance of 108
cycles is very promising for application in large crossbar arrays.

Memristors are new non-volatile electronic memory devices As for 1S1M, to reduce the energy consumption and improve
with programmable resistance that has enormous potential the performance of programming and reading of the cells in
application in tomorrow's electronics. One of the appealing large-scale arrays, selector devices with high nonlinearity must
aspects is that memristor crossbar arrays can be an ideal be created. Nonlinear selectors based on the tunneling barrier,
candidate for hardware neuromorphic networks. The mem- OTS and p-/n-combination have been vastly researched in these
ristor crossbar array can implement algorithms more efficiently 3 years. The nonlinearity of tunneling barrier selectors results
with much lower power consumption. However, to realize this from the intrinsic physical mechanism. The abrupt high
attractive prospect, the sneak-path current issue must be over- currents don't need assistance of Joule heating, and are inde-
come. Thanks to the efforts of researchers in the academic pendent of temperature, which benets low energy consump-
domain over the years, quite a number of solutions have been tion and wide available temperature windows. The tunnel
proposed to solve this sneak-path problem, and each specic selectors also possess excellent speed and reproducibility. One
category of solutions has been developed at a more and more of the drawbacks is the high temperature fabrication process,
sophisticated level, which improves the possibility for real limiting its further integrating. Low temperature tunneling
applications. barrier selectors need to be explored. The biggest stumbling
As a matter of fact, a potential solution is the 1T1M structure. block for p–n–p and n–p–n selectors is the low current density,
Due to its high compatibility with the CMOS process, 1T1M has which needs a large cell area to switch the accompanied
become the most practical approach. The transistor in this memristor and hinders a high-density crossbar array. The
structure could precisely manipulate the ON/OFF state of the outstanding nonlinearity and endurance behaviors in ion-based
cell, which mitigates the sneak path currents and half-select OTS selectors are appealing. But the dynamics of ions is slower
issues during array programming and reading. Moreover, the compared with electrons; electron-based OTS selectors usually
gate voltage could provide controllability of the synaptic weight possess a transition time less than 10 ns, and are also capable of
by regulating the limit resistance of the cell, which is signicant high endurance, such as an ultrahigh endurance of 1012 in
for application in neuromorphic networks, such as, by offering Nb1xO2 based and 108 in SiTe based selectors. OTS selectors
compliance currents, the gate lines in the 1T1M crossbar array based on the pure electron mechanism are promising for large
assist in obtaining the linear and symmetric conductance and dense crossbar arrays.
increase and decrease with minimal cycle-to-cycle and device- Self-selective and self-rectifying memristors show great
to-device variations, which is favorable for time-efficient potential for solving the sneak-path current issue with a simple
current domain VMM computing. structure. These two aforementioned solutions using a single
However, 1T1M has a cell area of 8F2, which is relatively large device instead of two move a step further in down-scaling
and limits the scaling of the array and integration density. To (including the cost). Self-rectifying memristors usually suffer
minimize as much as possible the scaling issue, a high channel from poor endurance due to the high voltage operation. Self-
conductance of transistors is preferred. Despite the large cell nonlinear selectors based on either CMOS-compatible oxides
area, CMOS transistors take advantage of their sophisticated or van der Waals Materials are promising for huge and dense
fabrication techniques and scalability, whereby vast 1T1M crossbar arrays. One note is recalled that VMM computation in
crossbar arrays are fabricated and demonstrated to perform 1S1M or single-device memristor crossbar arrays is limited to
well in various complicated information processing operations. the charge domain method (by modulating the pulse width or
In a passive array, which has a cell area of 4F2, a much higher number) due to the nonlinear I–V curves.
packing density and 3D stackability are achieved. On the other In short, this fast-growing eld of research is still in its
hand, it suffers from half-select issues, resulting in large energy infancy and we hope this overview concerning the sneak-path
consumption during the programming and reading of the cells current problem will benet the eld and arouse the curiosity
in large-scale arrays. To overcome this issue, a high rectication and inventiveness of researchers and engineers from chemistry,
ratio or nonlinearity must be induced to memristors by con- physics, materials science, electronics and computing science.
necting a series diode or nonlinear selector or by itself. The
series diode or nonlinear selector doesn't increase footpoints, Conflicts of interest
thus sustaining the advantage of high packing density and
stackability. There are no conicts to declare.
For the 1D1M structure, a higher rectication ratio and
bigger forward current density allow larger and denser crossbar Acknowledgements
arrays. The series diode also acts as an external load resistor to
suppress the overow current during the resistance transition, This work was nancially supported by the National Natural
which signicantly improves the cycle-to-cycle distribution of Science Foundation of China (61804055), the “Chenguang
the integrated cells. Recently, the forward/reverse ratio of the Program” supported by the Shanghai Education Development
View Article Online
Foundation and the Shanghai Municipal Education Commis- 18 C.-X. Xue, W.-H. Chen, J.-S. Liu, J.-F. Li, W.-Y. Lin, W.-E. Lin,
sion (17CG24), the Postdoctoral Science Foundation of China J.-H. Wang, W.-C. Wei, T.-W. Chang, T.-C. Chang,
(2017M611501), the Shanghai Science and Technology Innova- T.-Y. Huang, H.-Y. Kao, S.-Y. Wei, Y.-C. Chiu, C.-Y. Lee,
tion Action Plan (19JC1416700), and the Shanghai Sailing C.-C. Lo, Y.-C. King, C.-J. Lin, R.-S. Liu, C.-C. Hsieh,
Program (17YF1404200). K.-T. Tang and M.-F. Chang, IEEE International Solid-State
Circuits Conference (ISSCC), 2019, vol. 24.1, p. 388.
19 Y. Zhou, H. Wu, B. Gao, W. Wu, Y. Xi, P. Yao, S. Zhang,
Notes and references Q. Zhang and H. Qian, Adv. Funct. Mater., 2019, 29, 1900155.
20 H. Tsai, S. Ambrogio, C. Mackin, P. Narayanan, R. M. Shelby,
1 G. W. Burr, R. M. Shelby, A. Sebastian, S. Kim, S. Kim, K. Rocki, A. Chen and G. W. Burr, Symposium on VLSI
S. Sidler, K. Virwani, M. Ishii, P. Narayanan, A. Fumarola, Technology Digest of Technical Papers, 2019, vol. T82.
L. L. Sanches, I. Boybat, M. Le Gallo, K. Moon, J. Woo, 21 C.-H. Wang, C. McClellan, Y. Shi, X. Zheng, V. Chen,
H. Hwang and Y. Leblebici, Adv. Phys.: X, 2016, 2, 89–124. M. Lanza, E. Pop and H.-S. P. Wong, IEEE International
2 B. Hudec, C.-W. Hsu, I. T. Wang, W.-L. Lai, C.-C. Chang, Electron Devices Meeting (IEDM), 2018, vol. 18, p. 528.
T. Wang, K. Fröhlich, C.-H. Ho, C.-H. Lin and T.-H. Hou, 22 Y. Zhang, Z. Zhou, P. Huang, M. Fan, R. Han, W. Shen,
Sci. China Inf. Sci., 2016, 59, 061403. L. Liu, X. Liu and J. Kang, Silicon Nanoelectronics Workshop
3 S. Gi, I. Yeo, M. Chu, S. Kim and B. Lee, International SoC (SNW), 2019.
Design Conference (ISOCC), 2015, p. 215. 23 C. Mohan, L. A. Camuñas-Mesa, E. Vianello, L. Periniolla,
4 F. Pan, S. Gao, C. Chen, C. Song and F. Zeng, Mater. Sci. Eng., C. Reita, J. M. de la Rosa, T. Serrano-Gotarredona and
R, 2014, 83, 1–59. B. Linares-Barranco, Microelectron. Eng., 2018, 198, 35–47.
5 J. Y. Seok, S. J. Song, J. H. Yoon, K. J. Yoon, T. H. Park, 24 H.-X. Zheng, Y.-C. Zhang, X.-H. Ma, Y. Hao, S. M. Sze,
D. E. Kwon, H. Lim, G. H. Kim, D. S. Jeong and M.-C. Chen, T.-C. Chang, Y.-T. Su, W.-C. Chen,
C. S. Hwang, Adv. Funct. Mater., 2014, 24, 5316–5339. W.-C. Huang, P.-Y. Wu, Y.-F. Tan and Y.-L. Xu, IEEE Trans.
6 M. Hu, C. E. Graves, C. Li, Y. Li, N. Ge, E. Montgomery, Electron Devices, 2019, 66, 4706–4709.
N. Davila, H. Jiang, R. S. Williams, J. J. Yang, Q. Xia and 25 P. Yao, H. Wu, B. Gao, S. B. Eryilmaz, X. Huang, W. Zhang,
J. P. Strachan, Adv. Mater., 2018, 30, 1705914. Q. Zhang, N. Deng, L. Shi, H. P. Wong and H. Qian, Nat.
7 F. Cai, J. M. Correll, S. H. Lee, Y. Lim, V. Bothra, Z. Zhang, Commun., 2017, 8, 15199.
M. P. Flynn and W. D. Lu, Nat. Electron., 2019, 2, 290–299. 26 C. Li, M. Hu, Y. Li, H. Jiang, N. Ge, E. Montgomery, J. Zhang,
8 H. Jiang, K. Yamada, Z. Ren, T. Kwok, F. Luo, Q. Yang, X. Zhang, W. Song, N. Dávila, C. E. Graves, Z. Li, J. P. Strachan, P. Lin,
J. J. Yang, Q. Xia, Y. Chen, H. Li, Q. Wu and M. Barnell, IEEE Z. Wang, M. Barnell, Q. Wu, R. S. Williams, J. J. Yang and
International Symposium on Circuits and Systems (ISCAS), 2018. Q. Xia, Nat. Electron., 2017, 1, 52–59.
9 Q. Xia and J. J. Yang, Nat. Mater., 2019, 18, 309–323. 27 C. Li, Z. Wang, M. Rao, D. Belkin, W. Song, H. Jiang, P. Yan,
10 Y. Chen, G.-Y. Jung, D. A. A. Ohlberg, X. Li, D. R. Stewart, Y. Li, P. Lin, M. Hu, N. Ge, J. P. Strachan, M. Barnell, Q. Wu,
J. O. Jeppesen, K. A. Nielsen, J. F. Stoddart and R. S. Williams, J. J. Yang and Q. Xia, Nature Machine
R. S. Williams, Nanotechnology, 2003, 14, 462–468. Intelligence, 2019, 1, 49–57.
11 Y.-C. Chen, C. F. Chen, C. T. Chen, J. Y. Yu, S. Wu, S. L. Lung, 28 Z. Wang, C. Li, P. Lin, M. Rao, Y. Nie, W. Song, Q. Qiu, Y. Li,
R. Liu and C.-Y. Lu, IEEE International Electron Devices P. Yan, J. P. Strachan, N. Ge, N. McDonald, Q. Wu, M. Hu,
Meeting (IEDM), 2003, vol. 03, p. 905. H. Wu, R. S. Williams, Q. Xia and J. J. Yang, Nature
12 A. Ciprut and E. G. Friedman, IEEE Transactions on Very Large Machine Intelligence, 2019, 1, 434–442.
Scale Integration (VLSI) Systems, 2018, 26, 711–719. 29 P. Yao, H. Wu, B. Gao, J. Tang, Q. Zhang, W. Zhang, J. J. Yang
13 C. Li, D. Belkin, Y. Li, P. Yan, M. Hu, N. Ge, H. Jiang, and H. Qian, Nature, 2020, 577, 641–646.
E. Montgomery, P. Lin, Z. Wang, W. Song, J. P. Strachan, 30 M. Song, H. Lee, D. H. Seo, H.-J. Lee, J.-S. Kim, H.-S. Cho,
M. Barnell, Q. Wu, R. S. Williams, J. J. Yang and Q. Xia, H.-K. Lyu, S. Seo and M.-J. Lee, IEEE J. Electron Devices Soc.,
Nat. Commun., 2018, 9, 2385. 2018, 6, 905–909.
14 S. Yu, Z. Li, P.-Y. Chen, H. Wu, B. Gao, D. Wang, W. Wu and 31 D. K. Lee, G. H. Kim, H. Sohn and M. K. Yang, Appl. Phys.
H. Qian, IEEE International Electron Devices Meeting (IEDM), Lett., 2019, 115, 263502.
2016, vol. 16, p. 416. 32 J. Yoon, Y. Ji, S.-K. Lee, J. Hyon and J. M. Tour, Adv. Electron.
15 R. Mochida, K. Kouno, Y. Hayata, M. Nakayama, T. Ono, Mater., 2018, 4, 1700665.
H. Suwa, R. Yasuhara, K. Katayama, T. Mikawa and 33 K. J. Yoon, G. H. Kim, S. Yoo, W. Bae, J. H. Yoon, T. H. Park,
Y. Gohou, Symposium on VLSI Technology Digest of Technical D. E. Kwon, Y. J. Kwon, H. J. Kim, Y. M. Kim and C. S. Hwang,
Papers, 2018, p. 175. Adv. Electron. Mater., 2017, 3, 1700152.
16 S. Ambrogio, P. Narayanan, H. Tsai, R. M. Shelby, I. Boybat, 34 Q. Wu, G. Yang, C. Lu, G. Xu, J. Wang, B. Dang, Y. Gong,
C. di Nolfo, S. Sidler, M. Giordano, M. Bodini, X. Shi, X. Chuai, N. Lu, D. Geng, H. Wang, L. Li and
N. C. P. Farinha, B. Killeen, C. Cheng, Y. Jaoudi and M. Liu, IEEE Trans. Electron Devices, 2019, 66, 9.
G. W. Burr, Nature, 2018, 558, 60–67. 35 K.-J. Lee, Y.-C. Chang, C.-J. Lee and Y.-H. Wang, Vacuum,
17 Y. Shi, L. Nguyen, S. Oh, X. Liu, F. Koushan, J. R. Jameson 2017, 140, 35–41.
and D. Kuzum, Nat. Commun., 2018, 9, 5312.
View Article Online
36 J. Shin, I. Kim, K. P. Biju, M. Jo, J. Park, J. Lee, S. Jung, W. Lee, 55 L. Sun, Y. Zhang, G. Han, G. Hwang, J. Jiang, B. Joo,
S. Kim, S. Park and H. Hwang, J. Appl. Phys., 2011, 109, K. Watanabe, T. Taniguchi, Y. M. Kim, W. J. Yu,
033712. B. S. Kong, R. Zhao and H. Yang, Nat. Commun., 2019, 10,
37 M. Wang, X. Lian, Y. Pan, J. Zeng, C. Wang, E. Liu, B. Wang, 3161.
J. J. Yang, F. Miao and D. Xing, Appl. Phys. A: Mater. Sci. 56 J. H. Yoon, S. Yoo, S. J. Song, K. J. Yoon, D. E. Kwon,
Process., 2015, 120, 403–407. Y. J. Kwon, T. H. Park, H. J. Kim, X. L. Shao, Y. Kim and
38 B. J. Choi, J. Zhang, K. Norris, G. Gibson, K. M. Kim, C. S. Hwang, ACS Appl. Mater. Interfaces, 2016, 8, 18215–
W. Jackson, M. X. Zhang, Z. Li, J. J. Yang and 18221.
R. S. Williams, Adv. Mater., 2016, 28, 356–362. 57 J. H. Yoon, D. E. Kwon, Y. Kim, Y. J. Kwon, K. J. Yoon,
39 D. Kumar, R. Aluguri, U. Chand and T.-Y. Tseng, IEEE Trans. T. H. Park, X. L. Shao and C. S. Hwang, Nanoscale, 2017, 9,
Electron Devices, 2019, 66, 1296–1301. 11920–11928.

40 Y. C. Bae, A. R. Lee, G. H. Baek, J. B. Chung, T. Y. Kim, 58 S. Choi, S. Jang, J.-H. Moon, J. C. Kim, H. Y. Jeong, P. Jang,
J. G. Park and J. P. Hong, Sci. Rep., 2015, 5, 13362. K.-J. Lee and G. Wang, NPG Asia Mater., 2018, 10, 1097–1106.
41 Q. Luo, J. Yu, X. Zhang, K.-H. Xue, J.-H. Yuan, Y. Cheng, 59 W. Wang, R. Wang, T. Shi, J. Wei, R. Cao, X. Zhao, Z. Wu,
T. Gong, H. Lv, X. Xu, P. Yuan, J. Yin, L. Tai, S. Long, X. Zhang, J. Lu, H. Xu, Q. Li, Q. Liu and M. Liu, IEEE
Q. Liu, X. Miao, J. Li and M. Liu, Symposium on VLSI Electron Device Lett., 2019, 40, 1407–1410.
Technology Digest of Technical Papers, 2019, vol. T236. 60 X. Zhang, H. Ji and R. Jiang, IEEE Trans. Electron Devices,
42 R. Midya, Z. Wang, J. Zhang, S. E. Savel'ev, C. Li, M. Rao, 2019, 66, 3337–3341.
M. H. Jang, S. Joshi, H. Jiang, P. Lin, K. Norris, N. Ge, 61 K. M. Kim, J. Zhang, C. Graves, J. J. Yang, B. J. Choi,
Q. Wu, M. Barnell, Z. Li, H. L. Xin, R. S. Williams, Q. Xia C. S. Hwang, Z. Li and R. S. Williams, Nano Lett., 2016, 16,
and J. J. Yang, Adv. Mater., 2017, 29, 1604457. 6724–6732.
43 Y. Koo, S. Lee, S. Park, M. Yang and H. Hwang, IEEE Electron 62 C. Wu, T. W. Kim, H. Y. Choi, D. B. Strukov and J. J. Yang,
Device Lett., 2017, 38, 568–571. Nat. Commun., 2017, 8, 752.
44 B. Song, H. Xu, S. Liu, H. Liu and Q. Li, IEEE J. Electron 63 C. Li, L. Han, H. Jiang, M. H. Jang, P. Lin, Q. Wu, M. Barnell,
Devices Soc., 2018, 6, 674–679. J. J. Yang, H. L. Xin and Q. Xia, Nat. Commun., 2017, 8, 15666.
45 B. Song, H. Xu, S. Liu, H. Liu, Q. Liu and Q. Li, Appl. Phys. A: 64 J. Woo, D. Lee, G. Choi, E. Cha, S. Kim, W. Lee, S. Park and
Mater. Sci. Process., 2019, 125, 772. H. Hwang, Microelectron. Eng., 2013, 109, 360–363.
46 C.-H. Huang, K. Matsuzaki and K. Nomura, Appl. Phys. Lett., 65 M. Son, X. Liu, S. M. Sadaf, D. Lee, S. Park, W. Lee, S. Kim,
2020, 116, 023503. J. Park, J. Shin, S. Jung, M.-H. Ham and H. Hwang, IEEE
47 A. Chanthbouala, V. Garcia, R. O. Cheri, K. Bouzehouane, Electron Device Lett., 2012, 33, 718–720.
S. Fusil, X. Moya, S. Xavier, H. Yamada, C. Deranlot, 66 F. M. Bayat, M. Prezioso, B. Chakrabarti, H. Nili, I. Kataeva
N. D. Mathur, M. Bibes, A. Barthelemy and J. Grollier, Nat. and D. Strukov, Nat. Commun., 2018, 9, 2331.
Mater., 2012, 11, 860–864. 67 D. Kessler, M. C. Lechmann, S. Noh, R. Berger, C. Lee,
48 W. Huang, Y. W. Fang, Y. Yin, B. Tian, W. Zhao, C. Hou, J. S. Gutmann and P. Theato, Macromol. Rapid Commun.,
C. Ma, Q. Li, E. Y. Tsymbal, C. G. Duan and X. Li, ACS 2009, 30, 1238–1242.
Appl. Mater. Interfaces, 2018, 10, 5649–5656. 68 P. Kumbhare and U. Ganguly, IEEE Trans. Electron Devices,
49 B. B. Tian, J. L. Wang, S. Fusil, Y. Liu, X. L. Zhao, S. Sun, 2018, 65, 2479–2484.
H. Shen, T. Lin, J. L. Sun, C. G. Duan, M. Bibes, 69 Q. Luo, X. Zhang, Y. Hu, T. Gong, X. Xu, P. Yuan, H. Ma,
A. Barthelemy, B. Dkhil, V. Garcia, X. J. Meng and D. Dong, H. Lv, S. Long, Q. Liu and M. Liu, IEEE Electron
J. H. Chu, Nat. Commun., 2016, 7, 11502. Device Lett., 2018, 39, 664–667.
50 C. H. Huang, T. S. Chou, J. S. Huang, S. M. Lin and 70 B. Tian, P. Nukala, M. B. Hassine, X. Zhao, X. Wang, H. Shen,
Y. L. Chueh, Sci. Rep., 2017, 7, 2066. J. Wang, S. Sun, T. Lin, J. Sun, J. Ge, R. Huang, C. Duan,
51 S. Chakrabarti, S. Samanta, S. Maikap, S. Z. Rahaman and T. Reiss, M. Varela, B. Dkhil, X. Meng and J. Chu, Phys.
H. M. Cheng, Nanoscale Res. Lett., 2016, 11, 389. Chem. Chem. Phys., 2017, 19, 16960–16968.
52 M. Wang, J. Zhou, Y. Yang, S. Gaba, M. Liu and W. D. Lu, 71 M.-X. Jia, Z.-Q. Ren, Y.-D. Liu, Y. Cheng, R. Huang,
Nanoscale, 2015, 7, 4964–4970. P.-H. Xiang, X.-D. Tang, B.-B. Tian, N. Zhong and
53 Q. Luo, X. Xu, T. Gong, H. Lv, D. Dong, H. Ma, P. Yuan, C.-G. Duan, Appl. Phys. Lett., 2019, 114, 102901.
J. Gao, J. Liu, Z. Yu, J. Li, S. Long, Q. Liu and M. Liu, IEEE 72 N. Yang, Z. Q. Ren, C. Z. Hu, Z. Guan, B. B. Tian, N. Zhong,
International Electron Devices Meeting (IEDM), 2017, vol. 17, P. H. Xiang, C. G. Duan and J. H. Chu, Nanotechnology, 2019,
p. 48. 30, 464001.
54 X. Xu, Q. Luo, T. Gong, H. Lv, S. Long, Q. Liu, S. S. Chung, 73 J. H. Park, D. S. Jeon and T. G. Kim, ACS Appl. Mater.
J. Li and M. Liu, Symposium on VLSI Technology Digest of Interfaces, 2017, 9, 43336–43342.
Technical Papers, 2016.

Nanoscale Advances: Minireview

Uploaded by

Copyright:

Available Formats

Nanoscale Advances: Minireview

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Nanoscale Advances: Minireview

Uploaded by

Copyright:

Available Formats

Nanoscale

MINIREVIEW View Article Online

Research progress on solutions to the sneak path

Cite this: Nanoscale Adv., 2020, 2, 1811

Lingyun Shi,a Guohao Zheng,a Bobo Tian, *ab Brahim Dkhil b

and Chungang Duan ac

Lingyun Shi is an undergraduate Bobo Tian earned his Ph.D. in

Nanoscale Advances Minireview

basics associated with its solutions. Especially, typical and

Brahim Dkhil earned his Ph.D. Chungang Duan earned his

Minireview Nanoscale Advances

computation in articial neural networks, could be imple-

memristor crossbar.6–8 For the current domain VMM method,

Nanoscale Advances Minireview

processing and other machine learning tasks.6,13,26,27 Based on

Very recently, Wu's group demonstrated reliable and

based CNN and performed MNIST image recognition with

Minireview Nanoscale Advances

cell area of the diode and a higher integration density. Other

Some recent advances of 1D1M structures, concerning param-

88 oxide-based diode and shows uniform and stable memory

with not only conventional semiconductor processes, but also

exible memory applications. Using near-room-temperature

physical vapor deposition methods, Kyung et al. fabricated

resistance switching TiO2.33 Based on these outstanding units

whose rectication ratio is as high as 1.4 109, they demon-

strated a double-layer-stacked (4 4 2) 1D1M crossbar array,

conrming the possible route for the multi-stacked memory

It is noted that the 1D1M method prefers unipolar mem-

when the cell is reversely biased. Since the bipolar-type memory

is more appropriate in most neural networks where resistance

This makes it necessary for the diode to meet at least two

necessary requirements: (1) high forward current density and

low reverse current density as in a regular diode to guarantee

forward resistive switching and to suppress the sneak path

an ultrahigh resistance state due to the reversed series diode

unintended programming, the amplitude of the reverse

threshold voltage should be higher than the forward threshold

unit. Despite some advances of bipolar 1D1M devices,34,35 the

In a 1S1M array, a two-terminal selector device is connected to

The selector is actually a bidirectional highly nonlinear resistor.

sketched in Fig. 5a and b, the I–V curve of the 1S1M structure

Nanoscale Advances Minireview

Table 2 Partially reported 1S1M structure

Pt/TaN1+x/Ta2O5/TaN1+x/Pt, Pt/TaN1+x/Pt 103 A cm2 400  C 104 108 — 38

Minireview Nanoscale Advances

and the illuminated mechanism is shown in Fig. 7b; when

voltage sweeps back, the lament rupture event occurs due to

for example, 1010 in this Pd/Ag/HfOx/Ag/Pd case. Combining

Nanoscale Advances Minireview

Minireview Nanoscale Advances

Table 3 Partially reported single-device memristors used in crossbar arrays

Structure Mechanismsa Fabrication temperature Nonlinearity or ratiob Endurance Retention Ref.

Pt/TiO2-NRs/FTO, self-selective Interface phase transition 350  C 10 — 103 s 50

Nanoscale Advances Minireview

Minireview Nanoscale Advances

Nanoscale Advances Minireview

Minireview Nanoscale Advances

Nanoscale Advances Minireview

Pt/TaN1+x/Ta2O5/TaN1+x/Pt, Pt/TaN1+x/Pt 103 A cm2 400 C 104 108 — 38

Pt/TiO2-NRs/FTO, self-selective Interface phase transition 350 C 10 — 103 s 50