ADE Lab Manual
ADE Lab Manual
ADE Lab Manual
LAB MANUAL
18CSL37
Analog and Digital Electronics 18CSL37 III Sem
Emerge as centre of learning in the field of information science & engineering with technical
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PROGRAMME OUTCOMES
COURSE OUTCOMES
CO1 Apply the knowledge of basic gates to know the different analog and digital components
CO2 Analyze the behavior of a Analog and digital logic circuits
CO3 Design various Sequential and combinational circuits
CO4 Communicate on demonstrating the functionalities of Analog and Digital circuits.
CO5 Use modern tools for simulating analog and digital circuits.
CO PO Mapping
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
CO1 3 3 2
CO2 3 3 2
CO3 3 3 2
CO4 3 2 2 2
CO5 3 3 3 2 2
SYLLABUS
ANALOG ELECTRONICS
The vertical section controls the amplitude of the displayed signal. This section carries a
Volts-per- Division (Volts/Div) selector knob, an AC/DC/Ground selector switch and the vertical
(primary) input for the instrument. Additionally, this section is typically equipped with the
vertical beam position knob.
The horizontal section controls the time base or "sweep" of the instrument. The primary
control is the Seconds-per-Division (Sec/Div) selector switch. Also included is a horizontal input
for plotting dual X-Y axis signals. The horizontal beam position knob is generally located in this
section.
Function generators are used in the development, test and repair of electronic equipment. For
example, they may be used as a signal source to test amplifiers or to introduce an error signal
into a control loop.
Function generators, whether the old analog type or the newer digital type, have a few
common features: • A way to select a waveform type: sine, square, and triangle are most
common, but some will give ramps, pulses, ―noise‖, or allow you to program a particular
arbitrary shape. • A way to select the waveform frequency. Typical frequency ranges are from
0.01 Hz to 10 MHz. • A way to select the waveform amplitude. • At least two outputs. The
―main‖ output, which is where you find the desired waveform, typically has a maximum voltage
of 20 volts peak-to-peak, or ±10 volts range. The most common output impedance of the main
output is 50 ohms, although lower output impedances can sometimes be found. A second output,
sometimes called ―sync‖, ―aux‖ or ―TTL‖ produces a square wave with standard 0 and 5 volt
digital signal levels. It is used for synchronizing another device (such as an oscilloscope) to the
Digital circuits operate using digital, discrete signals. These circuits are usually made of a
combination of transistors and logic gates and, at higher levels, microcontrollers or other
computing chips. Most processors, whether they‘re big beefy processors in your computer, or
tiny little microcontrollers, operate in the digital realm.
Logic Design: Circuit that takes the logical decision and the process are called logic gates. Each
gate has one or more input and only one output. OR, AND and NOT are basic gates. NAND,
NOR are known as universal gates. Basic gates form these gates.
AND GATE: The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level when any one
of the inputs is low.
OR GATE: The OR gate performs a logical addition commonly known as OR function. The
output is high when any one of the inputs is high. The output is low level when both the inputs
are low.
NOT GATE: The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.
NAND GATE: The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both inputs are high.
NOR GATE: The NOR gate is a contraction of OR-NOT. The output is high when both inputs
are low. The output is low when one or both inputs are high.
X-OR GATE: The output is high when any one of the inputs is high. The output is low when
both the inputs are low and both the inputs are high.
AND GATE:
NOT GATE:
OR GATE:
X-OR GATE:
Multiplexer Multiplexer (or mux) is a device that selects one of several analog or digital input
signals and forwards the selected input into a single line. A multiplexer of 2ninputs has n select
lines, which are used to select which input line to send to the output. Multiplexers are mainly
used to increase the amount of data that can be sent over the network within a certain amount of
time and bandwidth. A multiplexer is also called a data selector. Multiplexers can also be used
to implement Boolean functions of multiple variables.
Shift register In digital circuits, a shift register is a cascade of flip flops, sharing the same clock,
in which the output of each flip-flop is connected to the data' input of the next flip-flop in the
chain, resulting in a circuit that shifts by one position the 'bit array' stored in it, ―shifting in‖ the
data present at its input and ―shifting out‖ the last bit in the array, at each transition of the clock
input.
Counter A Counter is a device which stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship to a clock signal.
1.Design an astable multivibrator ciruit for three cases of duty cycle (50%, <50% and
>50%) using NE 555 timer IC. Simulate the same for any one duty cycle.
AIM : To design and implement an Astable multivibrator using 555 Timer for a given frequency
and duty cycle.
COMPONENTS REQUIRED: 555 Timer IC, Resistors of 3.3KΩ, 6.8KΩ, Capacitors of 0.1
μF, 0.01 μF, Regulated power supply and CRO.
1. Design an Astable Multivibrator for the given frequency of 1KHZ and duty cycle of
60%.
Solution: Since the given frequency if 1KHZ,
Hence T = 1/F = 1/1KHZ = 1ms.
Duty cycle D = 60% = 60/100 = 0.6
Capacitor charging time = ton = 0.69R1C------------------ (1)
Capacitor discharging time = toff = 0.69 R2 C ----------- (2)
The Total Time is T = Ton +Toff --------------------------- (3)
The expression for Duty cycle is given by: D = Ton/T using this expression calculate for Ton
2. Design an Astable Multivibrator for the given frequency of 1KHZ and duty cycle of
50%.
Solution: Since the given frequency if 1KHZ,
Hence T = 1/F = 1/1KHZ = 1ms.
Duty cycle D = 50% = 50/100 = 0.5
Capacitor charging time = ton = 0.69R1C------------------ (1)
Capacitor discharging time = toff = 0.69 R2 C ----------- (2)
The Total Time is T = Ton +Toff --------------------------- (3)
The expression for Duty cycle is given by: D = Ton/T using this expression calculate for Ton
0.5 = Ton/1ms : Ton = 0.5 * 1ms = 0.5ms
Now calculate Toff from expression (3)
T off = T-Ton = 1ms – 0.5ms = 0.5ms
Hence Ton = 0.6 ms and Toff = 0.5ms
Now find the values of R1, R2 and C1 from expressions (1) and (2).
From (1) ton = 0.69R1C
w.k.t Ton = 0.5ms Assume C = 0.1μf ,
R1 = Ton/0.69*0.1 μf. = 7.2 KΩ
Similarly calculate for R2 from expression (2). The value of R2 = 7.2kΩ.
The Vcc determines the upper and lower threshold voltages (observed from the capacitor voltage
2 1
waveform) as V V & V V .
UT CC LT CC
3 3
Note: The duty cycle determined by R1 & R2 can vary only between 50 & 100%. If RA is much
smaller than RB, the duty cycle approaches 50%.
3. Design an Astable Multivibrator for the given frequency of 1KHZ and duty cycle of
75%.
PROCEDURE:
1. Before making the connections, check the components using multimeter.
2. Make the connections as shown in figure and switch on the power supply.
3. Observe the capacitor voltage waveform at 6th pin of 555 timer on CRO.
4. Observe the output waveform at 3rd pin of 555 timer on CRO (shown below).
5. Note down the amplitude levels, time period and hence calculate duty cycle.
WAVEFORMS
THEORY:
Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output
waveform is rectangular. The multivibrators are classified as: Astable or free running
multivibrator: It alternates automatically between two states (low and high for a rectangular
RESULTS:
Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with 50% duty cycle. and
simulate the same.
AIM : To design and implement a rectangular waveform generator (op-amp relaxation oscillator)
for a given frequency.
COMPONENTS REQUIRED:
Op-amp μA 741, Resistor of 1KΩ, 10KΩ, 20 kΩ Potentiometer, Capacitor of 0.1 μF,
Regulated DC power supply, CRO
Values
C=0.1μF
R1 = 10kΩ, R2 = 11.6
kΩ,R = 4.7k/5.1kΩ
DESIGN:
T =2RC ln (1+β/1- β ) --------- 1
Where,
β =R1/R1+ R2 is the feedback fraction
f0=1/2RC
THEORY:
Op-Amp Relaxation Oscillator is a simple Square wave generator which is also called as
a Free running oscillator or Astable multivibrator or Relaxation oscillator. In this figure the op-
amp operates in the saturation region. Here, a fraction (R2/(R1+R2)) of output is fed back to the
noninverting input terminal. Thus reference voltage is (R2/(R1+R2)) Vo. And may take values
as +(R2/(R1+R2)) Vsat or - (R2/(R1+R2)) Vsat. The output is also fed back to the inverting
input terminal after integrating by means of a low-pass RC combination. Thus whenever the
voltage at inverting input terminal just exceeds reference voltage, switching takes place resulting
in a square wave output.
0
RELAXATION OSCILLATOR
R3
10k R2
10k
V1
12v
U1
3 5
+ OS2
6
OUT
2 1
- OS1 V
V uA741
V2
12v
C1
.1uf
0
R1
0
1k
WINDOW COMPARATOR
Using ua 741 opamap, design a window comparator for any given UTP and LTP.
And simulate the same.
CIRCUIT DIAGRAM:
Solving Equations (1) and (2) for VCC, setting them equal to each other, then simplifying yields
Equation (3)
i.e. R1 = R2
To limit the current drawn from the reference voltage source, R1 and R2 were selected as 10 KΩ
While the values of R1 and R2 are related to the ratio of the window voltages, R3 determines the
voltage value. R3 is calculated in Equation (5)
. If the pull up voltage is increased, RP may have to be increased in order to obtain good
output swing to the negative rail. Notice that when the input, VIN, is between VH and VL, the output
goes to the pull-up voltage,
VP. VCC = 5V, RP = 5.1 K Ω, Vp = 10V, UTP = (2/3)VCC, LTP=(1/3)VCC
PROCEDURE:
Before doing the connections, check all the components using multimeter.
1. Make the connection as shown in circuit diagram.
2. Using a signal generator apply the sinusoidal input waveform of peak-to-peak amplitude
of 15V, frequency 1kHz.
3. Keep the CRO in dual mode; apply input (Vin) signal to the channel 1 and observe the
output (Vo) on channel 2 which is as shown in the waveform below. Note the amplitude
levels from the waveforms.
4. Now keep CRO in X-Y mode and observe the hysteresis curve.
Waveforms:
THEORY: A Window Comparator is basically the inverting and the non-inverting comparators
above combined into a single comparator stage. The window comparator detects input voltage levels
that are within a specific band or window of voltages, instead of indicating whether a voltage is greater
or less than some preset or fixed voltage reference point.
A window comparator will have two reference voltages implemented by a pair of voltage
comparators. One which triggers an op-amp comparator on detection of some upper voltage threshold,
VREF(UPPER) and one which triggers an op-amp comparator on detection of a lower voltage threshold
level, VREF(LOWER). Then the voltage levels between these two upper and lower reference voltages
is called the ―window‖, hence its name.
In the voltage divider network, if we now use three equal value resistors so that R1 = R2 = R3 =
R we can create a very simple window comparator circuit as shown. Also as the resistive values are
all equal, the voltage drops across each resistor will also be equal at one-third the supply voltage,
1/3Vcc. We can set the upper reference voltage to 2/3 Vcc and the lower reference voltage to 1/3 Vcc.
Consider the window comparator circuit below.
Result: A window comparator is designed and implemented for any given UTP and LTP
PART-B
EXPERIMENT NO. 4
Design and implement half adder, full adder, half subtractor, full subtractor using basic
gates.
AIM: Realise half adder, full adder, half subtractor, full subtractor using basic gates.
COMPONENTS REQUIRED: IC 7408, 7432, 7404, patch chords, power chords and trainer
kit.
THEORY:
An adder, also called summer, is a digital circuit that performs addition of numbers.
1. Half Adder:
It is a combinational circuit that performs the addition of two bits; this circuit needs two binary
inputs and two binary outputs, with one producing sum output and other produce carry output.
The half-adder is useful to add one binary digit quantities.
2. Full adder:
This type of adder is a little more difficult to implement than a half-adder. The main difference
between a half-adder and a full-adder is that the full-adder has three inputs and two outputs.
The first two inputs are A and B and the third input is an input carry designated as CIN. The
output
carry is designated as COUT and the normal output Sum is designated as S.
3. Half Subtractor:
A half Subtractor is a multiple output combinational logic network that does the subtraction of
two bits of binary data. It has input variables and two output variables. Two inputs are
corresponding
to two input bits and two output variables correspond to the difference bit and borrow
bit.
4. Full subtractor:
The full subtractor is a combinational circuit which is used to perform subtraction of three bits
the minuend A, subtrahend B with a carry-in C. It produces two outputs the Sum and the Carry
our to the next higher stage. Here we elect to translate the truth table to two Sum of Products
expressions and implement the Sum and Carry using AND-OR logic.
PROCEDURE:
1. Verify all the components and the patch chords whether they are in good condition or not.
Department of IS&E, BMST&M Page 25
Analog and Digital Electronics 18CSL37 III Sem
2. Make connections as shown in the circuit diagram.
3. Give power supply to the trainer kit.
4. Provide input data to the circuit via switches.
5. Record and verify the output sequence for each combination of the select lines.
HALF ADDER:
Block Diagram Truth Table
INPUTS OUTPUTS
B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
CIRCUIT DIAGRAM
Fig(A) Fig(B)
The simplified Boolean function from the truth table using SoP method is:
S = A‘B‘C + A‘BC‘ + ABC‘ + ABC Fig (C)
The simplified Boolean function from the truth table Using SoP is
C out =AB + B Cin+ Cin A Fig (C)
By simplifying the above expression using DeMorgan‘s Law we get:
Sum = A ⊕ B ⊕ C and
Carry = A.B + Cin (A +B) Fig (D)
Fig(C) Fig(D
HALF SUBTRACTOR:
D= A ⊕ B ⊕ C
__
Br= A B + B Cin + A Cin
Circuit diagram:
Results:
1. Truth table verified for :
2. Truth table verified for :
3. Truth table verified for :
4. Truth table verified for :
EXPERIMENT NO. 5
5 Given a 4-variable logic expression, simplify it using appropriate technique and realize
the simplified logic expression using 8:1 multiplexer IC. And implement the same in HDL.
AIM: To simplify the Boolean expression using Entered Variable map method and realize the
simplified logic using 8:1 MUX.
COMPONENTS REQUIRED:IC 74151/IC74153,IC7404.IC7432, patch chords, power chords
and trainer kit.
THEORY
Multiplexer sometimes is called universal logic circuit because a 2n to 1 multiplexer can be
used as a design solution for any n variable truth table. Let‘s consider A B and C variables to be
fed as select inputs, the fourth D as data input. We write all the combinations of 3 select inputs in
first row along different columns. Now corresponding to each value of 4th variable D truth table
output Y is written.The 4th column Y as a function of D.
PROCEDURE:
1 Verify all the components and the patch chords whether they are in good condition or not.
2 Make connections as shown in the circuit diagram.
3 Give power supply to the trainer kit.
4 Provide input data to the circuit via switches.
5 Record and verify the output sequence for each combination of the select lines.
PIN DIAGRAMS:
CIRCUIT DIAGRAM:
Simplify the given 4 variable Boolean expression and simplify it using 8:1 multiplexer.
Write the Verilog/VHDL code for an 8:1 multiplexer. Simulate and verify its working.
MULTIPLEX
ER
I
8 TO 1
8
3
SEL
TruthTable
INPUTS OUTPUTS
SEL (2) SEL (1) SEL (0) Zout
0 0 0 I(0)
0 0 1 I(1)
0 1 0 I(2)
0 1 1 I(3)
1 0 0 I(4)
1 0 1 I(5)
0 1 1 I(6)
1 1 1 I(7)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux1 is
Port ( I : in std_logic_vector(7 down to 0);
sel : in std_logic_vector(2 downto 0);
zout : out std_logic);
end mux1;
architecture Behavioral of mux1 is
begin
zout<= I(0) when sel="000" else
end Behavioral;
output
EXPERIMENT-6
6. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table. And
implement the same in HDL.
AIM: To realize a J-K Master/Slave FF using NAND gates and verifies its truth table
COMPONENTS REQUIRED: IC7410 three input NAND gate, IC7400 two input NAND gate,
IC7404 NOT gate, patch chords, power chords and trainer kit
THEORY: The circuit below shows the solution. To the RS flip-flop we have added two new
connections from the Q and Q' outputs back to the original input gates. Remember that a NAND
gate may have any number of inputs, so this causes no trouble. To show that we have done this,
we change the designations of the logic inputs and of the flip-flop itself. The inputs are now
designated J (instead of S) and K (instead of R). The entire circuit is known as a JK flip-flop. In
most ways, the JK flip-flop behaves just like the RS flip-flop. The Q and Q' outputs will only
change state on the falling edge of the CLK signal, and the J and K inputs will control the future
output state pretty much as before. However, there are some important differences.
Since one of the two logic inputs is always disabled according to the output state of the
overall flip-flop, the master latch cannot change state back and forth while the CLK input is at
logic 1. Instead, the enabled input can change the state of the master latch once, after which this
latch will not change again. This was not true of the RS flip-flop.
If both the J and K inputs are held at logic 1 and the CLK signal continues to change, the Q
and Q' outputs will simply change state with each falling edge of the CLK signal. (The master
latch circuit will change state with each rising edge of CLK.) We can use this characteristic to
advantage in a number of ways. A flip-flop built specifically to operate this way is typically
designated as a T (for Toggle) flip-flop. The lone T input is in fact the CLK input for other types
of flip-flops.
The JK flip-flop must be edge triggered in this manner. Any level-triggered JK latch circuit
will oscillate rapidly if all three inputs are held at logic 1. This is not very useful. For the same
Because the behavior of the JK flip-flop is completely predictable under all conditions, this is
the preferred type of flip-flop for most logic circuit designs. The RS flip-flop is only used in
applications where it can be guaranteed that both R and S cannot be logic 1 at the same time.
At the same time, there are some additional useful configurations of both latches and flip-
flops. In the next pages, we will look first at the major configurations and note their properties.
Then we will see how multiple flip-flops or latches can be combined to perform useful functions
and operations.
Master Slave Flip Flop:
The control inputs to a clocked flip flop will be making a transition at approximately the same
times as triggering edge of the clock input occurs. This can lead to unpredictable triggering.
A JK master flip flop is positive edge triggered, where as slave is negative edge triggered.
Therefore master first responds to J and K inputs and then slave. If J=0 and K=1, master resets
on arrival of positive clock edge. High output of the master drives the K input of the slave. For
the trailing edge of the clock pulse the slave is forced to reset. If both the inputs are high, it
changes the state or toggles on the arrival of the positive clock edge and the slave toggles on the
negative clock edge. The slave does exactly what the master
PIN DIAGRAMS:
0 0 Q0 Q0 No change
0 1 0 1 Reset
1 0 1 0 Set
1 1 Q0 Q0 toggle
Write the Verilog/VHDL code for D Flip-Flop with positive-edge triggering. Simulate and
verify its working
entity dflipflop is
Port ( D,Clk : in std_logic;
Q : inout std_logic;
Qbar : out std_logic);
end dflipflop;
begin
process(clk)
begin
if rising_edge(clk) then
Q<= D;
end if;
end process;
Qbar<= not Q;
end Behavioral;
7. Design and implement code converter I)Binary to Gray (II) Gray to Binary Code using
basic gates.
AIM:
COMPONENTS REQUIRED:
THEORY: The logical circuit which converts binary code to equivalent gray code is known as
binary to gray code converter. The gray code is a non weighted code. The successive gray code
differs in one bit position only that means it is a unit distance code. It is also referred as cyclic
code. It is not suitable for arithmetic operations. It is the most popular of the unit distance codes.
It is also a reflective code. An n-bit Gray code can be obtained by reflecting an n-1 bit code
about an axis after 2n-1 rows, and putting the MSB of 0 above the axis and the MSB of 1 below
the axis.
Following steps can make your idea clear on this type of conversions.
(1) The M.S.B of the binary number will be equal to the M.S.B of the given gray code.
(2) Now if the second gray bit is 0 the second binary bit will be same as the previous or the first
bit. If the gray bit is 1 the second binary bit will alter. If it was 1 it will be 0 and if it was 0 it will
be 1.
(3) This step is continued for all the bits to do Gray code to binary conversion.
In the above example the M.S.B of the binary will be 0 as the M.S.B of gray is 0. Now move to
the next gray bit. As it is 1 the previous binary bit will alter i.e. it will be 1, thus the second
binary bit will be 1.Next look at the third bit of the gray code. It is again 1 thus the previous bit
i.e the second binary bit will again alter and the third bit of the binary number will be 0. Now,
(1) The M.S.B. of the gray code will be exactly equal to the first bit of the given binary number.
(2) Now the second bit of the code will be exclusive-or of the first and second bit of the given
binary Number, i.e if both the bits are same the result will be 0 and if they are different the result
will be 1.
(3)The third bit of gray code will be equal to the exclusive-or of the second and third bit of the
given Binary number.
One example given below can make your idea clear on this type of conversion. Now concentrate
on the example where the M.S.B. of the binary is 0 so for it will be 0 for the most significant
gray bit. Next, the XOR of the first and the second bit is done. The bits are different so the
resultant gray bit will be 1. Again move to the next step, XOR of second and third bit is again 1
as they are different. Next, XOR of third and fourth bit is 0 as both the bits are same. Lastly the
XOR of fourth and fifth bit is 1 as they are different. That is how the result of binary to gray code
conversion of 01001 is done whose equivalent gray code is 01101.
PROCEDURE:
1 Verify all the components and the patch chords whether they are in good condition or not.
2 Make connections as shown in the circuit diagram.
3 Give power supply to the trainer kit.
That means, in 4 bit gray code, (4-1) or 3 bit code is reflected against the axis drawn after (24-1)th
or 8th row. The bits of 4 bit gray code are considered as G4G3G2G1. Now from conversion table,
B3 = G3
B2 = G3 ⊕ G2
B1 = B2 ⊕ G1
= (G3 ⊕ G2) ⊕ G1
B0 = B1 ⊕G0
= (G3 ⊕G2) ⊕ (G1 ⊕ G0)
CIRCUIT DIAGRAM:
Results:
1. Truth Table verified for:
2. Truth Table verified for:
EXPERIMENT-8
Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and
demonstrate its working.
By examining the four-bit binary count sequence, it noticed that just before a bit toggles,
all preceding bits are "high". That is a synchronous up-counter can be implemented by toggling
the bit when all of the less significant bits are at a logic high state. For example, bit 1 toggles
when bit 0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3 toggles when
bit 2, bit 1 and bit 0 are all high; and so on.
The ripple counter requires a finite amount of time for each flip flop to change state. This
problem can be solved by using a synchronous parallel counter where every flip flop is triggered
in synchronism with the clock, and all the output which are scheduled to change do so
simultaneously.
The counter progresses counting upwards in a natural binary sequence from count 000 to count
100 advancing count with every negative clock transition and get back to 000 after this cycle.
7476 7408
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Design and Develop the Verilog /VHDL code for Mod-8 up counter . Simulate and verify its
working.
Truth Table
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod_8 is
Port ( rst,clk,en: in std_logic;
q : inout std_logic_vector(3 downto 0));
end mod_8;
if en='1' then
Q<=Q+1;
end if;
if Q="0111" then
Q<= "0000";
end if;
end if;
end process;
end Behavioral
9. Design and implement asynchronous counter using decade counter IC to count up from 0
to n (n≤9) and demonstrate on 7- segment display using IC 7447.
AIM: To design and implement an asynchronous counter using decade counter IC to count up
from 0to (n<9)
COMPONENTS REQUIRED: IC7490,7447, patch chords, power chords and trainer kit
THEORY: Asynchronous counter is a counter in which the clock signal is connected to the
clock input of only first stage flip flop. The clock input of the second stage flip flop is triggered
by the output of the first stage flip flop and so on. This introduces an inherent propagation delay
time through a flip flop.
The 7490 is an asynchronous decade counter, able to count from 0 to 9 cyclically, and
that is its natural mode. To make 7490 to work in normal mode the pin numbers 2, 3, 6, and 7
should hold at Low state. QA, QB, QC, QD are 4 output pins which gives the binary value of the
decimal count. Pin 14 is Clock input.
Pin 2 and 3: Set inputs. They held to Low to activate 7490 IC as decade counter. At any
instant of time, if they provide High signal then the output will hold at Low state until Pin 2 and
3 brought to Low voltage.
Pin 6 and 7: Clear inputs. At any instant of time, if they provide High signal then the
output
will hold at High state until Pin 6 and 7 brought to Low voltage.
PROCEDURE:
1. Verify all the components and the patch chords whether they are in good condition or not.
2. Make connections as shown in the circuit diagram.
3. Give power supply to the trainer kit.
4. Provide input data to the circuit via switches.
5. Record and verify the output sequence for each combination of the select lines.
Clock Qa Qb Qc
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
8 1 1 1
For mod 9
connect Q0 and Q3 to reset(clear) through an AND gate. Reset should not be
connected to the switch
For mod8
Connect Q3 to reset
For mod7
Connect Q2, Q1,Q0 to reset through an And Gate
For Mod 6
Connect Q2 and Q1 to reset through an AND gate
For mod 5
Connect Q0 and Q2 to reset through an AND gate
For Mod 4
Connect Q2 to
reset For mod 3
Connect Q1 and Q0 to reset through an AND gate
For mod 2
Connect Q1 to
reset Function
It is one of most popular software tool used to synthesize VHDL code. This tool Includes
many steps. To make user feel comfortable with the tool the steps are given below:-
Double click on Project navigator. (Assumed icon is present on desktop).
Select NEW PROJECT in FILE MENU.
Enter following details as per your convenience
Project name : sample
Project location : C:\example
Top level module : HDL
In NEW PROJECT dropdown Dialog box, Choose your appropriate device specification.
Example is given below:
Device family : Spartan2
Device : xc2s200
Package : PQ208
TOP Level Module : HDL
Synthesis Tool : XST
Simulation : Modelsim / others
Generate sim lang : VHDL
In source window right click on specification, select new source
Enter the following details
Entity: sample
Architecture : Behavioral
Enter the input and output port and modes.
This will create sample.VHD source file. Click Next and finish the initial Project
preparation.
Double click on synthesis. If error occurs edit and correct VHDL code.
Double click on Lunch modelsim (or any equivalent simulator if you are using) for functional
simulation of your design.
Right click on sample.VHD in source window, select new source
Select source : Implementation constraints file.
File name : sample
Department of IS&E, BMST&M Page 54
Analog and Digital Electronics 18CSL37 III Sem
This will create sample. UCF constraints file.
Double click on Edit constraint (Text) in process window.
Edit and enter pin constraints with syntax:
NET ―NETNAME‖ LOC = ―PIN NAME‖
Double click on Implement, which will carry out translate, mapping, place and route of your
design. Also generate program file by double clicking on it, intern which will create .bit file.
Connect JTAG cable between your kit and parallel pot of your computer.
Double click on configure device and select mode in which you want to configure your
device. For ex: select slave serial mode in configuration window and finish your
configuration.
Right click on device and select ‗program‘. Verify your design giving appropriate inputs
and check for the output.
Also verify the actual working of the circuit using pattern generator & logic analyzer.
Sample Programs:
1. Write the Verilog /VHDL code for a 2 Input AND gate. Simulate and verify its
working.
Entity And1 is
Port (A, B: IN STD_LOGIC;
C: OUT STD_LOGIC);
End And1;
Architecture Behavioral of And1 is
Begin
C <= A AND B;
End Behavioral;
2. Write the Verilog /VHDL code for a half adder. Simulate and verify its working.
Entity Half_adder is
Port (A, B: IN STD_LOGIC;
SUM, CARRY: OUT STD_LOGIC);
End Half_adder;
Architecture Behavioral of Half_adder is
Begin
SUM <= A XOR B;
CARRY <= A AND B;
End Behavioral;
20. How do you realize a higher magnitude comparator using lower bit comparator?
21. Design a 2 bit comparator using a single Logic gates?
22. Design an 8 bit comparator using a two numbers of IC 7485?
23. What are the applications of decoder?
24. What is the difference between decoder & encoder?
25. For n- 2n decoder how many i/p lines & how many o/p lines?
26. Using 3:8 decoder and associated logic, implement a full adder
27. What is the difference between decoder and de-mux?
28. What are the different types of LEDs?
29. What are the applications of LEDs?
30. What is a priority encoder?
31. What is the difference between Flip-Flop & latch?
32. Give examples for synchronous & asynchronous inputs?
33. What are the applications of different Flip-Flops?
34. What is the advantage of Edge triggering over level triggering?
35. What is the relation between propagation delay & clock frequency of flip-flop?
36. What is race around in flip-flop & how to overcome it?
37. Convert the J K Flip-Flop into D flip-flop and T flip-flop
38. List the functions of asynchronous inputs?
39. What is the necessity for sequence generation?
40. What are PISO, SIPO, and SISO with respect to shift register?
41. Differentiate between serial data & parallel data
42. What is the significance of Mode control bit?
43. What is a ring counter?
44. What is a Johnson counter?
45. How many Flip-flops are present in IC 7495?
46. What is an asynchronous counter?
47. How is it different from a synchronous counter?
48. Realize asynchronous counter using T flip-flop
49. What are synchronous counters?
50. What are the advantages of synchronous counters?
51. What is an excitation table?
52. Write the excitation table for D, T FF
53. Design mod-5 synchronous counter using T FF
54. What is a presettable counter?
55. What are the applications of presettable counters?
56. Write the circuit for preset value of 0100 and N=5 (up counter)
57. What is a decade counter?
58. What do you mean by a ripple counter?