JEDEC

STANDARD

N-Channel MOSFET Hot Carrier

Data Analysis
SI

JESD28-1

SEPTEMBER 2001

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

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SI

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 JEDEC Standard No. 28-1

N-CHANNEL MOSFET HOT CARRIER DATA ANALYSIS

CONTENTS

1 Scope 1

2 Applicable Standards 1

3 Terms and Definitions 1

4 Measurement conditions and parameters 2

5 Data requirements 3

6 Analysis methodologies 3

Figures

1 Example data for substrate/drain current ratio method 5

2 Example data for drain-source voltage acceleration method 6

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3 Example data for the substrate current method 8

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JEDEC Standard No. 28-1

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 JEDEC Standard No. 28-1
Page 1

N-CHANNEL MOSFET HOT CARRIER DATA ANALYSIS

(From JEDEC Board Ballot JCB-01-47, formulated under the cognizance of the JC-14.2 Subcommittee
on Wafer-Level Reliability.)

1 Scope

The purpose of this addendum is to provide data analysis examples that may be useful in analyzing
MOSFET n-channel hot-carrier-induced degradation data. This addendum is not a standard but a
reference that suggests possible alternative hot-carrier data analysis techniques.

The examples presented in this document are restricted to dc testing. While devices are often operated
under ac or pulsed conditions, it is beyond the scope of this addendum to predict ac degradations or dc
lifetimes of integrated circuits.

The described analysis examples are restricted to devices of a single gate length and temperature.
Characterization of a semiconductor process over a wide range of gate lengths and temperatures, is
implemented by repeated use of the analysis techniques described within this addendum.

2 Applicable standards
SI

JESD-28, A Procedure for Measuring N-Channel MOSFET Hot-Carrier Induced Degradation Under DC
Stress

JESD-60, A Procedure for Measuring P-Channel MOSFET Hot-Carrier Induced Degradation at

Maximum Gate Current Under DC Stress

JESD-77A, Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelectronic
Devices

3 Terms and definitions

3.1 MOSFET Drain Stress Voltage (VDS,stress)

The voltage that is applied between the drain contact and the source contact of a MOSFET during stress.

3.2 MOSFET Gate Stress Voltage (VGS,stress)

The voltage that is applied between the gate contact and the source contact of a MOSFET during stress.

3.3 MOSFET Drain Stress Current (ID,stress)

The current at the drain contact under the MOSFET stress bias conditions VDS,stress and VGS,stress.

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JEDEC Standard No. 28-1
Page 2

3 Terms and definitions (cont’d)

3.4 MOSFET Substrate Stress Current (IB,stress)

The current at the bulk contact under the MOSFET stress bias conditions VDS,stress and VGS,stress.

3.5 MOSFET Drain Voltage at Usage Condition (VDS,use)

The drain voltage for the technology under worst case operating condition.

3.6 MOSFET Gate Voltage at Usage Condition(VGS,use)

The worst-case degradation gate voltage at VDS,use (See JESD-28).

3.7 MOSFET Drain Current at Usage Condition (ID,use)

The current at the drain contact under the MOSFET usage bias conditions VDS,use and VGS,use.

3.8 MOSFET Substrate Current at Usage Condition (IB,use)

The current at the bulk contact under the MOSFET usage bias conditions VDS,use and VGS,use.

3.9 The Specified Failure Criterion (YTAR)

The specified degradation failure criteria for a particular measured parameter.

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3.10 Time to Reach the Specified Failure Criterion (tTAR)

The elapsed time for the degradation in a particular measured parameter to reach the failure criterion
(TAR).

4 Measurement conditions and parameters

It is assumed that the hot electron measurements have been performed according to JEDEC specification
JESD-28. These analysis methods can be applied to degradations in linear transconductance (Gm),
threshold voltage (Vt), linear drain current (IDlin), saturated drain current (IDsat) or other transistor
parameters.

4.1 Stress and usage conditions

The device is to be stressed using VDS,stress and VGS,stress and the measured parameters are ID,stress
and IB,stress. ID,stress and IB,stress are the initial values of these parameters and are measured at time
equal zero during stress test.

It is also necessary to measure the usage conditions for the MOSFET. In this case the applied bias
conditions are VDS,use and VGS,use and the measured parameters are ID,use and IB,use. An identical
applied nominal bulk voltage should be the used in both the stress and usage measurements.

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 JEDEC Standard No. 28-1
Page 3

4.1 Stress and usage conditions (cont’d)

It is preferable to perform all stressing measurements on transistors with identical widths. However, it is
sometimes necessary to relate degradations in test transistors of various widths. For this reason, the
transistor width W parameter is displayed in most model equations and is not combined with other
constants.

5 Data requirements

Data collection methods are described in Section 6 of JESD-28.

For n-channel MOSFET devices the degradation data typically displays power law behavior where the
absolute value of the percentage change Y(t) in a parameter as a function of time t is given by:

|Y(t)| = Ctn (1)

A linear regression of log(|Y(t)|) versus log(t) provides the fit coefficients n and C. The time to failure
tTAR of each stressed transistor can be determined by algebraically rearranging Equation 1 to give:

1/ n
Y 
t tar =  TAR  (2)
 C 
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where YTAR is the specified degradation failure criteria.

This process is repeated for each stressed transistor, and an individual value tTAR determined.

NOTE LDD devices can saturate during stress and this possibility should be considered when performing data fits
as noted in JESD-28.

6 Analysis methodologies

There are three analysis methods commonly used. Each method has equal validity and are based on the
same carrier heating model. In this model the probability of a carrier achieving enough energy to cause
device damage is directly related to the exponent of the lateral electric field. Each analysis methodology
involves the characterization of several transistors at various stress bias conditions. The objective is to
predict the time for a certain parameter degradation at usage bias condition. The analysis methods are:

• Substrate/drain current ratio method

• Drain-source voltage acceleration method
• Substrate current method
Whichever method is chosen a 2-sided confidence interval (e.g. 80%) can be constructed about the data
set. The confidence bounds will indicate the likelihood that repeating the experiment will produce result
passing the use condition requirement. (If the confidence interval is excessively large consider increasing
the sample size of stressed units or the number of stress conditions.)
These methods are described in detail .

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JEDEC Standard No. 28-1
Page 4

6.1 Substrate/drain current ratio method

Stressing experiments are performed on a number of transistors, each at different stress bias conditions.
A minimum of three stress conditions, with at least five transistors per stress condition is required. For
each transistor, the stress conditions are VDS,stress and VGS,stress and the following parameters are
obtained:

tTAR; YTAR; ID,stress; IB,stress; ID,use; IB,use and n.

The failure time model is given by

−m
I 
ttar I D , stress = HW  B , stress  (3)
 I D , stress 

where H and m are fit parameters and W is the transistor width. If measurements are performed on
transistors of equal width, then the quantity W can be combined with the fit parameter H. Rearranging
Equation 3 gives:

−m
ttar I D , stress I 
= H  B , stress  (4)
W  I D , stress 

Taking the logarithm of both sides of Equation 4 yields:

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t I  I 
log tar D , stress  = log H − m × log B , stress  (5)
 W   I D , stress 

A linear regression analysis is performed to obtain fit parameters H and m. Figure 1 displays a plot of this
relationship. According to theory, m should be 3, but values may vary depending on stress conditions and
technology. In a stress experiment with typical stress bias voltage conditions, a moderate variation in
IB,stress/ID, stress results in a large variation in failure times, tTAR. The quantity on the left hand side of
Equation 5 is thus dominated by the failure times tTAR with other terms relatively constant.

Once the constants H and m are determined, the time to failure at usage condition is estimated using
Equation 4 to give:

−m
1  I B , use 
ttar ,use = HW (6)
I D , use  I D ,use 

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 JEDEC Standard No. 28-1
Page 5

6.1 Substrate/drain current ratio method (cont’d)

VDS,stress = 6.5V

 ttarID , stress  7.0V

log
 W 

7.5V

8.0V
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 IB , stress 
log 
 ID , stress 
Figure 1 — Example data for substrate/drain current ratio method

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JEDEC Standard No. 28-1
Page 6

6.2 Drain-source voltage acceleration method

In this method the stress is performed on a number of transistors, each at a different stress condition
VDS,stress and VGS,stress. For each transistor, the time to reach the failure criteria is obtained (ttar):

The time to failure is given by:

 B 
t tar = t o exp  (7)
 V DS , stress 

where to and B are fit parameters. Figure 2 displays a typical plot showing this relationship. Taking the
natural logarithm of both sides of Equation 7 yields the following relationship:

 1 
ln t tar = ln t o + B  (8)
 V DS ,stress 

A linear regression analysis of Equation 8 yields the fit coefficients to and B. The failure time ttar,use at
usage bias conditions is found by substituting VDS,use for VDS,stress in Equation 8.
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log(tTAR)

1
VD,stress

Figure 2 — Example data for drain-source voltage acceleration method

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 JEDEC Standard No. 28-1
Page 7

6.3 Substrate current method

Again stress experiments are performed on a number of transistors, each at a different stress bias
condition. For each transistor, the stress conditions are VDS,stress and VGS,stress and the following
parameters are obtained:

ttar; IB,stress and IB,use.

The time to failure is given by

−b
 I B ,stress 
t tar = C  (9)
 W 

where C and b are fit parameters, and W is the transistor width. Figure 3 displays this relationship.
Taking the logarithm of both sides of Equation 9 yields the following:

 I B ,stress 
log t tar = log C − b ⋅ log  (10)
 W 

Again a linear regression is performed on Equation 10 to obtain the fit coefficients C and b.

The time to failure at usage bias conditions is found from

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−b
 I B ,use 
t tar ,use = C  (11)
 W 

where IB,use/W in brackets is the substrate current per unit width at the usage condition averaged over the
number of stressed transistors.

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JEDEC Standard No. 28-1
Page 8

6.3 Substrate current method (cont’d)

log(tTAR)

)
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 IB, stress 
log 
 W 
Figure 3 — Example data for the substrate current method

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 SI

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 SI

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